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[ScratchNES.git] / src / CPU /
2017-01-22 Alyssa RosenzweigRemove debug cruft
2016-09-10 Alyssa RosenzweigFix INC/DEC bug
2016-07-13 Alyssa RosenzweigBugs
2016-07-07 Alyssa RosenzweigFix negative flag on compare
2016-07-07 Alyssa RosenzweigPad hex (probably fixes multiple bugs)
2016-07-07 Alyssa RosenzweigSimilar bugs as last commit
2016-07-07 Alyssa RosenzweigSubtle tosh bug
2016-07-07 Alyssa RosenzweigPHP subtlety
2016-07-07 Alyssa RosenzweigDon't try to emit nonexistant common
2016-07-07 Alyssa RosenzweigFix BIT instruction
2016-07-07 Alyssa RosenzweigCommon code should not be part of build-cpu
2016-07-07 Alyssa Rosenzweigdebugging common code
2016-07-06 Alyssa Rosenzweigimprove common
2016-07-06 Alyssa Rosenzweigfix bug with DEC
2016-07-06 Alyssa RosenzweigFix indirect,x
2016-07-05 Alyssa RosenzweigFixes
2016-07-05 Alyssa RosenzweigMaybe fix CP* instructions
2016-07-05 Alyssa RosenzweigCPU bugfix start -- ADC/SBC
2016-07-05 Alyssa RosenzweigJump to reset vector
2016-07-05 Alyssa RosenzweigCarry flag bugfix in SBC
2016-07-05 Alyssa RosenzweigImprove common code
2016-07-05 Alyssa RosenzweigFix (indirect),Y
2016-07-04 Alyssa RosenzweigForgot I left those in -- woohoo massive boost :D
2016-07-04 Alyssa RosenzweigAdjacent pixel optimization yields like 2x performance :D
2016-07-04 Alyssa RosenzweigTrying optimizations?
2016-07-03 Alyssa RosenzweigOptimize background emission (the usual case)
2016-07-02 Alyssa RosenzweigFix broken compare instructions
2016-07-02 Alyssa RosenzweigBitmask table
2016-07-02 Alyssa RosenzweigUpdate common to reflect last commit
2016-07-02 Alyssa RosenzweigDon't use temp opcode
2016-07-02 Alyssa RosenzweigWrong register for controllers
2016-07-02 Alyssa RosenzweigInline SR
2016-07-02 Alyssa RosenzweigAdjustment
2016-07-02 Alyssa RosenzweigPrioritize instructions
2016-07-02 Alyssa RosenzweigNo more says
2016-07-02 Alyssa RosenzweigSmall bug
2016-07-02 Alyssa RosenzweigNROM mapper support for controllers
2016-07-02 Alyssa RosenzweigFix longstanding error
2016-06-30 Alyssa RosenzweigCPU verbosity is no longer desired
2016-06-30 Alyssa RosenzweigOptimize a few frame things
2016-06-30 Alyssa RosenzweigEndianness of RTI
2016-06-30 Alyssa RosenzweigRTIs work now :D
2016-06-30 Alyssa RosenzweigPush the right number of bits :P
2016-06-30 Alyssa RosenzweigDMA register
2016-06-30 Alyssa RosenzweigFix RTI maybe
2016-06-30 Alyssa RosenzweigMore control stubs
2016-06-30 Alyssa RosenzweigPPU registers in the memory map
2016-06-30 Alyssa RosenzweigExplicit CPU step
2016-06-30 Alyssa Rosenzweighex, for now
2016-06-30 Alyssa RosenzweigUpdate BRK to use new interrupt code
2016-06-30 Alyssa RosenzweigImplement interrupts
2016-06-29 Alyssa RosenzweigSolve some issues discovered during CPU/PPU integration
2016-06-29 Alyssa RosenzweigDump common code in build-cpu.js
2016-06-29 Alyssa RosenzweigPrepare for a cleaner build system
2016-06-29 Alyssa Rosenzweigbin
2016-06-29 Alyssa RosenzweigForgot to check these in
2016-06-29 Alyssa RosenzweigNew tools folder
2016-06-29 Alyssa RosenzweigPLP; compute SR
2016-06-29 Alyssa RosenzweigFix bitwise ops
2016-06-29 Alyssa RosenzweigFix RTS endianness
2016-06-29 Alyssa RosenzweigWrong order transfer
2016-06-26 Alyssa RosenzweigNTSC Box -- experiments with aggressive optimizations
2016-06-23 Alyssa RosenzweigDon't advance in JSR
2016-06-23 Alyssa RosenzweigFix bitwise
2016-06-23 Alyssa RosenzweigImprove meta
2016-06-23 Alyssa RosenzweigMeta file
2016-06-23 Alyssa RosenzweigRemove old meta tosh
2016-06-23 Alyssa RosenzweigTableify
2016-06-23 Alyssa RosenzweigBuild lookup tables
2016-06-23 Alyssa RosenzweigSwitch endian, maybe
2016-06-23 Alyssa Rosenzweigthe pause is annoying
2016-06-23 Alyssa RosenzweigMissed a line in indirect
2016-06-23 Alyssa RosenzweigFix
2016-06-23 Alyssa RosenzweigMaybe fix branching / jmp?
2016-06-23 Alyssa RosenzweigFix some flags
2016-06-23 Alyssa RosenzweigINC operand
2016-06-23 Alyssa RosenzweigSpecify BIT operand; synatx error
2016-06-23 Alyssa RosenzweigParse the other flags
2016-06-23 Alyssa RosenzweigCarry flag -- also I might have bugs with not implement...
2016-06-23 Alyssa RosenzweigW mode
2016-06-23 Alyssa RosenzweigRAW mode
2016-06-23 Alyssa RosenzweigBIT
2016-06-23 Alyssa RosenzweigLet's do the whole CPU :D
2016-06-23 Alyssa RosenzweigWoohoo :D ASL A works, and the flag setting is correct
2016-06-23 Alyssa RosenzweigNegative and zero flag handling
2016-06-23 Alyssa RosenzweigAccumulator modes kind of break things :P
2016-06-23 Alyssa Rosenzweiglet RW do something
2016-06-23 Alyssa RosenzweigRW
2016-06-23 Alyssa RosenzweigImprove code generation
2016-06-23 Alyssa RosenzweigParse flags
2016-06-23 Alyssa RosenzweigContinue code emission
2016-06-23 Alyssa RosenzweigContinue modernization
2016-06-23 Alyssa RosenzweigModernize instruction set to be hexless
2016-06-23 Alyssa RosenzweigMakefile
2016-06-23 Alyssa RosenzweigAutomate bitwise
2016-06-23 Alyssa RosenzweigI'm changing the format -- this is insanity
2016-06-23 Alyssa RosenzweigWork on emulator, misc.
2016-06-23 Alyssa RosenzweigUpdate README
2016-06-23 Alyssa RosenzweigBegin working on actual instruction emission
2016-06-23 Alyssa RosenzweigSo, now I have a (working) disassembler thingy
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