2016-07-02 Alyssa RosenzweigFix PPU VRAM address convention; nametables
2016-07-02 Alyssa RosenzweigTrying to wrap my head around scrolling
2016-07-01 Alyssa RosenzweigFix a few pattern table bugs
2016-07-01 Alyssa RosenzweigPattern tables :D[
2016-07-01 Alyssa RosenzweigPPU standalone support files
2016-07-01 Alyssa RosenzweigFix slight graphical glitch with PPU
2016-07-01 Alyssa RosenzweigBegin reworking the PPU
2016-06-30 Alyssa RosenzweigCPU verbosity is no longer desired
2016-06-30 Alyssa RosenzweigGreat pipelining effect :P
2016-06-30 Alyssa RosenzweigOptimize a few frame things
2016-06-30 Alyssa RosenzweigIT WORKS :D
2016-06-30 Alyssa RosenzweigFix OAM DMA
2016-06-30 Alyssa RosenzweigEndianness of RTI
2016-06-30 Alyssa RosenzweigRTIs work now :D
2016-06-30 Alyssa RosenzweigPush the right number of bits :P
2016-06-30 Alyssa RosenzweigDMA register
2016-06-30 Alyssa RosenzweigFix RTI maybe
2016-06-30 Alyssa RosenzweigMore control stubs
2016-06-30 Alyssa RosenzweigPPU registers in the memory map
2016-06-30 Alyssa RosenzweigHBlank isn't VBlank; the clock still ticks without...
2016-06-30 Alyssa RosenzweigNaming conflict between CPU index registers and PPU...
2016-06-30 Alyssa RosenzweigExplicit CPU step
2016-06-30 Alyssa Rosenzweighex, for now
2016-06-30 Alyssa RosenzweigStep cycles in VBlank
2016-06-30 Alyssa RosenzweigPreliminary CPU stepping code
2016-06-30 Alyssa RosenzweigFurther refactoring
2016-06-30 Alyssa RosenzweigUse 3 pixel borders so I can do a timing trick on NTSC
2016-06-30 Alyssa RosenzweigGenerate VBlank interrupt
2016-06-30 Alyssa RosenzweigUpdate BRK to use new interrupt code
2016-06-30 Alyssa RosenzweigImplement interrupts
2016-06-29 Alyssa RosenzweigEmulator shell (blob)
2016-06-29 Alyssa RosenzweigSolve some issues discovered during CPU/PPU integration
2016-06-29 Alyssa RosenzweigFix build script
2016-06-29 Alyssa RosenzweigDon't use extra directory
2016-06-29 Alyssa RosenzweigBuild emulator
2016-06-29 Alyssa Rosenzweigupdate the README
2016-06-29 Alyssa RosenzweigDump common code in build-cpu.js
2016-06-29 Alyssa RosenzweigPrepare for a cleaner build system
2016-06-29 Alyssa Rosenzweigbin
2016-06-29 Alyssa RosenzweigForgot to check these in
2016-06-29 Alyssa RosenzweigProper PPU
2016-06-29 Alyssa RosenzweigTrivial tool to rip PRG from NROM .nes files
2016-06-29 Alyssa RosenzweigNew tools folder
2016-06-29 Alyssa RosenzweigPLP; compute SR
2016-06-29 Alyssa RosenzweigLine counting; PC at 0xC000 for CPU testing
2016-06-29 Alyssa RosenzweigUpdate meta CPU
2016-06-29 Alyssa RosenzweigFix bitwise ops
2016-06-29 Alyssa RosenzweigFix RTS endianness
2016-06-29 Alyssa RosenzweigWrong order transfer
2016-06-29 Alyssa RosenzweigLog PPU register writes
2016-06-29 Alyssa RosenzweigWrite PPU memory
2016-06-29 Alyssa RosenzweigRead PPU memory
2016-06-28 Alyssa RosenzweigPPU registers emulation
2016-06-28 Alyssa RosenzweigPretty colors
2016-06-28 Alyssa RosenzweigSprite evaluation
2016-06-27 Alyssa RosenzweigMIsc updates to the NTSC box
2016-06-26 Alyssa RosenzweigSqueeze the NTSC box
2016-06-26 Alyssa RosenzweigNTSC Box -- experiments with aggressive optimizations
2016-06-24 Alyssa RosenzweigUnoptimized disco
2016-06-24 Alyssa Rosenzweigreadmeplz
2016-06-24 Alyssa RosenzweigSR register
2016-06-23 Alyssa RosenzweigMisc changes to meta
2016-06-23 Alyssa RosenzweigDon't advance in JSR
2016-06-23 Alyssa RosenzweigFix bitwise
2016-06-23 Alyssa RosenzweigImprove meta
2016-06-23 Alyssa RosenzweigContinue shell
2016-06-23 Alyssa RosenzweigMeta file
2016-06-23 Alyssa RosenzweigRemove old meta tosh
2016-06-23 Alyssa RosenzweigTableify
2016-06-23 Alyssa RosenzweigBuild lookup tables
2016-06-23 Alyssa RosenzweigSwitch endian, maybe
2016-06-23 Alyssa Rosenzweigthe pause is annoying
2016-06-23 Alyssa RosenzweigMissed a line in indirect
2016-06-23 Alyssa RosenzweigFix
2016-06-23 Alyssa RosenzweigMaybe fix branching / jmp?
2016-06-23 Alyssa RosenzweigFix some flags
2016-06-23 Alyssa RosenzweigINC operand
2016-06-23 Alyssa RosenzweigSpecify BIT operand; synatx error
2016-06-23 Alyssa RosenzweigParse the other flags
2016-06-23 Alyssa RosenzweigCarry flag -- also I might have bugs with not implement...
2016-06-23 Alyssa RosenzweigW mode
2016-06-23 Alyssa RosenzweigRAW mode
2016-06-23 Alyssa RosenzweigBIT
2016-06-23 Alyssa RosenzweigLet's do the whole CPU :D
2016-06-23 Alyssa RosenzweigWoohoo :D ASL A works, and the flag setting is correct
2016-06-23 Alyssa RosenzweigNegative and zero flag handling
2016-06-23 Alyssa RosenzweigAccumulator modes kind of break things :P
2016-06-23 Alyssa Rosenzweiglet RW do something
2016-06-23 Alyssa RosenzweigRW
2016-06-23 Alyssa RosenzweigImprove code generation
2016-06-23 Alyssa RosenzweigParse flags
2016-06-23 Alyssa RosenzweigContinue code emission
2016-06-23 Alyssa RosenzweigContinue modernization
2016-06-23 Alyssa RosenzweigModernize instruction set to be hexless
2016-06-23 Alyssa RosenzweigMakefile
2016-06-23 Alyssa RosenzweigAutomate bitwise
2016-06-23 Alyssa RosenzweigI'm changing the format -- this is insanity
2016-06-23 Alyssa RosenzweigWork on emulator, misc.
2016-06-23 Alyssa RosenzweigUpdate README
2016-06-23 Alyssa RosenzweigBegin working on actual instruction emission
This page took 0.057278 seconds and 4 git commands to generate.