2018-03-05 Alyssa RosenzweigPartial decode of fb fields master
2018-03-05 Alyssa RosenzweigFlip filter/raw
2018-03-05 Alyssa Rosenzweigunknown7 should always be 1, I think
2018-03-05 Alyssa RosenzweigTexture opcodes?
2018-03-05 Alyssa RosenzweigCont/last/format
2018-03-05 Alyssa RosenzweigRemove comments for the simplest texture instructions
2018-03-05 Alyssa Rosenzweighconstants
2018-03-05 Alyssa RosenzweigAdd authorship
2018-03-05 Alyssa RosenzweigClarify unknownB
2018-03-05 Alyssa RosenzweigRemove whitespace
2018-03-05 Alyssa Rosenzweigin_reg_full
2018-03-05 Alyssa RosenzweigFilter bit, in_reg_upper bit
2018-03-05 Alyssa RosenzweigYou're the 1 that I want (00, 00, 00)... 0 yes indeed...
2018-03-05 Alyssa RosenzweigFix swizzle location
2018-03-05 Alyssa RosenzweigCorrect comma palcement
2018-03-05 Alyssa RosenzweigExpand out what little we know of offset fields
2018-03-04 Alyssa RosenzweigTexture words are properly decoded now
2018-03-04 Alyssa RosenzweigUnknown offset field... (TODO: Decode X_X)
2018-03-04 Alyssa RosenzweigContinue embedded constant type analysis
2018-03-04 Alyssa RosenzweigBegin constant static analysis
2018-03-04 Alyssa RosenzweigHas offset bit
2018-03-04 Alyssa RosenzweigIdentify shadow bit
2018-03-04 Alyssa RosenzweigNote LOD usage
2018-03-04 Alyssa RosenzweigNew texture word type
2018-03-04 Alyssa RosenzweigIdentify bias
2018-03-04 Alyssa RosenzweigOutput full printing is redunant
2018-03-04 Alyssa RosenzweigIn reg swizzle
2018-03-04 Alyssa RosenzweigIdentify out_full bit
2018-03-04 Alyssa RosenzweigInput register selection
2018-03-04 Alyssa RosenzweigSwizzle/mask were printed in the wrong place
2018-03-04 Alyssa RosenzweigIdentify texture mask
2018-03-04 Alyssa RosenzweigTexture output swizzle
2018-03-04 Alyssa RosenzweigOutput register name directly
2018-03-04 Alyssa RosenzweigBreak up into out reg select and out upper
2018-03-04 Alyssa RosenzweigBegin initial disassembly of texture words
2018-02-27 Alyssa RosenzweigPrint modifiers as instruction triplets
2018-02-27 Alyssa RosenzweigCleanup
2018-02-27 Alyssa RosenzweigFix tabs
2018-02-26 Alyssa RosenzweigSingle header for panwrap integration
2018-02-25 Alyssa RosenzweigPrefix #immediates
2018-02-23 Alyssa RosenzweigAdd commas
2018-02-23 Alyssa RosenzweigOffset in frontend
2018-02-23 Alyssa RosenzweigHandle degenerate mask case
2018-02-23 Alyssa RosenzweigConstants as instruction
2018-02-23 Alyssa RosenzweigRemove spacing
2018-02-23 Alyssa RosenzweigTexture on one line
2018-02-23 Alyssa RosenzweigPrefix scalar too
2018-02-23 Alyssa Rosenzweigfbwrite as actual word
2018-02-23 Alyssa RosenzweigPrefix ins names with unit
2018-02-23 Alyssa RosenzweigExplicit ALU debug condition
2018-02-23 Alyssa Rosenzweigasm_replay constant
2018-02-23 Alyssa RosenzweigMake load/store output a little more assembler like
2018-02-23 Alyssa RosenzweigRemove known human instruction prefixes
2018-02-23 Alyssa RosenzweigPrefetch flag-based break
2018-02-23 Alyssa RosenzweigRemove most of the disasm main logic
2018-01-25 Alyssa RosenzweigDisassemble from raw file
2018-01-24 Alyssa RosenzweigRemove t650 since it's identical afaict
2018-01-24 Alyssa RosenzweigForce midgard
2018-01-24 Alyssa RosenzweigRemove mbs support
2018-01-24 Alyssa RosenzweigRemove ir
2018-01-24 Alyssa RosenzweigRemove non-Midgard arches
2018-01-24 Alyssa RosenzweigStrip more
2018-01-24 Alyssa RosenzweigGet it to build
2014-02-22 Connor Abbottpp_hir: add support for shifts
2014-02-22 Connor Abbottmbs: print VIDX correctly
2014-02-03 Connor Abbottpp_lir: add support for multiply shifts
2014-02-03 Connor Abbottpp_lir: fix codegen bug
2014-02-03 Connor Abbottt6xx: add all and any opcodes
2014-02-03 Connor Abbottadd missing file
2014-01-19 Connor Abbottt6xx: add integer move instruction
2014-01-19 Connor Abbottt6xx: add initial load/store disassembly
2013-11-29 Connor Abbottt6xx: s/lima_t6xx_op/lima_t6xx_alu_op/
2013-10-26 Connor Abbottt6xx: be more annoying about unknown things
2013-10-26 Connor Abbottt6xx: add dest override
2013-10-13 Connor Abbottt6xx: add more opcodes
2013-10-13 Connor Abbottt6xx: add atan opcodes
2013-10-01 Connor AbbottMerge branch 't6xx'
2013-09-30 Connor Abbottforgot to add these
2013-08-02 Connor Abbottt6xx: add initial ALU field disassembly
2013-07-22 Connor Abbottt6xx: start to parse ALU word
2013-07-20 Connor Abbottt6xx: add 0xB word type
2013-07-14 Connor Abbottt6xx: parse instruction words
2013-07-13 Connor Abbottlima: add initial skeleton for t6xx
2013-07-13 Connor Abbottptrset: add ptrset_first() and use it
2013-07-13 Connor Abbottptrset: create ptrset_iter_for_each() macro
2013-07-13 Connor Abbottrename ptrset_iterator to ptrset_iter
2013-07-11 Connor Abbottptrset: don't allocate ptrset objects on the heap
2013-07-11 Connor Abbottptrset: reduce the MAX_LOAD to .7
2013-07-11 Connor Abbottptrset: rewrite to use open-coding
2013-07-11 Connor Abbottgp_ir: fix memory errors found by the new ptrset
2013-07-11 Connor Abbottmake ptrsets dynamically sized
2013-07-11 Connor Abbottgp_ir: add register spilling
2013-07-11 Connor Abbottgp_ir: be more paranoid in to_ssa
2013-07-11 Connor Abbottgp_ir: fix a bug with generating temp dependencies
2013-07-11 Connor Abbottgp_ir: fix a subtle bug with ordering root nodes
2013-07-11 Connor Abbottgp_ir: fix another bug with dce
2013-07-10 Connor Abbottgp_ir: fix bug that could result in an infinite loop...
2013-07-10 Connor Abbottgp_ir: add support for parsing temporary offsets
2013-07-10 Connor Abbottgp_ir: add simple test for temporaries
2013-07-10 Connor Abbottgp_ir: add a temp_alloc parameter
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