add basic secure monitor code for armv7+, for some reason sdram security does not...
[rpi-open-firmware.git] / arm_chainloader / chainloader.h
1 #pragma once
2
3 #include <lib/runtime.h>
4 #include <stdint.h>
5 #include <stddef.h>
6 #include <memory_map.h>
7
8 #ifdef __cplusplus
9 extern "C" {
10 #endif
11
12 static inline void __attribute__((noreturn)) hang_cpu() {
13 __asm__ __volatile__ (
14 "wfi\n"
15 );
16
17 /* in case the above fails */
18 for (;;) {
19 __asm__ __volatile__ ("nop\nnop\nnop\nnop\nnop\nnop");
20 }
21 }
22
23 #define STATIC_INIT_PRIORITY(x) __attribute__((init_priority(x)))
24
25 #define STATIC_CPRMAN_DRIVER STATIC_INIT_PRIORITY(101)
26 #define STATIC_DRIVER STATIC_INIT_PRIORITY(200)
27 #define STATIC_FILESYSTEM STATIC_INIT_PRIORITY(300)
28 #define STATIC_APP STATIC_INIT_PRIORITY(600)
29
30 #define mfence() __sync_synchronize()
31
32 #define NBBY 8
33
34 #define __BIT(__n) \
35 (((uintmax_t)(__n) >= NBBY * sizeof(uintmax_t)) ? 0 : \
36 ((uintmax_t)1 << (uintmax_t)((__n) & (NBBY * sizeof(uintmax_t) - 1))))
37
38 static inline uint32_t arm_get_cpsr() {
39 uint32_t r;
40 __asm__ volatile("mrs %0, cpsr\n" : "=r" (r) :: "memory");
41 return r;
42 }
43
44 #define ARM32_MODE_MASK 0x1f
45 #define ARM32_USR 0x10
46 #define ARM32_FIQ 0x11
47 #define ARM32_IRQ 0x12
48 #define ARM32_SVC 0x13
49 #define ARM32_MON 0x16
50 #define ARM32_ABT 0x17
51 #define ARM32_HYP 0x1a
52 #define ARM32_UND 0x1b
53 #define ARM32_SYS 0x1f
54
55 #ifdef __cplusplus
56 }
57 #endif
58
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