Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / arm_chainloader / drivers / sd_proto.hpp
1 /* $NetBSD: sdmmcreg.h,v 1.21 2015/10/29 22:37:15 jmcneill Exp $ */
2 /* $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <limits.h>
21
22 #pragma once
23
24 /* MMC commands */ /* response type */
25 #define MMC_GO_IDLE_STATE 0 /* R0 */
26 #define MMC_SEND_OP_COND 1 /* R3 */
27 #define MMC_ALL_SEND_CID 2 /* R2 */
28 #define MMC_SET_RELATIVE_ADDR 3 /* R1 */
29 #define MMC_SWITCH 6 /* R1b */
30 #define MMC_SELECT_CARD 7 /* R1 */
31 #define MMC_SEND_EXT_CSD 8 /* R1 */
32 #define MMC_SEND_CSD 9 /* R2 */
33 #define MMC_SEND_CID 10 /* R2 */
34 #define MMC_STOP_TRANSMISSION 12 /* R1b */
35 #define MMC_SEND_STATUS 13 /* R1 */
36 #define MMC_INACTIVE_STATE 15 /* R0 */
37 #define MMC_SET_BLOCKLEN 16 /* R1 */
38 #define MMC_READ_BLOCK_SINGLE 17 /* R1 */
39 #define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */
40 #define MMC_SEND_TUNING_BLOCK 19 /* R1 */
41 #define MMC_SEND_TUNING_BLOCK_HS200 21 /* R1 */
42 #define MMC_SET_BLOCK_COUNT 23 /* R1 */
43 #define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */
44 #define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */
45 #define MMC_PROGRAM_CSD 27 /* R1 */
46 #define MMC_SET_WRITE_PROT 28 /* R1b */
47 #define MMC_SET_CLR_WRITE_PROT 29 /* R1b */
48 #define MMC_SET_SEND_WRITE_PROT 30 /* R1 */
49 #define MMC_TAG_SECTOR_START 32 /* R1 */
50 #define MMC_TAG_SECTOR_END 33 /* R1 */
51 #define MMC_UNTAG_SECTOR 34 /* R1 */
52 #define MMC_TAG_ERASE_GROUP_START 35 /* R1 */
53 #define MMC_TAG_ERASE_GROUP_END 36 /* R1 */
54 #define MMC_UNTAG_ERASE_GROUP 37 /* R1 */
55 #define MMC_ERASE 38 /* R1b */
56 #define MMC_LOCK_UNLOCK 42 /* R1b */
57 #define MMC_APP_CMD 55 /* R1 */
58 #define MMC_READ_OCR 58 /* R3 */
59
60 /* SD commands */ /* response type */
61 #define SD_SEND_RELATIVE_ADDR 3 /* R6 */
62 #define SD_SEND_SWITCH_FUNC 6 /* R1 */
63 #define SD_SEND_IF_COND 8 /* R7 */
64 #define SD_VOLTAGE_SWITCH 11 /* R1 */
65
66 /* SD application commands */ /* response type */
67 #define SD_APP_SET_BUS_WIDTH 6 /* R1 */
68 #define SD_APP_SD_STATUS 13 /* R1 */
69 #define SD_APP_OP_COND 41 /* R3 */
70 #define SD_APP_SEND_SCR 51 /* R1 */
71
72 /* OCR bits */
73 #define MMC_OCR_MEM_READY (1U<<31)/* memory power-up status bit */
74 #define MMC_OCR_HCS (1<<30) /* SD only */
75 #define MMC_OCR_ACCESS_MODE_MASK (3<<29) /* MMC only */
76 #define MMC_OCR_ACCESS_MODE_BYTE (0<<29) /* MMC only */
77 #define MMC_OCR_ACCESS_MODE_SECTOR (2<<29) /* MMC only */
78 #define MMC_OCR_S18A (1<<24)
79 #define MMC_OCR_3_5V_3_6V (1<<23)
80 #define MMC_OCR_3_4V_3_5V (1<<22)
81 #define MMC_OCR_3_3V_3_4V (1<<21)
82 #define MMC_OCR_3_2V_3_3V (1<<20)
83 #define MMC_OCR_3_1V_3_2V (1<<19)
84 #define MMC_OCR_3_0V_3_1V (1<<18)
85 #define MMC_OCR_2_9V_3_0V (1<<17)
86 #define MMC_OCR_2_8V_2_9V (1<<16)
87 #define MMC_OCR_2_7V_2_8V (1<<15)
88 #define MMC_OCR_2_6V_2_7V (1<<14)
89 #define MMC_OCR_2_5V_2_6V (1<<13)
90 #define MMC_OCR_2_4V_2_5V (1<<12)
91 #define MMC_OCR_2_3V_2_4V (1<<11)
92 #define MMC_OCR_2_2V_2_3V (1<<10)
93 #define MMC_OCR_2_1V_2_2V (1<<9)
94 #define MMC_OCR_2_0V_2_1V (1<<8)
95 #define MMC_OCR_1_9V_2_0V (1<<7)
96 #define MMC_OCR_1_8V_1_9V (1<<6)
97 #define MMC_OCR_1_7V_1_8V (1<<5)
98 #define MMC_OCR_1_6V_1_7V (1<<4)
99
100 /* R1 response type bits */
101 #define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */
102 #define MMC_R1_SWITCH_ERROR (1<<7) /* switch command failed */
103 #define MMC_R1_APP_CMD (1<<5) /* app. commands supported */
104
105 /* 48-bit response decoding (32 bits w/o CRC) */
106 #define MMC_R1(resp) ((resp)[0])
107 #define MMC_R3(resp) ((resp)[0])
108 #define SD_R6(resp) ((resp)[0])
109 #define MMC_R7(resp) ((resp)[0])
110 #define MMC_SPI_R1(resp) ((resp)[0])
111 #define MMC_SPI_R7(resp) ((resp)[1])
112
113 /* RCA argument and response */
114 #define MMC_ARG_RCA(rca) ((rca) << 16)
115 #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16)
116
117 /* bus width argument */
118 #define SD_ARG_BUS_WIDTH_1 0
119 #define SD_ARG_BUS_WIDTH_4 2
120
121 /* EXT_CSD fields */
122 #define EXT_CSD_BUS_WIDTH 183 /* WO */
123 #define EXT_CSD_HS_TIMING 185 /* R/W */
124 #define EXT_CSD_REV 192 /* RO */
125 #define EXT_CSD_STRUCTURE 194 /* RO */
126 #define EXT_CSD_CARD_TYPE 196 /* RO */
127 #define EXT_CSD_SEC_COUNT 212 /* RO */
128
129 /* EXT_CSD field definitions */
130 #define EXT_CSD_CMD_SET_NORMAL (1U << 0)
131 #define EXT_CSD_CMD_SET_SECURE (1U << 1)
132 #define EXT_CSD_CMD_SET_CPSECURE (1U << 2)
133
134 /* EXT_CSD_BUS_WIDTH */
135 #define EXT_CSD_BUS_WIDTH_1 0 /* 1 bit mode */
136 #define EXT_CSD_BUS_WIDTH_4 1 /* 4 bit mode */
137 #define EXT_CSD_BUS_WIDTH_8 2 /* 8 bit mode */
138
139 /* EXT_CSD_STRUCTURE */
140 #define EXT_CSD_STRUCTURE_VER_1_0 0 /* CSD Version No.1.0 */
141 #define EXT_CSD_STRUCTURE_VER_1_1 1 /* CSD Version No.1.1 */
142 #define EXT_CSD_STRUCTURE_VER_1_2 2 /* Version 4.1-4.2-4.3 */
143
144 /* EXT_CSD_CARD_TYPE */
145 #define EXT_CSD_CARD_TYPE_F_26M (1 << 0)
146 #define EXT_CSD_CARD_TYPE_F_52M (1 << 1)
147 #define EXT_CSD_CARD_TYPE_F_52M_1_8V (1 << 2)
148 #define EXT_CSD_CARD_TYPE_F_52M_1_2V (1 << 3)
149 #define EXT_CSD_CARD_TYPE_F_HS200_1_8V (1 << 4)
150 #define EXT_CSD_CARD_TYPE_F_HS200_1_2V (1 << 5)
151 #define EXT_CSD_CARD_TYPE_F_HS400_1_8V (1 << 6)
152 #define EXT_CSD_CARD_TYPE_F_HS400_1_2V (1 << 7)
153 #define EXT_CSD_CARD_TYPE_26M 0x01
154 #define EXT_CSD_CARD_TYPE_52M 0x03
155 #define EXT_CSD_CARD_TYPE_52M_V18 0x07
156 #define EXT_CSD_CARD_TYPE_52M_V12 0x0b
157 #define EXT_CSD_CARD_TYPE_52M_V12_18 0x0f
158
159 /* MMC_SWITCH access mode */
160 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
161 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */
162 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */
163 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
164
165 /* SPI mode reports R1/R2(SEND_STATUS) status. */
166 #define R1_SPI_IDLE (1 << 0)
167 #define R1_SPI_ERASE_RESET (1 << 1)
168 #define R1_SPI_ILLEGAL_COMMAND (1 << 2)
169 #define R1_SPI_COM_CRC (1 << 3)
170 #define R1_SPI_ERASE_SEQ (1 << 4)
171 #define R1_SPI_ADDRESS (1 << 5)
172 #define R1_SPI_PARAMETER (1 << 6)
173 /* R1 bit 7 is always zero */
174 #define R2_SPI_CARD_LOCKED (1 << 8)
175 #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
176 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
177 #define R2_SPI_ERROR (1 << 10)
178 #define R2_SPI_CC_ERROR (1 << 11)
179 #define R2_SPI_CARD_ECC_ERROR (1 << 12)
180 #define R2_SPI_WP_VIOLATION (1 << 13)
181 #define R2_SPI_ERASE_PARAM (1 << 14)
182 #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
183 #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
184
185 /* MMC R2 response (CSD) */
186 #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
187 #define MMC_CSD_CSDVER_1_0 0
188 #define MMC_CSD_CSDVER_1_1 1
189 #define MMC_CSD_CSDVER_1_2 2 /* MMC 4.1 - 4.2 - 4.3 */
190 #define MMC_CSD_CSDVER_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
191 #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
192 #define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */
193 #define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */
194 #define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */
195 #define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */
196 #define MMC_CSD_MMCVER_4_0 4 /* MMC 4.1 - 4.2 - 4.3 */
197 #define MMC_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
198 #define MMC_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 115, 4)
199 #define MMC_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 112, 3)
200 #define MMC_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
201 #define MMC_CSD_TRAN_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
202 #define MMC_CSD_TRAN_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4)
203 #define MMC_CSD_TRAN_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3)
204 #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
205 #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
206 #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \
207 (MMC_CSD_C_SIZE_MULT((resp))+2))
208 #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
209 #define MMC_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
210 #define MMC_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
211
212 /* MMC v1 R2 response (CID) */
213 #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24)
214 #define MMC_CID_PNM_V1_CPY(resp, pnm) \
215 do { \
216 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
217 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
218 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
219 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
220 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
221 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
222 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \
223 (pnm)[7] = '\0'; \
224 } while (/*CONSTCOND*/0)
225 #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8)
226 #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24)
227 #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8)
228
229 /* MMC v2 R2 response (CID) */
230 #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8)
231 #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16)
232 #define MMC_CID_PNM_V2_CPY(resp, pnm) \
233 do { \
234 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
235 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
236 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
237 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
238 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
239 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
240 (pnm)[6] = '\0'; \
241 } while (/*CONSTCOND*/0)
242 #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32)
243
244 /* SD R2 response (CSD) */
245 #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
246 #define SD_CSD_CSDVER_1_0 0
247 #define SD_CSD_CSDVER_2_0 1
248 #define SD_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
249 #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
250 #define SD_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 115, 4)
251 #define SD_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 112, 3)
252 #define SD_CSD_TAAC_1_5_MSEC 0x26
253 #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
254 #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
255 #define SD_CSD_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4)
256 #define SD_CSD_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3)
257 #define SD_CSD_SPEED_25_MHZ 0x32
258 #define SD_CSD_SPEED_50_MHZ 0x5a
259 #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12)
260 #define SD_CSD_CCC_BASIC (1 << 0) /* basic */
261 #define SD_CSD_CCC_BR (1 << 2) /* block read */
262 #define SD_CSD_CCC_BW (1 << 4) /* block write */
263 #define SD_CSD_CCC_ERACE (1 << 5) /* erase */
264 #define SD_CSD_CCC_WP (1 << 6) /* write protection */
265 #define SD_CSD_CCC_LC (1 << 7) /* lock card */
266 #define SD_CSD_CCC_AS (1 << 8) /*application specific*/
267 #define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */
268 #define SD_CSD_CCC_SWITCH (1 << 10) /* switch */
269 #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
270 #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1)
271 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
272 #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1)
273 #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1)
274 #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
275 #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \
276 (SD_CSD_C_SIZE_MULT((resp))+2))
277 #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3)
278 #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3)
279 #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3)
280 #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3)
281 #define SD_CSD_VDD_RW_CURR_100mA 0x7
282 #define SD_CSD_VDD_RW_CURR_80mA 0x6
283 #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22)
284 #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
285 #define SD_CSD_V2_BL_LEN 0x9 /* 512 */
286 #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
287 #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1)
288 #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */
289 #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */
290 #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1)
291 #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
292 #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
293 #define SD_CSD_RW_BL_LEN_2G 0xa
294 #define SD_CSD_RW_BL_LEN_1G 0x9
295 #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1)
296 #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1)
297 #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1)
298 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
299 #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1)
300 #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2)
301
302 /* SD R2 response (CID) */
303 #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8)
304 #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16)
305 #define SD_CID_PNM_CPY(resp, pnm) \
306 do { \
307 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
308 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
309 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
310 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
311 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
312 (pnm)[5] = '\0'; \
313 } while (/*CONSTCOND*/0)
314 #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8)
315 #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32)
316 #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12)
317
318 /* SCR (SD Configuration Register) */
319 #define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4)
320 #define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */
321 #define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4)
322 #define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */
323 #define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */
324 #define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */
325 #define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1)
326 #define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3)
327 #define SCR_SD_SECURITY_NONE 0 /* no security */
328 #define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */
329 #define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */
330 #define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4)
331 #define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */
332 #define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */
333 #define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1)
334 #define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4)
335 #define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 9)
336 #define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1)
337 #define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1)
338 #define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32)
339
340 #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start), (len))
341 static inline int
342 __bitfield(uint32_t *src, int start, int len)
343 {
344 uint8_t *sp;
345 uint32_t dst, mask;
346 int shift, bs, bc;
347
348 if (start < 0 || len < 0 || len > 32)
349 return 0;
350
351 dst = 0;
352 mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX;
353 shift = 0;
354
355 while (len > 0) {
356 sp = (uint8_t *)src + start / 8;
357 bs = start % 8;
358 bc = 8 - bs;
359 if (bc > len)
360 bc = len;
361 dst |= (*sp >> bs) << shift;
362 shift += bc;
363 start += bc;
364 len -= bc;
365 }
366
367 dst &= mask;
368 return (int)dst;
369 }
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