misc cleanup
[rpi-open-firmware.git] / arm_chainloader / drivers / sdhost_impl.cc
1 /*=============================================================================
2 Copyright (C) 2016-2017 Authors of rpi-open-firmware
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 SDHOST driver. This used to be known as ALTMMC.
17
18 =============================================================================*/
19
20 #include <chainloader.h>
21 #include <hardware.h>
22
23 #include "sd_proto.hpp"
24 #include "block_device.hpp"
25
26 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
27 #define SDEDM_READ_THRESHOLD_SHIFT 14
28 #define SDEDM_THRESHOLD_MASK 0x1f
29
30 #define SAFE_READ_THRESHOLD 4
31 #define SAFE_WRITE_THRESHOLD 4
32
33 #define VOLTAGE_SUPPLY_RANGE 0x100
34 #define CHECK_PATTERN 0x55
35
36 #define SDHSTS_BUSY_IRPT 0x400
37 #define SDHSTS_BLOCK_IRPT 0x200
38 #define SDHSTS_SDIO_IRPT 0x100
39 #define SDHSTS_REW_TIME_OUT 0x80
40 #define SDHSTS_CMD_TIME_OUT 0x40
41 #define SDHSTS_CRC16_ERROR 0x20
42 #define SDHSTS_CRC7_ERROR 0x10
43 #define SDHSTS_FIFO_ERROR 0x08
44
45 #define SDEDM_FSM_MASK 0xf
46 #define SDEDM_FSM_IDENTMODE 0x0
47 #define SDEDM_FSM_DATAMODE 0x1
48 #define SDEDM_FSM_READDATA 0x2
49 #define SDEDM_FSM_WRITEDATA 0x3
50 #define SDEDM_FSM_READWAIT 0x4
51 #define SDEDM_FSM_READCRC 0x5
52 #define SDEDM_FSM_WRITECRC 0x6
53 #define SDEDM_FSM_WRITEWAIT1 0x7
54 #define SDEDM_FSM_POWERDOWN 0x8
55 #define SDEDM_FSM_POWERUP 0x9
56 #define SDEDM_FSM_WRITESTART1 0xa
57 #define SDEDM_FSM_WRITESTART2 0xb
58 #define SDEDM_FSM_GENPULSES 0xc
59 #define SDEDM_FSM_WRITEWAIT2 0xd
60 #define SDEDM_FSM_STARTPOWDOWN 0xf
61
62 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR|SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR)
63 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK)
64
65 #define logf(fmt, ...) printf("[EMMC:%s]: " fmt, __FUNCTION__, ##__VA_ARGS__);
66
67 #define kIdentSafeClockRate 0x148
68
69 struct BCM2708SDHost : BlockDevice {
70 bool is_sdhc;
71 bool is_high_capacity;
72 bool card_ready;
73
74 uint32_t ocr;
75 uint32_t rca;
76
77 uint32_t cid[4];
78 uint32_t csd[4];
79
80 uint32_t capacity_bytes;
81
82 uint32_t r[4];
83
84 uint32_t current_cmd;
85
86 void set_power(bool on) {
87 SH_VDD = on ? SH_VDD_POWER_ON_SET : 0x0;
88 }
89
90 bool wait(uint32_t timeout = 100000) {
91 uint32_t t = timeout;
92
93 while(SH_CMD & SH_CMD_NEW_FLAG_SET) {
94 if (t == 0) {
95 logf("timed out after %dus!\n", timeout)
96 return false;
97 }
98 t--;
99 udelay(10);
100 }
101
102 return true;
103 }
104
105 bool send_raw(uint32_t command, uint32_t arg = 0) {
106 uint32_t sts;
107
108 wait();
109
110 sts = SH_HSTS;
111 if (sts & SDHSTS_ERROR_MASK)
112 SH_HSTS = sts;
113
114 current_cmd = command & SH_CMD_COMMAND_SET;
115
116 SH_ARG = arg;
117 SH_CMD = command | SH_CMD_NEW_FLAG_SET;
118
119 mfence();
120
121 return true;
122 }
123
124 bool send(uint32_t command, uint32_t arg = 0) {
125 return send_raw(command & SH_CMD_COMMAND_SET, arg);
126 }
127
128 bool send_136_resp(uint32_t command, uint32_t arg = 0) {
129 return send_raw((command & SH_CMD_COMMAND_SET) | SH_CMD_LONG_RESPONSE_SET, arg);
130 }
131
132 bool send_no_resp(uint32_t command, uint32_t arg = 0) {
133 return send_raw((command & SH_CMD_COMMAND_SET) | SH_CMD_NO_RESPONSE_SET, arg);
134 }
135
136 void configure_pinmux() {
137 logf("configuring pinmux ...\n");
138
139 GP_FSEL4 = 0x24000000;
140 GP_FSEL5 = 0x924;
141
142 GP_PUD = 2;
143 mfence();
144 udelay(500);
145 GP_PUD = 0;
146
147 /* are these in bank 1 or 2? */
148 GP_PUDCLK1 = GP_PUDCLK1_PUDCLKn32_SET;
149 GP_PUDCLK2 = GP_PUDCLK2_PUDCLKn64_SET;
150 udelay(500);
151
152 GP_PUDCLK1 = 0;
153 GP_PUDCLK2 = 0;
154
155 logf("pinmux configured for aux0\n");
156 }
157
158 void reset() {
159 logf("resetting controller ...\n");
160 set_power(false);
161
162 SH_CMD = 0;
163 SH_ARG = 0;
164 SH_TOUT = 0xF00000;
165 SH_CDIV = 0;
166 SH_HSTS = 0x7f8;
167 SH_HCFG = 0;
168 SH_HBCT = 0;
169 SH_HBLC = 0;
170
171 uint32_t temp = SH_EDM;
172
173 temp &= ~((SDEDM_THRESHOLD_MASK<<SDEDM_READ_THRESHOLD_SHIFT) |
174 (SDEDM_THRESHOLD_MASK<<SDEDM_WRITE_THRESHOLD_SHIFT));
175 temp |= (SAFE_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
176 (SAFE_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
177
178 SH_EDM = temp;
179 udelay(300);
180
181 set_power(true);
182
183 udelay(300);
184 mfence();
185 }
186
187 inline void get_response() {
188 r[0] = SH_RSP0;
189 r[1] = SH_RSP1;
190 r[2] = SH_RSP2;
191 r[3] = SH_RSP3;
192 }
193
194 bool wait_and_get_response() {
195 if (!wait())
196 return false;
197
198 get_response();
199
200 if (SH_CMD & SH_CMD_FAIL_FLAG_SET) {
201 if (SH_HSTS & SDHSTS_ERROR_MASK) {
202 logf("ERROR: sdhost status: 0x%x\n", SH_HSTS);
203 return false;
204 }
205 logf("ERROR: unknown error, SH_CMD=0x%x\n", SH_CMD);
206 return false;
207 }
208
209
210 return true;
211 }
212
213 bool query_voltage_and_type() {
214 uint32_t t;
215
216 /* identify */
217 send(SD_SEND_IF_COND, 0x1AA);
218 wait_and_get_response();
219
220 /* set voltage */
221 t = MMC_OCR_3_3V_3_4V;
222 if (r[0] == 0x1AA) {
223 t |= MMC_OCR_HCS;
224 is_sdhc = true;
225 }
226
227 /* query voltage and type */
228 for (;;) {
229 send(MMC_APP_CMD); /* 55 */
230 send_no_resp(SD_APP_OP_COND, t);
231
232 if (!wait_and_get_response())
233 return false;
234
235 if (r[0] & MMC_OCR_MEM_READY)
236 break;
237
238 logf("waiting for SD (0x%x) ...\n", r[0]);
239 udelay(100);
240 }
241
242 logf("SD card has arrived!\n", r);
243
244 return true;
245
246 }
247
248 inline void copy_136_to(uint32_t* dest) {
249 dest[0] = r[0];
250 dest[1] = r[1];
251 dest[2] = r[2];
252 dest[3] = r[3];
253 }
254
255 bool identify_card() {
256 logf("identifying card ...\n");
257
258 send_136_resp(MMC_ALL_SEND_CID);
259 if (!wait_and_get_response())
260 return false;
261
262 /* for SD this gets RCA */
263 send(MMC_SET_RELATIVE_ADDR);
264 if (!wait_and_get_response())
265 return false;
266 rca = SD_R6_RCA(r);
267
268 send_136_resp(MMC_SEND_CID, MMC_ARG_RCA(rca));
269 if (!wait_and_get_response())
270 return false;
271
272 copy_136_to(cid);
273
274 /* get card specific data */
275 send_136_resp(MMC_SEND_CSD, MMC_ARG_RCA(rca));
276 if (!wait_and_get_response())
277 return false;
278
279 copy_136_to(csd);
280
281 return true;
282 }
283
284 bool wait_for_fifo_data(uint32_t timeout = 100000) {
285 uint32_t t = timeout;
286
287 while ((SH_HSTS & SH_HSTS_DATA_FLAG_SET) == 0) {
288 if (t == 0) {
289 putchar('\n');
290 logf("ERROR: no FIFO data, timed out after %dus!\n", timeout);
291 return false;
292 }
293 t--;
294 udelay(10);
295 }
296
297 return true;
298 }
299
300 void drain_fifo() {
301 wait();
302
303 while (SH_HSTS & SH_HSTS_DATA_FLAG_SET) {
304 SH_DATA;
305 mfence();
306 }
307 }
308
309 void drain_fifo_nowait() {
310 while (true) {
311 SH_DATA;
312
313 uint32_t hsts = SH_HSTS;
314 if (hsts != SH_HSTS_DATA_FLAG_SET)
315 break;
316 }
317 }
318
319 virtual bool read_block(uint32_t sector, uint32_t* buf) override {
320 if (!card_ready)
321 panic("card not ready");
322
323 if (!is_high_capacity)
324 sector <<= 9;
325
326 /* drain junk from FIFO */
327 drain_fifo();
328
329 /* enter READ mode */
330 send_raw(MMC_READ_BLOCK_MULTIPLE | SH_CMD_READ_CMD_SET, sector);
331
332 int i;
333 uint32_t hsts_err = 0;
334
335 #ifdef DUMP_READ
336 if (buf)
337 logf("Reading %d bytes from sector %d using FIFO ...\n", block_size, sector);
338 #endif
339
340 #ifdef DUMP_READ
341 if (buf)
342 printf("----------------------------------------------------\n");
343 #endif
344
345 /* drain useful data from FIFO */
346 for (i = 0; i < 128; i++) {
347 /* wait for FIFO */
348 if (!wait_for_fifo_data())
349 break;
350
351 uint32_t hsts_err = SH_HSTS & SDHSTS_ERROR_MASK;
352 if (hsts_err) {
353 logf("ERROR: transfer error on FIFO word %d: 0x%x\n", i, SH_HSTS);
354 break;
355 }
356
357
358 volatile uint32_t data = SH_DATA;
359
360 #ifdef DUMP_READ
361 printf("%08x ", data);
362 #endif
363 if (buf)
364 *(buf++) = data;
365 }
366
367 send_raw(MMC_STOP_TRANSMISSION | SH_CMD_BUSY_CMD_SET);
368
369 #ifdef DUMP_READ
370 if (buf)
371 printf("\n----------------------------------------------------\n");
372 #endif
373
374 if (hsts_err) {
375 logf("ERROR: Transfer error, status: 0x%x\n", SH_HSTS);
376 return false;
377 }
378
379 #ifdef DUMP_READ
380 if (buf)
381 logf("Completed read for %d\n", sector);
382 #endif
383 return true;
384 }
385
386
387
388 bool select_card() {
389 send(MMC_SELECT_CARD, MMC_ARG_RCA(rca));
390
391 return wait();
392 }
393
394 bool init_card() {
395 char pnm[8];
396 uint32_t block_length;
397 uint32_t clock_div = 0;
398
399 send_no_resp(MMC_GO_IDLE_STATE);
400
401 if (!query_voltage_and_type()) {
402 logf("ERROR: Failed to query card voltage!\n");
403 return false;
404 }
405
406 if (!identify_card()) {
407 logf("ERROR: Failed to identify card!\n");
408 return false;
409 }
410
411 SD_CID_PNM_CPY(cid, pnm);
412
413 logf("Detected SD card:\n");
414 printf(" Product : %s\n", &pnm);
415
416 if (SD_CSD_CSDVER(csd) == SD_CSD_CSDVER_2_0) {
417 printf(" CSD : Ver 2.0\n");
418 printf(" Capacity: %d\n", SD_CSD_V2_CAPACITY(csd));
419 printf(" Size : %d\n", SD_CSD_V2_C_SIZE(csd));
420
421 block_length = 1 << SD_CSD_V2_BL_LEN;
422
423 /* work out the capacity of the card in bytes */
424 capacity_bytes = (SD_CSD_V2_CAPACITY(csd) * block_length);
425
426 clock_div = 5;
427 } else if (SD_CSD_CSDVER(csd) == SD_CSD_CSDVER_1_0) {
428 printf(" CSD : Ver 1.0\n");
429 printf(" Capacity: %d\n", SD_CSD_CAPACITY(csd));
430 printf(" Size : %d\n", SD_CSD_C_SIZE(csd));
431
432 block_length = 1 << SD_CSD_READ_BL_LEN(csd);
433
434 /* work out the capacity of the card in bytes */
435 capacity_bytes = (SD_CSD_CAPACITY(csd) * block_length);
436
437 clock_div = 10;
438 } else {
439 printf("ERROR: Unknown CSD version 0x%x!\n", SD_CSD_CSDVER(csd));
440 return false;
441 }
442
443 printf(" BlockLen: 0x%x\n", block_length);
444
445 if (!select_card()) {
446 logf("ERROR: Failed to select card!\n");
447 return false;
448 }
449
450 if (SD_CSD_CSDVER(csd) == SD_CSD_CSDVER_1_0) {
451 /*
452 * only needed for 1.0 ones, the 2.0 ones have this
453 * fixed at 512.
454 */
455 logf("Setting block length to 512 ...\n");
456 send(MMC_SET_BLOCKLEN, 512);
457 if (!wait()) {
458 logf("ERROR: Failed to set block length!\n");
459 return false;
460 }
461 }
462
463 block_size = 512;
464
465 logf("Card initialization complete: %s %dMB SD%s Card\n", &pnm, capacity_bytes >> 20, is_high_capacity ? "HC" : "");
466
467 /*
468 * this makes some dangerous assumptions that the all csd2 cards are sdio cards
469 * and all csd1 cards are sd cards and that mmc cards won't be used. this also assumes
470 * PLLC.CORE0 is at 250MHz which is probably a safe assumption since we set it.
471 */
472 if (clock_div) {
473 logf("Identification complete, changing clock to %dMHz for data mode ...\n", 250 / clock_div);
474 SH_CDIV = clock_div - 2;
475 }
476
477 return true;
478 }
479
480 void restart_controller() {
481 is_sdhc = false;
482
483 logf("Restarting the eMMC controller ...\n");
484
485 configure_pinmux();
486 reset();
487
488 SH_HCFG &= ~SH_HCFG_WIDE_EXT_BUS_SET;
489 SH_HCFG = SH_HCFG_SLOW_CARD_SET | SH_HCFG_WIDE_INT_BUS_SET;
490 SH_CDIV = kIdentSafeClockRate;
491
492 udelay(300);
493 mfence();
494
495 if (init_card()) {
496 card_ready = true;
497
498 /* work around quirk / silicon bug */
499 for (int i = 0; i < 3; i++)
500 if (!read_block(0, nullptr))
501 panic("fifo flush cycle %d failed", i);
502 } else {
503 panic("failed to reinitialize the eMMC controller");
504 }
505 }
506
507 virtual void stop() override {
508 if (card_ready) {
509 logf("flushing fifo ...\n");
510 drain_fifo_nowait();
511
512 logf("asking card to enter idle state ...\n");
513 SH_CDIV = kIdentSafeClockRate;
514 udelay(150);
515
516 send_no_resp(MMC_GO_IDLE_STATE);
517 udelay(500);
518 }
519
520 logf("stopping sdhost controller driver ...\n");
521
522 SH_CMD = 0;
523 SH_ARG = 0;
524 SH_TOUT = 0xA00000;
525 SH_CDIV = 0x1FB;
526
527 logf("powering down controller ...\n");
528 SH_VDD = 0;
529 SH_HCFG = 0;
530 SH_HBCT = 0x400;
531 SH_HBLC = 0;
532 SH_HSTS = 0x7F8;
533
534 logf("resetting state machine ...\n");
535
536 SH_CMD = 0;
537 SH_ARG = 0;
538 }
539
540 BCM2708SDHost() {
541 restart_controller();
542 logf("eMMC driver sucessfully started!\n");
543 }
544 };
545
546 BCM2708SDHost STATIC_DRIVER g_SDHostDriver {};
547
548 BlockDevice* get_sdhost_device() {
549 return &g_SDHostDriver;
550 }
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