add basic secure monitor code for armv7+, for some reason sdram security does not...
[rpi-open-firmware.git] / arm_chainloader / start.s
1 /*=============================================================================
2 Copyright (C) 2016-2017 Authors of rpi-open-firmware
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 ARM entry point.
17
18 This is where all cores start. For RPi1, only one core starts so we can jump
19 straight to the main bootloader. For later models, the first core jumps to the
20 bootloader. The other cores wait until SMP is enabled by the kernel later in
21 the boot process.
22
23 =============================================================================*/
24
25 #include "memory_map.h"
26
27 .arch_extension sec
28
29 .text
30 .globl _start
31 _start:
32 /* vectors */
33 b _common_start /* reset */
34 nop /* undefined */
35 b _secure_monitor /* swi/smc */
36 nop /* prefetch abort */
37 nop /* data abort */
38 nop /* reserved */
39 nop /* irq */
40 nop /* fiq */
41
42 .globl g_FirmwareData
43 g_FirmwareData:
44 .long 0 /* SDRAM capacity */
45 .long 0 /* VPU CPUID */
46 .long 0 /* Reserved */
47 .long 0 /* Reserved */
48 .long 0 /* Reserved */
49
50 _secure_monitor:
51 mrc p15, 0, r0, c1, c1, 0
52 bic r0, r0, #0x4a /* clear IRQ, EA, nET */
53 orr r0, r0, #1 /* set NS */
54 mcr p15, 0, r0, c1, c1, 0
55
56 mov r0, #((1 << 7) | (1 << 8) | (1 << 6)) /* mask IRQ, AA and FIQ */
57 orr r0, r0, #0x1a /* switch to hypervisor mode */
58 msr spsr_cxfs, r0
59
60 movs pc, lr
61
62 _common_start:
63 /*
64 * read MIDR, see if this is an ARMv6 system, if it is, just
65 * assume single core (BCM2708) and not bother doing SMP stuff.
66 */
67 mrc p15, 0, r0, c0, c0, 0
68 lsr r0, #16
69 and r0, #0xF
70 cmp r0, #0x7
71 mov r12, #0
72 beq L_finish_init
73
74 L_armv7_or_higher:
75 /*
76 * okay, we're an ARMv7 or an ARMv8.
77 */
78 mrc p15, 0, r0, c0, c0, 5 // read MPIDR
79 and r3, r0, #0xc0000000 // multiprocessing extensions and
80 teq r3, #0x80000000 // not part of a uniprocessor system?
81 bne L_setup_monitor // no, assume UP
82 ands r0, r0, #0x03 // CPU 0?
83 bne L_deadloop // if not, spin.
84
85 L_setup_monitor:
86 adr r1, _start
87 mcr p15, 0, r1, c12, c0, 1 /* MVBAR */
88 mcr p15, 0, r1, c7, c5, 4 /* ISB (ARMv6 compatible way) */
89
90 mov r12, #1
91 smc 0
92
93 L_finish_init:
94 /* enable instruction cache */
95 mrc p15, 0, r0, c1, c0, 0
96 orr r0, r0, #(1<<12)
97 mcr p15, 0, r0, c1, c0, 0
98
99 mov sp, #(MEM_STACK_END)
100 mov r0, r12
101 b main
102
103 L_deadloop:
104 cpsie if
105 wfi
106 b L_deadloop
This page took 0.095268 seconds and 4 git commands to generate.