Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / apb_async_bridge_ctrl.h
1 // This file was generated by the create_regs script
2 #define ASB_BASE 0x7e00a000
3 #define ASB_APB_ID 0x62726467
4 #define ASB_AXI_BRDG_VERSION HW_REGISTER_RW( 0x7e00a000 )
5 #define ASB_AXI_BRDG_VERSION_MASK 0x000000ff
6 #define ASB_AXI_BRDG_VERSION_WIDTH 8
7 #define ASB_AXI_BRDG_VERSION_RESET 0000000000
8 #define ASB_CPR_CTRL HW_REGISTER_RW( 0x7e00a004 )
9 #define ASB_CPR_CTRL_MASK 0x00ffffff
10 #define ASB_CPR_CTRL_WIDTH 24
11 #define ASB_CPR_CTRL_RESET 0x00000007
12 #define ASB_CPR_CTRL_CLR_REQ_BITS 0:0
13 #define ASB_CPR_CTRL_CLR_REQ_SET 0x00000001
14 #define ASB_CPR_CTRL_CLR_REQ_CLR 0xfffffffe
15 #define ASB_CPR_CTRL_CLR_REQ_MSB 0
16 #define ASB_CPR_CTRL_CLR_REQ_LSB 0
17 #define ASB_CPR_CTRL_CLR_ACK_BITS 1:1
18 #define ASB_CPR_CTRL_CLR_ACK_SET 0x00000002
19 #define ASB_CPR_CTRL_CLR_ACK_CLR 0xfffffffd
20 #define ASB_CPR_CTRL_CLR_ACK_MSB 1
21 #define ASB_CPR_CTRL_CLR_ACK_LSB 1
22 #define ASB_CPR_CTRL_EMPTY_BITS 2:2
23 #define ASB_CPR_CTRL_EMPTY_SET 0x00000004
24 #define ASB_CPR_CTRL_EMPTY_CLR 0xfffffffb
25 #define ASB_CPR_CTRL_EMPTY_MSB 2
26 #define ASB_CPR_CTRL_EMPTY_LSB 2
27 #define ASB_CPR_CTRL_FULL_BITS 3:3
28 #define ASB_CPR_CTRL_FULL_SET 0x00000008
29 #define ASB_CPR_CTRL_FULL_CLR 0xfffffff7
30 #define ASB_CPR_CTRL_FULL_MSB 3
31 #define ASB_CPR_CTRL_FULL_LSB 3
32 #define ASB_CPR_CTRL_RCOUNT_BITS 13:4
33 #define ASB_CPR_CTRL_RCOUNT_SET 0x00003ff0
34 #define ASB_CPR_CTRL_RCOUNT_CLR 0xffffc00f
35 #define ASB_CPR_CTRL_RCOUNT_MSB 13
36 #define ASB_CPR_CTRL_RCOUNT_LSB 4
37 #define ASB_CPR_CTRL_WCOUNT_BITS 23:14
38 #define ASB_CPR_CTRL_WCOUNT_SET 0x00ffc000
39 #define ASB_CPR_CTRL_WCOUNT_CLR 0xff003fff
40 #define ASB_CPR_CTRL_WCOUNT_MSB 23
41 #define ASB_CPR_CTRL_WCOUNT_LSB 14
42 #define ASB_V3D_S_CTRL HW_REGISTER_RW( 0x7e00a008 )
43 #define ASB_V3D_S_CTRL_MASK 0x00ffffff
44 #define ASB_V3D_S_CTRL_WIDTH 24
45 #define ASB_V3D_S_CTRL_RESET 0x00000007
46 #define ASB_V3D_S_CTRL_CLR_REQ_BITS 0:0
47 #define ASB_V3D_S_CTRL_CLR_REQ_SET 0x00000001
48 #define ASB_V3D_S_CTRL_CLR_REQ_CLR 0xfffffffe
49 #define ASB_V3D_S_CTRL_CLR_REQ_MSB 0
50 #define ASB_V3D_S_CTRL_CLR_REQ_LSB 0
51 #define ASB_V3D_S_CTRL_CLR_ACK_BITS 1:1
52 #define ASB_V3D_S_CTRL_CLR_ACK_SET 0x00000002
53 #define ASB_V3D_S_CTRL_CLR_ACK_CLR 0xfffffffd
54 #define ASB_V3D_S_CTRL_CLR_ACK_MSB 1
55 #define ASB_V3D_S_CTRL_CLR_ACK_LSB 1
56 #define ASB_V3D_S_CTRL_EMPTY_BITS 2:2
57 #define ASB_V3D_S_CTRL_EMPTY_SET 0x00000004
58 #define ASB_V3D_S_CTRL_EMPTY_CLR 0xfffffffb
59 #define ASB_V3D_S_CTRL_EMPTY_MSB 2
60 #define ASB_V3D_S_CTRL_EMPTY_LSB 2
61 #define ASB_V3D_S_CTRL_FULL_BITS 3:3
62 #define ASB_V3D_S_CTRL_FULL_SET 0x00000008
63 #define ASB_V3D_S_CTRL_FULL_CLR 0xfffffff7
64 #define ASB_V3D_S_CTRL_FULL_MSB 3
65 #define ASB_V3D_S_CTRL_FULL_LSB 3
66 #define ASB_V3D_S_CTRL_RCOUNT_BITS 13:4
67 #define ASB_V3D_S_CTRL_RCOUNT_SET 0x00003ff0
68 #define ASB_V3D_S_CTRL_RCOUNT_CLR 0xffffc00f
69 #define ASB_V3D_S_CTRL_RCOUNT_MSB 13
70 #define ASB_V3D_S_CTRL_RCOUNT_LSB 4
71 #define ASB_V3D_S_CTRL_WCOUNT_BITS 23:14
72 #define ASB_V3D_S_CTRL_WCOUNT_SET 0x00ffc000
73 #define ASB_V3D_S_CTRL_WCOUNT_CLR 0xff003fff
74 #define ASB_V3D_S_CTRL_WCOUNT_MSB 23
75 #define ASB_V3D_S_CTRL_WCOUNT_LSB 14
76 #define ASB_V3D_M_CTRL HW_REGISTER_RW( 0x7e00a00c )
77 #define ASB_V3D_M_CTRL_MASK 0x00ffffff
78 #define ASB_V3D_M_CTRL_WIDTH 24
79 #define ASB_V3D_M_CTRL_RESET 0x00000007
80 #define ASB_V3D_M_CTRL_CLR_REQ_BITS 0:0
81 #define ASB_V3D_M_CTRL_CLR_REQ_SET 0x00000001
82 #define ASB_V3D_M_CTRL_CLR_REQ_CLR 0xfffffffe
83 #define ASB_V3D_M_CTRL_CLR_REQ_MSB 0
84 #define ASB_V3D_M_CTRL_CLR_REQ_LSB 0
85 #define ASB_V3D_M_CTRL_CLR_ACK_BITS 1:1
86 #define ASB_V3D_M_CTRL_CLR_ACK_SET 0x00000002
87 #define ASB_V3D_M_CTRL_CLR_ACK_CLR 0xfffffffd
88 #define ASB_V3D_M_CTRL_CLR_ACK_MSB 1
89 #define ASB_V3D_M_CTRL_CLR_ACK_LSB 1
90 #define ASB_V3D_M_CTRL_EMPTY_BITS 2:2
91 #define ASB_V3D_M_CTRL_EMPTY_SET 0x00000004
92 #define ASB_V3D_M_CTRL_EMPTY_CLR 0xfffffffb
93 #define ASB_V3D_M_CTRL_EMPTY_MSB 2
94 #define ASB_V3D_M_CTRL_EMPTY_LSB 2
95 #define ASB_V3D_M_CTRL_FULL_BITS 3:3
96 #define ASB_V3D_M_CTRL_FULL_SET 0x00000008
97 #define ASB_V3D_M_CTRL_FULL_CLR 0xfffffff7
98 #define ASB_V3D_M_CTRL_FULL_MSB 3
99 #define ASB_V3D_M_CTRL_FULL_LSB 3
100 #define ASB_V3D_M_CTRL_RCOUNT_BITS 13:4
101 #define ASB_V3D_M_CTRL_RCOUNT_SET 0x00003ff0
102 #define ASB_V3D_M_CTRL_RCOUNT_CLR 0xffffc00f
103 #define ASB_V3D_M_CTRL_RCOUNT_MSB 13
104 #define ASB_V3D_M_CTRL_RCOUNT_LSB 4
105 #define ASB_V3D_M_CTRL_WCOUNT_BITS 23:14
106 #define ASB_V3D_M_CTRL_WCOUNT_SET 0x00ffc000
107 #define ASB_V3D_M_CTRL_WCOUNT_CLR 0xff003fff
108 #define ASB_V3D_M_CTRL_WCOUNT_MSB 23
109 #define ASB_V3D_M_CTRL_WCOUNT_LSB 14
110 #define ASB_ISP_S_CTRL HW_REGISTER_RW( 0x7e00a010 )
111 #define ASB_ISP_S_CTRL_MASK 0x00ffffff
112 #define ASB_ISP_S_CTRL_WIDTH 24
113 #define ASB_ISP_S_CTRL_RESET 0x00000007
114 #define ASB_ISP_S_CTRL_CLR_REQ_BITS 0:0
115 #define ASB_ISP_S_CTRL_CLR_REQ_SET 0x00000001
116 #define ASB_ISP_S_CTRL_CLR_REQ_CLR 0xfffffffe
117 #define ASB_ISP_S_CTRL_CLR_REQ_MSB 0
118 #define ASB_ISP_S_CTRL_CLR_REQ_LSB 0
119 #define ASB_ISP_S_CTRL_CLR_ACK_BITS 1:1
120 #define ASB_ISP_S_CTRL_CLR_ACK_SET 0x00000002
121 #define ASB_ISP_S_CTRL_CLR_ACK_CLR 0xfffffffd
122 #define ASB_ISP_S_CTRL_CLR_ACK_MSB 1
123 #define ASB_ISP_S_CTRL_CLR_ACK_LSB 1
124 #define ASB_ISP_S_CTRL_EMPTY_BITS 2:2
125 #define ASB_ISP_S_CTRL_EMPTY_SET 0x00000004
126 #define ASB_ISP_S_CTRL_EMPTY_CLR 0xfffffffb
127 #define ASB_ISP_S_CTRL_EMPTY_MSB 2
128 #define ASB_ISP_S_CTRL_EMPTY_LSB 2
129 #define ASB_ISP_S_CTRL_FULL_BITS 3:3
130 #define ASB_ISP_S_CTRL_FULL_SET 0x00000008
131 #define ASB_ISP_S_CTRL_FULL_CLR 0xfffffff7
132 #define ASB_ISP_S_CTRL_FULL_MSB 3
133 #define ASB_ISP_S_CTRL_FULL_LSB 3
134 #define ASB_ISP_S_CTRL_RCOUNT_BITS 13:4
135 #define ASB_ISP_S_CTRL_RCOUNT_SET 0x00003ff0
136 #define ASB_ISP_S_CTRL_RCOUNT_CLR 0xffffc00f
137 #define ASB_ISP_S_CTRL_RCOUNT_MSB 13
138 #define ASB_ISP_S_CTRL_RCOUNT_LSB 4
139 #define ASB_ISP_S_CTRL_WCOUNT_BITS 23:14
140 #define ASB_ISP_S_CTRL_WCOUNT_SET 0x00ffc000
141 #define ASB_ISP_S_CTRL_WCOUNT_CLR 0xff003fff
142 #define ASB_ISP_S_CTRL_WCOUNT_MSB 23
143 #define ASB_ISP_S_CTRL_WCOUNT_LSB 14
144 #define ASB_ISP_M_CTRL HW_REGISTER_RW( 0x7e00a014 )
145 #define ASB_ISP_M_CTRL_MASK 0x00ffffff
146 #define ASB_ISP_M_CTRL_WIDTH 24
147 #define ASB_ISP_M_CTRL_RESET 0x00000007
148 #define ASB_ISP_M_CTRL_CLR_REQ_BITS 0:0
149 #define ASB_ISP_M_CTRL_CLR_REQ_SET 0x00000001
150 #define ASB_ISP_M_CTRL_CLR_REQ_CLR 0xfffffffe
151 #define ASB_ISP_M_CTRL_CLR_REQ_MSB 0
152 #define ASB_ISP_M_CTRL_CLR_REQ_LSB 0
153 #define ASB_ISP_M_CTRL_CLR_ACK_BITS 1:1
154 #define ASB_ISP_M_CTRL_CLR_ACK_SET 0x00000002
155 #define ASB_ISP_M_CTRL_CLR_ACK_CLR 0xfffffffd
156 #define ASB_ISP_M_CTRL_CLR_ACK_MSB 1
157 #define ASB_ISP_M_CTRL_CLR_ACK_LSB 1
158 #define ASB_ISP_M_CTRL_EMPTY_BITS 2:2
159 #define ASB_ISP_M_CTRL_EMPTY_SET 0x00000004
160 #define ASB_ISP_M_CTRL_EMPTY_CLR 0xfffffffb
161 #define ASB_ISP_M_CTRL_EMPTY_MSB 2
162 #define ASB_ISP_M_CTRL_EMPTY_LSB 2
163 #define ASB_ISP_M_CTRL_FULL_BITS 3:3
164 #define ASB_ISP_M_CTRL_FULL_SET 0x00000008
165 #define ASB_ISP_M_CTRL_FULL_CLR 0xfffffff7
166 #define ASB_ISP_M_CTRL_FULL_MSB 3
167 #define ASB_ISP_M_CTRL_FULL_LSB 3
168 #define ASB_ISP_M_CTRL_RCOUNT_BITS 13:4
169 #define ASB_ISP_M_CTRL_RCOUNT_SET 0x00003ff0
170 #define ASB_ISP_M_CTRL_RCOUNT_CLR 0xffffc00f
171 #define ASB_ISP_M_CTRL_RCOUNT_MSB 13
172 #define ASB_ISP_M_CTRL_RCOUNT_LSB 4
173 #define ASB_ISP_M_CTRL_WCOUNT_BITS 23:14
174 #define ASB_ISP_M_CTRL_WCOUNT_SET 0x00ffc000
175 #define ASB_ISP_M_CTRL_WCOUNT_CLR 0xff003fff
176 #define ASB_ISP_M_CTRL_WCOUNT_MSB 23
177 #define ASB_ISP_M_CTRL_WCOUNT_LSB 14
178 #define ASB_H264_S_CTRL HW_REGISTER_RW( 0x7e00a018 )
179 #define ASB_H264_S_CTRL_MASK 0x00ffffff
180 #define ASB_H264_S_CTRL_WIDTH 24
181 #define ASB_H264_S_CTRL_RESET 0x00000007
182 #define ASB_H264_S_CTRL_CLR_REQ_BITS 0:0
183 #define ASB_H264_S_CTRL_CLR_REQ_SET 0x00000001
184 #define ASB_H264_S_CTRL_CLR_REQ_CLR 0xfffffffe
185 #define ASB_H264_S_CTRL_CLR_REQ_MSB 0
186 #define ASB_H264_S_CTRL_CLR_REQ_LSB 0
187 #define ASB_H264_S_CTRL_CLR_ACK_BITS 1:1
188 #define ASB_H264_S_CTRL_CLR_ACK_SET 0x00000002
189 #define ASB_H264_S_CTRL_CLR_ACK_CLR 0xfffffffd
190 #define ASB_H264_S_CTRL_CLR_ACK_MSB 1
191 #define ASB_H264_S_CTRL_CLR_ACK_LSB 1
192 #define ASB_H264_S_CTRL_EMPTY_BITS 2:2
193 #define ASB_H264_S_CTRL_EMPTY_SET 0x00000004
194 #define ASB_H264_S_CTRL_EMPTY_CLR 0xfffffffb
195 #define ASB_H264_S_CTRL_EMPTY_MSB 2
196 #define ASB_H264_S_CTRL_EMPTY_LSB 2
197 #define ASB_H264_S_CTRL_FULL_BITS 3:3
198 #define ASB_H264_S_CTRL_FULL_SET 0x00000008
199 #define ASB_H264_S_CTRL_FULL_CLR 0xfffffff7
200 #define ASB_H264_S_CTRL_FULL_MSB 3
201 #define ASB_H264_S_CTRL_FULL_LSB 3
202 #define ASB_H264_S_CTRL_RCOUNT_BITS 13:4
203 #define ASB_H264_S_CTRL_RCOUNT_SET 0x00003ff0
204 #define ASB_H264_S_CTRL_RCOUNT_CLR 0xffffc00f
205 #define ASB_H264_S_CTRL_RCOUNT_MSB 13
206 #define ASB_H264_S_CTRL_RCOUNT_LSB 4
207 #define ASB_H264_S_CTRL_WCOUNT_BITS 23:14
208 #define ASB_H264_S_CTRL_WCOUNT_SET 0x00ffc000
209 #define ASB_H264_S_CTRL_WCOUNT_CLR 0xff003fff
210 #define ASB_H264_S_CTRL_WCOUNT_MSB 23
211 #define ASB_H264_S_CTRL_WCOUNT_LSB 14
212 #define ASB_H264_M_CTRL HW_REGISTER_RW( 0x7e00a01c )
213 #define ASB_H264_M_CTRL_MASK 0x00ffffff
214 #define ASB_H264_M_CTRL_WIDTH 24
215 #define ASB_H264_M_CTRL_RESET 0x00000007
216 #define ASB_H264_M_CTRL_CLR_REQ_BITS 0:0
217 #define ASB_H264_M_CTRL_CLR_REQ_SET 0x00000001
218 #define ASB_H264_M_CTRL_CLR_REQ_CLR 0xfffffffe
219 #define ASB_H264_M_CTRL_CLR_REQ_MSB 0
220 #define ASB_H264_M_CTRL_CLR_REQ_LSB 0
221 #define ASB_H264_M_CTRL_CLR_ACK_BITS 1:1
222 #define ASB_H264_M_CTRL_CLR_ACK_SET 0x00000002
223 #define ASB_H264_M_CTRL_CLR_ACK_CLR 0xfffffffd
224 #define ASB_H264_M_CTRL_CLR_ACK_MSB 1
225 #define ASB_H264_M_CTRL_CLR_ACK_LSB 1
226 #define ASB_H264_M_CTRL_EMPTY_BITS 2:2
227 #define ASB_H264_M_CTRL_EMPTY_SET 0x00000004
228 #define ASB_H264_M_CTRL_EMPTY_CLR 0xfffffffb
229 #define ASB_H264_M_CTRL_EMPTY_MSB 2
230 #define ASB_H264_M_CTRL_EMPTY_LSB 2
231 #define ASB_H264_M_CTRL_FULL_BITS 3:3
232 #define ASB_H264_M_CTRL_FULL_SET 0x00000008
233 #define ASB_H264_M_CTRL_FULL_CLR 0xfffffff7
234 #define ASB_H264_M_CTRL_FULL_MSB 3
235 #define ASB_H264_M_CTRL_FULL_LSB 3
236 #define ASB_H264_M_CTRL_RCOUNT_BITS 13:4
237 #define ASB_H264_M_CTRL_RCOUNT_SET 0x00003ff0
238 #define ASB_H264_M_CTRL_RCOUNT_CLR 0xffffc00f
239 #define ASB_H264_M_CTRL_RCOUNT_MSB 13
240 #define ASB_H264_M_CTRL_RCOUNT_LSB 4
241 #define ASB_H264_M_CTRL_WCOUNT_BITS 23:14
242 #define ASB_H264_M_CTRL_WCOUNT_SET 0x00ffc000
243 #define ASB_H264_M_CTRL_WCOUNT_CLR 0xff003fff
244 #define ASB_H264_M_CTRL_WCOUNT_MSB 23
245 #define ASB_H264_M_CTRL_WCOUNT_LSB 14
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