ff4fe9a8442d44b0fd538ca41ad99aa59f871a6c
[rpi-open-firmware.git] / bcm2708_chip / aux_io.h
1 //
2 // Auxiliary I/O header file
3 //
4
5 #define AUX_IO_BASE 0x7E215000
6 #define AUX_IRQ (AUX_IO_BASE+0x000)
7 #define AUX_ENABLES (AUX_IO_BASE+0x004)
8 #define AUX_ENABLE_MINIUART 0x01
9 #define AUX_ENABLE_SPI0 0x02
10 #define AUX_ENABLE_SPI1 0x04
11
12
13 //
14 // Micro UART
15 //
16 // Baud rate = sysclk/(8*(BAUD_REG+1))
17
18 #define AUX_MU_IO_REG (AUX_IO_BASE+0x040) // Write=TX read=RX
19 #define AUX_MU_BDLS_REG (AUX_IO_BASE+0x040) // Baudrate LS
20 #define AUX_MU_BDMS_REG (AUX_IO_BASE+0x044) // Baudrate MS.
21
22 #define AUX_MU_IER_REG (AUX_IO_BASE+0x044) // IRQ enbl. reg.
23 #define AUX_MU_IER_RXIRQEN 0x01 //
24 #define AUX_MU_IER_TXIRQEN 0x02 //
25 // Line interrupts are not supported
26
27 #define AUX_MU_IIR_REG (AUX_IO_BASE+0x048) // IRQ status reg
28 #define AUX_MU_IIR_NOIRQS 0x01 // No irq pending
29 #define AUX_MU_IIR_IRQ 0x06 // 10 = rec irq, 01 = tx irq
30 // Timeout is not supported
31
32 #define AUX_MU_FCR_REG (AUX_IO_BASE+0x048) // FIFO control reg
33 #define AUX_MU_FCR_RXCLR 0x02 // Flush receive FF
34 #define AUX_MU_FCR_TXCLR 0x04 // Flush transmit fifo
35
36
37 #define AUX_MU_LCR_REG (AUX_IO_BASE+0x04C) // Line control reg.
38 #define AUX_MU_LCR_7BITS 0x02 // 7 bits mode
39 #define AUX_MU_LCR_8BITS 0x03 // 8 bits mode
40 #define AUX_MU_LCR_BREAK 0x40 // send break
41 #define AUX_MU_LCR_DLAB 0x80 // DLAB access
42 // 5 & 6 bits are not supported
43 // 2 stop bits are not supported
44 // Parity bits are not supported
45
46 #define AUX_MU_MCR_REG (AUX_IO_BASE+0x050) // Modem control reg.
47 #define AUX_MU_MCR_RTS 0x02 // Set RTS high
48 // DTR is not supported
49 // Out1/2 are not supported
50 // Loopback is not supported
51
52 #define AUX_MU_LSR_REG (AUX_IO_BASE+0x054) // Line status reg.
53 #define AUX_MU_LSR_DR 0x01 // Receive Data ready
54 #define AUX_MU_LSR_OE 0x02 // Receiver overrun error
55 #define AUX_MU_LSR_THRE 0x20 // Transmitter holding register
56 #define AUX_MU_LSR_TEMT 0x40 // Transmitter empty
57 // Parity bits (and thus errors) are not supported
58 // Framing errors are not detected
59 // Break detect is not (yet) supported
60
61 #define AUX_MU_MSR_REG (AUX_IO_BASE+0x058) // Modem status reg.
62 #define AUX_MU_MSR_CTS 0x10
63 // Delta CTS not supported
64 // DCE,DCD not supportred
65
66 #define AUX_MU_SCRATCH (AUX_IO_BASE+0x05C) // Scratch reg.
67
68 // None 16550 features
69 #define AUX_MU_CNTL_REG (AUX_IO_BASE+0x060) // AUX control reg.
70 #define AUX_MU_CNTL_REC_ENBL 0x01 // receiver enable
71 #define AUX_MU_CNTL_TRN_ENBL 0x02 // transmitter enable
72 #define AUX_MU_CNTL_AUTO_RTR 0x04 // RTR set by RX FF level
73 #define AUX_MU_CNTL_AUTO_CTS 0x08 // CTS auto stops transmitter
74 #define AUX_MU_CNTL_FLOW3 0x00 // Stop on RX FF 3 entries left
75 #define AUX_MU_CNTL_FLOW2 0x10 // Stop on RX FF 2 entries left
76 #define AUX_MU_CNTL_FLOW1 0x20 // Stop on RX FF 1 entries left
77 #define AUX_MU_CNTL_FLOW4 0x30 // Stop on RX FF 4 entries left
78 #define AUX_MU_CNTL_AURTRINV 0x40 // Invert AUTO RTR polarity
79 #define AUX_MU_CNTL_AUCTSINV 0x80 // Invert AUTO CTS polarity
80
81
82 #define AUX_MU_STAT_REG (AUX_IO_BASE+0x064) // AUX status reg.
83 #define AUX_MU_STAT_RX_DATA 0x00000001 // RX FF has value
84 #define AUX_MU_STAT_TX_SPACE 0x00000002 // TX FF has space (not full)
85 #define AUX_MU_STAT_RX_IDLE 0x00000004 // Receiver is idle
86 #define AUX_MU_STAT_TX_IDLE 0x00000008 // Transmitter is idle
87 #define AUX_MU_STAT_RX_OFLW 0x00000010 // Receiver FF overflow error
88 #define AUX_MU_STAT_TX_FULL 0x00000020 // Transmit FF full
89 #define AUX_MU_STAT_RTR 0x00000040 // Status of the RTR line
90 #define AUX_MU_STAT_CTS 0x00000080 // Status of the CTS line (fully synced)
91 #define AUX_MU_STAT_TXEMPTY 0x00000100 // TX FF is empty
92 #define AUX_MU_STAT_TXDONE 0x00000200 // TX FF is empty and TX is idle
93 #define AUX_MU_STAT_RXFILL 0x00FF0000 // RX FF fill level
94 #define AUX_MU_STAT_TXFILL 0xFF000000 // TX FF fill level
95
96 #define AUX_MU_BAUD_REG (AUX_IO_BASE+0x068) // Baudrate reg (16 bits)
97 // Baud rate = sysclk/(8*(BAUD_REG+1))
98
99 //
100 // SPI 0 (SPI1 in the device!)
101 //
102 #define AUX_SPI0_CNTL0_REG (AUX_IO_BASE+0x080) // control reg 0
103 #define AUX_SPI_CNTL0_BITS 0x0000003F // Number of bits to send/receive
104 #define AUX_SPI_CNTL0_OUTMS 0x00000040 // Shift MS bit out first)
105 #define AUX_SPI_CNTL0_INVCLK 0x00000080 // Invert SPI_CLK
106 #define AUX_SPI_CNTL0_OUTRISE 0x00000100 // data out leaves on rising clock edge
107 #define AUX_SPI_CNTL0_OUTFALL 0x00000000 // data out leaves on falling clock edge
108 #define AUX_SPI_CNTL0_FFCLR 0x00000200 // Reset fifos (Set and clear bit)
109 #define AUX_SPI_CNTL0_INRISE 0x00000400 // data in on rising clock edge
110 #define AUX_SPI_CNTL0_INFALL 0x00000000 // data in on falling clock edge
111 #define AUX_SPI_CNTL0_SERENBL 0x00000800 // Serial enable (does not disable FFs)
112 #define AUX_SPI_CNTL0_HOLD0 0x00000000 // Dout hold 0 sys clock cycles
113 #define AUX_SPI_CNTL0_HOLD4 0x00001000 // Dout hold 4 sys clock cycle
114 #define AUX_SPI_CNTL0_HOLD7 0x00002000 // Dout hold 7 sys clock cycles
115 #define AUX_SPI_CNTL0_HOLD10 0x00003000 // Dout hold 10 sys clock cycles
116 #define AUX_SPI_CNTL0_VARWID 0x00004000 // Variable width mode (din[15-12]=bits)
117 #define AUX_SPI_CNTL0_CSFROMFF 0x00008000 // CS pattern comesfrom MS 3 TX FIFO bits
118 #define AUX_SPI_CNTL0_POSTIN 0x00010000 // Load last bit after cycles finished
119 #define AUX_SPI_CNTL0_CS_HIGH 0x000E0000 // All CS are high
120 #define AUX_SPI_CNTL0_CS0_N 0x000C0000 // CS 0 low
121 #define AUX_SPI_CNTL0_CS1_N 0x000A0000 // CS 1 low
122 #define AUX_SPI_CNTL0_CS2_N 0x00060000 // CS 2 low
123 #define AUX_SPI_CNTL0_CSA_N 0x00000000 // ALL CS low (test only)
124 #define AUX_SPI_CNTL0_SPEED 0xFFF00000 // SPI clock = sysclock/(2xspeed)
125 #define AUX_SPI_CNTL0_SPEEDSHFT 20 // Speed shift left value
126
127 #define AUX_SPI0_CNTL1_REG (AUX_IO_BASE+0x084) // control reg 1
128 #define AUX_SPI_CNTL1_HOLDIN 0x00000001 // Do not clear DIN register at start
129 #define AUX_SPI_CNTL1_INMS 0x00000002 // Shift data in MS first MS--->LS
130 //#define AUX_SPI_CNTL1_CS_NOW 0x00000004 // Assert CS pattern now
131 #define AUX_SPI_CNTL1_EMPTYIRQ 0x00000040 // IRQ on TX Fifo empty
132 #define AUX_SPI_CNTL1_DONEIRQ 0x00000080 // IRQ on IDLE AND TxFifo empty
133 #define AUX_SPI_CNTL1_CSPLUS1 0x00000100 // CS HI plus 1 bit
134 #define AUX_SPI_CNTL1_CSPLUS2 0x00000200 // CS HI plus 2 bit
135 #define AUX_SPI_CNTL1_CSPLUS3 0x00000300 // CS HI plus 3 bit
136 #define AUX_SPI_CNTL1_CSPLUS4 0x00000400 // CS HI plus 4 bit
137 #define AUX_SPI_CNTL1_CSPLUS5 0x00000500 // CS HI plus 5 bit
138 #define AUX_SPI_CNTL1_CSPLUS6 0x00000600 // CS HI plus 6 bit
139 #define AUX_SPI_CNTL1_CSPLUS7 0x00000700 // CS HI plus 7 bit
140
141 #define AUX_SPI0_STAT_REG (AUX_IO_BASE+0x088) // Status reg.
142 #define AUX_SPI_STAT_BITCNT 0x0000003F // Bits remaining to be shifted out
143 #define AUX_SPI_STAT_BUSY 0x00000040 // FSM is busy
144 #define AUX_SPI_STAT_RXEMPTY 0x00000080 // RX FF is empty
145 #define AUX_SPI_STAT_RXFULL 0x00000100 // RX FF is full
146 #define AUX_SPI_STAT_TXEMPTY 0x00000200 // TX FF is empyt
147 #define AUX_SPI_STAT_TXFULL 0x00000400 // TX FF is full
148 #define AUX_SPI_STAT_RXFILL 0x000F0000 // RX FF fill level
149 #define AUX_SPI_STAT_TXFILL 0x0F000000 // TX FF fill level
150 #define AUX_SPI0_PEEK_REG (AUX_IO_BASE+0x08C) // Read but do not take from FF
151 #define AUX_SPI0_IO_REG (AUX_IO_BASE+0x0A0) // Write = TX, read=RX
152 #define AUX_SPI0_TXHOLD_REG (AUX_IO_BASE+0x0B0) // Write = TX keep cs, read=RX
153
154
155
156 //
157 // SPI 1 (SPI2 in the device!)
158 //
159 #define AUX_SPI1_CNTL0_REG (AUX_IO_BASE+0x0C0)
160 #define AUX_SPI1_CNTL1_REG (AUX_IO_BASE+0x0C4)
161 #define AUX_SPI1_STAT_REG (AUX_IO_BASE+0x0C8)
162 #define AUX_SPI1_PEEK_REG (AUX_IO_BASE+0x0CC)
163 #define AUX_SPI1_IO_REG (AUX_IO_BASE+0x0E0)
164 #define AUX_SPI1_TXHOLD_REG (AUX_IO_BASE+0x0F0) // Write = TX keep cs, read=RX
165
166 //
167 // Some usefull GPIO macros
168 //
169 #define CLR_GPIO(g) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))&= ~(7<<(((g)%10)*3))
170 #define SET_GPIO_ALT(g,a) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))|= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
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