Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / ave_out.h
1 // This file was generated by the create_regs script
2 #define AVE_OUT_BASE 0x7e240000
3 #define AVE_OUT_APB_ID 0x61766538
4 #define AVE_OUT_CTRL HW_REGISTER_RW( 0x7e240000 )
5 #define AVE_OUT_CTRL_MASK 0xc0fff13f
6 #define AVE_OUT_CTRL_WIDTH 32
7 #define AVE_OUT_CTRL_RESET 0x40000100
8 #define AVE_OUT_CTRL_ENABLE_BITS 31:31
9 #define AVE_OUT_CTRL_ENABLE_SET 0x80000000
10 #define AVE_OUT_CTRL_ENABLE_CLR 0x7fffffff
11 #define AVE_OUT_CTRL_ENABLE_MSB 31
12 #define AVE_OUT_CTRL_ENABLE_LSB 31
13 #define AVE_OUT_CTRL_SOFT_RESET_BITS 30:30
14 #define AVE_OUT_CTRL_SOFT_RESET_SET 0x40000000
15 #define AVE_OUT_CTRL_SOFT_RESET_CLR 0xbfffffff
16 #define AVE_OUT_CTRL_SOFT_RESET_MSB 30
17 #define AVE_OUT_CTRL_SOFT_RESET_LSB 30
18 #define AVE_OUT_CTRL_BYTE_SWAP_BITS 23:19
19 #define AVE_OUT_CTRL_BYTE_SWAP_SET 0x00f80000
20 #define AVE_OUT_CTRL_BYTE_SWAP_CLR 0xff07ffff
21 #define AVE_OUT_CTRL_BYTE_SWAP_MSB 23
22 #define AVE_OUT_CTRL_BYTE_SWAP_LSB 19
23 #define AVE_OUT_CTRL_INVERT_DSYNC_BITS 18:18
24 #define AVE_OUT_CTRL_INVERT_DSYNC_SET 0x00040000
25 #define AVE_OUT_CTRL_INVERT_DSYNC_CLR 0xfffbffff
26 #define AVE_OUT_CTRL_INVERT_DSYNC_MSB 18
27 #define AVE_OUT_CTRL_INVERT_DSYNC_LSB 18
28 #define AVE_OUT_CTRL_INVERT_CSYNC_BITS 17:17
29 #define AVE_OUT_CTRL_INVERT_CSYNC_SET 0x00020000
30 #define AVE_OUT_CTRL_INVERT_CSYNC_CLR 0xfffdffff
31 #define AVE_OUT_CTRL_INVERT_CSYNC_MSB 17
32 #define AVE_OUT_CTRL_INVERT_CSYNC_LSB 17
33 #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_BITS 16:16
34 #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_SET 0x00010000
35 #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_CLR 0xfffeffff
36 #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_MSB 16
37 #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_LSB 16
38 #define AVE_OUT_CTRL_INVERT_VSYNC_BITS 15:15
39 #define AVE_OUT_CTRL_INVERT_VSYNC_SET 0x00008000
40 #define AVE_OUT_CTRL_INVERT_VSYNC_CLR 0xffff7fff
41 #define AVE_OUT_CTRL_INVERT_VSYNC_MSB 15
42 #define AVE_OUT_CTRL_INVERT_VSYNC_LSB 15
43 #define AVE_OUT_CTRL_INVERT_HSYNC_BITS 14:14
44 #define AVE_OUT_CTRL_INVERT_HSYNC_SET 0x00004000
45 #define AVE_OUT_CTRL_INVERT_HSYNC_CLR 0xffffbfff
46 #define AVE_OUT_CTRL_INVERT_HSYNC_MSB 14
47 #define AVE_OUT_CTRL_INVERT_HSYNC_LSB 14
48 #define AVE_OUT_CTRL_NTSC_PAL_IDENT_BITS 13:13
49 #define AVE_OUT_CTRL_NTSC_PAL_IDENT_SET 0x00002000
50 #define AVE_OUT_CTRL_NTSC_PAL_IDENT_CLR 0xffffdfff
51 #define AVE_OUT_CTRL_NTSC_PAL_IDENT_MSB 13
52 #define AVE_OUT_CTRL_NTSC_PAL_IDENT_LSB 13
53 #define AVE_OUT_CTRL_INTERLEAVE_BITS 12:12
54 #define AVE_OUT_CTRL_INTERLEAVE_SET 0x00001000
55 #define AVE_OUT_CTRL_INTERLEAVE_CLR 0xffffefff
56 #define AVE_OUT_CTRL_INTERLEAVE_MSB 12
57 #define AVE_OUT_CTRL_INTERLEAVE_LSB 12
58 #define AVE_OUT_CTRL_PRIV_ACCESS_BITS 8:8
59 #define AVE_OUT_CTRL_PRIV_ACCESS_SET 0x00000100
60 #define AVE_OUT_CTRL_PRIV_ACCESS_CLR 0xfffffeff
61 #define AVE_OUT_CTRL_PRIV_ACCESS_MSB 8
62 #define AVE_OUT_CTRL_PRIV_ACCESS_LSB 8
63 #define AVE_OUT_CTRL_MODE_BITS 5:4
64 #define AVE_OUT_CTRL_MODE_SET 0x00000030
65 #define AVE_OUT_CTRL_MODE_CLR 0xffffffcf
66 #define AVE_OUT_CTRL_MODE_MSB 5
67 #define AVE_OUT_CTRL_MODE_LSB 4
68 #define AVE_OUT_CTRL_REFRESH_RATE_BITS 3:2
69 #define AVE_OUT_CTRL_REFRESH_RATE_SET 0x0000000c
70 #define AVE_OUT_CTRL_REFRESH_RATE_CLR 0xfffffff3
71 #define AVE_OUT_CTRL_REFRESH_RATE_MSB 3
72 #define AVE_OUT_CTRL_REFRESH_RATE_LSB 2
73 #define AVE_OUT_CTRL_COEFF_IRQ_EN_BITS 1:1
74 #define AVE_OUT_CTRL_COEFF_IRQ_EN_SET 0x00000002
75 #define AVE_OUT_CTRL_COEFF_IRQ_EN_CLR 0xfffffffd
76 #define AVE_OUT_CTRL_COEFF_IRQ_EN_MSB 1
77 #define AVE_OUT_CTRL_COEFF_IRQ_EN_LSB 1
78 #define AVE_OUT_CTRL_ERROR_IRQ_EN_BITS 0:0
79 #define AVE_OUT_CTRL_ERROR_IRQ_EN_SET 0x00000001
80 #define AVE_OUT_CTRL_ERROR_IRQ_EN_CLR 0xfffffffe
81 #define AVE_OUT_CTRL_ERROR_IRQ_EN_MSB 0
82 #define AVE_OUT_CTRL_ERROR_IRQ_EN_LSB 0
83 #define AVE_OUT_STATUS HW_REGISTER_RW( 0x7e240004 )
84 #define AVE_OUT_STATUS_MASK 0x000003f7
85 #define AVE_OUT_STATUS_WIDTH 10
86 #define AVE_OUT_STATUS_RESET 0000000000
87 #define AVE_OUT_STATUS_VSYNC_BITS 9:9
88 #define AVE_OUT_STATUS_VSYNC_SET 0x00000200
89 #define AVE_OUT_STATUS_VSYNC_CLR 0xfffffdff
90 #define AVE_OUT_STATUS_VSYNC_MSB 9
91 #define AVE_OUT_STATUS_VSYNC_LSB 9
92 #define AVE_OUT_STATUS_VBACK_PORCH_BITS 8:8
93 #define AVE_OUT_STATUS_VBACK_PORCH_SET 0x00000100
94 #define AVE_OUT_STATUS_VBACK_PORCH_CLR 0xfffffeff
95 #define AVE_OUT_STATUS_VBACK_PORCH_MSB 8
96 #define AVE_OUT_STATUS_VBACK_PORCH_LSB 8
97 #define AVE_OUT_STATUS_VFRONT_PORCH_BITS 7:7
98 #define AVE_OUT_STATUS_VFRONT_PORCH_SET 0x00000080
99 #define AVE_OUT_STATUS_VFRONT_PORCH_CLR 0xffffff7f
100 #define AVE_OUT_STATUS_VFRONT_PORCH_MSB 7
101 #define AVE_OUT_STATUS_VFRONT_PORCH_LSB 7
102 #define AVE_OUT_STATUS_HSYNC_BITS 6:6
103 #define AVE_OUT_STATUS_HSYNC_SET 0x00000040
104 #define AVE_OUT_STATUS_HSYNC_CLR 0xffffffbf
105 #define AVE_OUT_STATUS_HSYNC_MSB 6
106 #define AVE_OUT_STATUS_HSYNC_LSB 6
107 #define AVE_OUT_STATUS_HBACK_PORCH_BITS 5:5
108 #define AVE_OUT_STATUS_HBACK_PORCH_SET 0x00000020
109 #define AVE_OUT_STATUS_HBACK_PORCH_CLR 0xffffffdf
110 #define AVE_OUT_STATUS_HBACK_PORCH_MSB 5
111 #define AVE_OUT_STATUS_HBACK_PORCH_LSB 5
112 #define AVE_OUT_STATUS_HFRONT_PORCH_BITS 4:4
113 #define AVE_OUT_STATUS_HFRONT_PORCH_SET 0x00000010
114 #define AVE_OUT_STATUS_HFRONT_PORCH_CLR 0xffffffef
115 #define AVE_OUT_STATUS_HFRONT_PORCH_MSB 4
116 #define AVE_OUT_STATUS_HFRONT_PORCH_LSB 4
117 #define AVE_OUT_STATUS_COEFF_ERROR_BITS 2:2
118 #define AVE_OUT_STATUS_COEFF_ERROR_SET 0x00000004
119 #define AVE_OUT_STATUS_COEFF_ERROR_CLR 0xfffffffb
120 #define AVE_OUT_STATUS_COEFF_ERROR_MSB 2
121 #define AVE_OUT_STATUS_COEFF_ERROR_LSB 2
122 #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_BITS 1:1
123 #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_SET 0x00000002
124 #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_CLR 0xfffffffd
125 #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_MSB 1
126 #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_LSB 1
127 #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_BITS 0:0
128 #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_SET 0x00000001
129 #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_CLR 0xfffffffe
130 #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_MSB 0
131 #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_LSB 0
132 #define AVE_OUT_OFFSET HW_REGISTER_RW( 0x7e240008 )
133 #define AVE_OUT_OFFSET_MASK 0x80ffffff
134 #define AVE_OUT_OFFSET_WIDTH 32
135 #define AVE_OUT_OFFSET_RESET 0x80109090
136 #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_BITS 31:31
137 #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_SET 0x80000000
138 #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_CLR 0x7fffffff
139 #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_MSB 31
140 #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_LSB 31
141 #define AVE_OUT_OFFSET_RED_OFFSET_BITS 23:16
142 #define AVE_OUT_OFFSET_RED_OFFSET_SET 0x00ff0000
143 #define AVE_OUT_OFFSET_RED_OFFSET_CLR 0xff00ffff
144 #define AVE_OUT_OFFSET_RED_OFFSET_MSB 23
145 #define AVE_OUT_OFFSET_RED_OFFSET_LSB 16
146 #define AVE_OUT_OFFSET_GREEN_OFFSET_BITS 15:8
147 #define AVE_OUT_OFFSET_GREEN_OFFSET_SET 0x0000ff00
148 #define AVE_OUT_OFFSET_GREEN_OFFSET_CLR 0xffff00ff
149 #define AVE_OUT_OFFSET_GREEN_OFFSET_MSB 15
150 #define AVE_OUT_OFFSET_GREEN_OFFSET_LSB 8
151 #define AVE_OUT_OFFSET_BLUE_OFFSET_BITS 7:0
152 #define AVE_OUT_OFFSET_BLUE_OFFSET_SET 0x000000ff
153 #define AVE_OUT_OFFSET_BLUE_OFFSET_CLR 0xffffff00
154 #define AVE_OUT_OFFSET_BLUE_OFFSET_MSB 7
155 #define AVE_OUT_OFFSET_BLUE_OFFSET_LSB 0
156 #define AVE_OUT_Y_COEFF HW_REGISTER_RW( 0x7e24000c )
157 #define AVE_OUT_Y_COEFF_MASK 0x3fffffff
158 #define AVE_OUT_Y_COEFF_WIDTH 30
159 #define AVE_OUT_Y_COEFF_RESET 0x0994b43a
160 #define AVE_OUT_Y_COEFF_RED_COEFF_BITS 29:20
161 #define AVE_OUT_Y_COEFF_RED_COEFF_SET 0x3ff00000
162 #define AVE_OUT_Y_COEFF_RED_COEFF_CLR 0xc00fffff
163 #define AVE_OUT_Y_COEFF_RED_COEFF_MSB 29
164 #define AVE_OUT_Y_COEFF_RED_COEFF_LSB 20
165 #define AVE_OUT_Y_COEFF_GREEN_COEFF_BITS 19:10
166 #define AVE_OUT_Y_COEFF_GREEN_COEFF_SET 0x000ffc00
167 #define AVE_OUT_Y_COEFF_GREEN_COEFF_CLR 0xfff003ff
168 #define AVE_OUT_Y_COEFF_GREEN_COEFF_MSB 19
169 #define AVE_OUT_Y_COEFF_GREEN_COEFF_LSB 10
170 #define AVE_OUT_Y_COEFF_BLUE_COEFF_BITS 9:0
171 #define AVE_OUT_Y_COEFF_BLUE_COEFF_SET 0x000003ff
172 #define AVE_OUT_Y_COEFF_BLUE_COEFF_CLR 0xfffffc00
173 #define AVE_OUT_Y_COEFF_BLUE_COEFF_MSB 9
174 #define AVE_OUT_Y_COEFF_BLUE_COEFF_LSB 0
175 #define AVE_OUT_CB_COEFF HW_REGISTER_RW( 0x7e240010 )
176 #define AVE_OUT_CB_COEFF_MASK 0x3fffffff
177 #define AVE_OUT_CB_COEFF_WIDTH 30
178 #define AVE_OUT_CB_COEFF_RESET 0x3a9d5900
179 #define AVE_OUT_CB_COEFF_RED_COEFF_BITS 29:20
180 #define AVE_OUT_CB_COEFF_RED_COEFF_SET 0x3ff00000
181 #define AVE_OUT_CB_COEFF_RED_COEFF_CLR 0xc00fffff
182 #define AVE_OUT_CB_COEFF_RED_COEFF_MSB 29
183 #define AVE_OUT_CB_COEFF_RED_COEFF_LSB 20
184 #define AVE_OUT_CB_COEFF_GREEN_COEFF_BITS 19:10
185 #define AVE_OUT_CB_COEFF_GREEN_COEFF_SET 0x000ffc00
186 #define AVE_OUT_CB_COEFF_GREEN_COEFF_CLR 0xfff003ff
187 #define AVE_OUT_CB_COEFF_GREEN_COEFF_MSB 19
188 #define AVE_OUT_CB_COEFF_GREEN_COEFF_LSB 10
189 #define AVE_OUT_CB_COEFF_BLUE_COEFF_BITS 9:0
190 #define AVE_OUT_CB_COEFF_BLUE_COEFF_SET 0x000003ff
191 #define AVE_OUT_CB_COEFF_BLUE_COEFF_CLR 0xfffffc00
192 #define AVE_OUT_CB_COEFF_BLUE_COEFF_MSB 9
193 #define AVE_OUT_CB_COEFF_BLUE_COEFF_LSB 0
194 #define AVE_OUT_CR_COEFF HW_REGISTER_RW( 0x7e240014 )
195 #define AVE_OUT_CR_COEFF_MASK 0x3fffffff
196 #define AVE_OUT_CR_COEFF_WIDTH 30
197 #define AVE_OUT_CR_COEFF_RESET 0x100ca7d6
198 #define AVE_OUT_CR_COEFF_RED_COEFF_BITS 29:20
199 #define AVE_OUT_CR_COEFF_RED_COEFF_SET 0x3ff00000
200 #define AVE_OUT_CR_COEFF_RED_COEFF_CLR 0xc00fffff
201 #define AVE_OUT_CR_COEFF_RED_COEFF_MSB 29
202 #define AVE_OUT_CR_COEFF_RED_COEFF_LSB 20
203 #define AVE_OUT_CR_COEFF_GREEN_COEFF_BITS 19:10
204 #define AVE_OUT_CR_COEFF_GREEN_COEFF_SET 0x000ffc00
205 #define AVE_OUT_CR_COEFF_GREEN_COEFF_CLR 0xfff003ff
206 #define AVE_OUT_CR_COEFF_GREEN_COEFF_MSB 19
207 #define AVE_OUT_CR_COEFF_GREEN_COEFF_LSB 10
208 #define AVE_OUT_CR_COEFF_BLUE_COEFF_BITS 9:0
209 #define AVE_OUT_CR_COEFF_BLUE_COEFF_SET 0x000003ff
210 #define AVE_OUT_CR_COEFF_BLUE_COEFF_CLR 0xfffffc00
211 #define AVE_OUT_CR_COEFF_BLUE_COEFF_MSB 9
212 #define AVE_OUT_CR_COEFF_BLUE_COEFF_LSB 0
213 #define AVE_OUT_BLOCK_ID HW_REGISTER_RW( 0x7e240060 )
214 #define AVE_OUT_BLOCK_ID_MASK 0xffffffff
215 #define AVE_OUT_BLOCK_ID_WIDTH 32
216 #define AVE_OUT_BLOCK_ID_RESET 0x61766538
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