Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / axi_dma0.h
1 // This file was generated by the create_regs script
2 #define DMA0_BASE 0x7e007000
3 #define DMA0_CS HW_REGISTER_RW( 0x7e007000 )
4 #define DMA0_CS_MASK 0xf0ff017f
5 #define DMA0_CS_WIDTH 32
6 #define DMA0_CS_RESET 0000000000
7 #define DMA0_CS_RESET_BITS 31:31
8 #define DMA0_CS_RESET_SET 0x80000000
9 #define DMA0_CS_RESET_CLR 0x7fffffff
10 #define DMA0_CS_RESET_MSB 31
11 #define DMA0_CS_RESET_LSB 31
12 #define DMA0_CS_ABORT_BITS 30:30
13 #define DMA0_CS_ABORT_SET 0x40000000
14 #define DMA0_CS_ABORT_CLR 0xbfffffff
15 #define DMA0_CS_ABORT_MSB 30
16 #define DMA0_CS_ABORT_LSB 30
17 #define DMA0_CS_DISDEBUG_BITS 29:29
18 #define DMA0_CS_DISDEBUG_SET 0x20000000
19 #define DMA0_CS_DISDEBUG_CLR 0xdfffffff
20 #define DMA0_CS_DISDEBUG_MSB 29
21 #define DMA0_CS_DISDEBUG_LSB 29
22 #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
23 #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
24 #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
25 #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
26 #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
27 #define DMA0_CS_PANIC_PRIORITY_BITS 23:20
28 #define DMA0_CS_PANIC_PRIORITY_SET 0x00f00000
29 #define DMA0_CS_PANIC_PRIORITY_CLR 0xff0fffff
30 #define DMA0_CS_PANIC_PRIORITY_MSB 23
31 #define DMA0_CS_PANIC_PRIORITY_LSB 20
32 #define DMA0_CS_PRIORITY_BITS 19:16
33 #define DMA0_CS_PRIORITY_SET 0x000f0000
34 #define DMA0_CS_PRIORITY_CLR 0xfff0ffff
35 #define DMA0_CS_PRIORITY_MSB 19
36 #define DMA0_CS_PRIORITY_LSB 16
37 #define DMA0_CS_ERROR_BITS 8:8
38 #define DMA0_CS_ERROR_SET 0x00000100
39 #define DMA0_CS_ERROR_CLR 0xfffffeff
40 #define DMA0_CS_ERROR_MSB 8
41 #define DMA0_CS_ERROR_LSB 8
42 #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
43 #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
44 #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
45 #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
46 #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
47 #define DMA0_CS_DREQ_STOPS_DMA_BITS 5:5
48 #define DMA0_CS_DREQ_STOPS_DMA_SET 0x00000020
49 #define DMA0_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
50 #define DMA0_CS_DREQ_STOPS_DMA_MSB 5
51 #define DMA0_CS_DREQ_STOPS_DMA_LSB 5
52 #define DMA0_CS_PAUSED_BITS 4:4
53 #define DMA0_CS_PAUSED_SET 0x00000010
54 #define DMA0_CS_PAUSED_CLR 0xffffffef
55 #define DMA0_CS_PAUSED_MSB 4
56 #define DMA0_CS_PAUSED_LSB 4
57 #define DMA0_CS_DREQ_BITS 3:3
58 #define DMA0_CS_DREQ_SET 0x00000008
59 #define DMA0_CS_DREQ_CLR 0xfffffff7
60 #define DMA0_CS_DREQ_MSB 3
61 #define DMA0_CS_DREQ_LSB 3
62 #define DMA0_CS_INT_BITS 2:2
63 #define DMA0_CS_INT_SET 0x00000004
64 #define DMA0_CS_INT_CLR 0xfffffffb
65 #define DMA0_CS_INT_MSB 2
66 #define DMA0_CS_INT_LSB 2
67 #define DMA0_CS_END_BITS 1:1
68 #define DMA0_CS_END_SET 0x00000002
69 #define DMA0_CS_END_CLR 0xfffffffd
70 #define DMA0_CS_END_MSB 1
71 #define DMA0_CS_END_LSB 1
72 #define DMA0_CS_ACTIVE_BITS 0:0
73 #define DMA0_CS_ACTIVE_SET 0x00000001
74 #define DMA0_CS_ACTIVE_CLR 0xfffffffe
75 #define DMA0_CS_ACTIVE_MSB 0
76 #define DMA0_CS_ACTIVE_LSB 0
77 #define DMA0_CONBLK_AD HW_REGISTER_RW( 0x7e007004 )
78 #define DMA0_CONBLK_AD_MASK 0xffffffe0
79 #define DMA0_CONBLK_AD_WIDTH 32
80 #define DMA0_CONBLK_AD_RESET 0000000000
81 #define DMA0_CONBLK_AD_SCB_ADDR_BITS 31:5
82 #define DMA0_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
83 #define DMA0_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
84 #define DMA0_CONBLK_AD_SCB_ADDR_MSB 31
85 #define DMA0_CONBLK_AD_SCB_ADDR_LSB 5
86 #define DMA0_TI HW_REGISTER_RO( 0x7e007008 )
87 #define DMA0_TI_MASK 0x07fffffb
88 #define DMA0_TI_WIDTH 27
89 #define DMA0_TI_NO_WIDE_BURSTS_BITS 26:26
90 #define DMA0_TI_NO_WIDE_BURSTS_SET 0x04000000
91 #define DMA0_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
92 #define DMA0_TI_NO_WIDE_BURSTS_MSB 26
93 #define DMA0_TI_NO_WIDE_BURSTS_LSB 26
94 #define DMA0_TI_WAITS_BITS 25:21
95 #define DMA0_TI_WAITS_SET 0x03e00000
96 #define DMA0_TI_WAITS_CLR 0xfc1fffff
97 #define DMA0_TI_WAITS_MSB 25
98 #define DMA0_TI_WAITS_LSB 21
99 #define DMA0_TI_PERMAP_BITS 20:16
100 #define DMA0_TI_PERMAP_SET 0x001f0000
101 #define DMA0_TI_PERMAP_CLR 0xffe0ffff
102 #define DMA0_TI_PERMAP_MSB 20
103 #define DMA0_TI_PERMAP_LSB 16
104 #define DMA0_TI_BURST_LENGTH_BITS 15:12
105 #define DMA0_TI_BURST_LENGTH_SET 0x0000f000
106 #define DMA0_TI_BURST_LENGTH_CLR 0xffff0fff
107 #define DMA0_TI_BURST_LENGTH_MSB 15
108 #define DMA0_TI_BURST_LENGTH_LSB 12
109 #define DMA0_TI_SRC_IGNORE_BITS 11:11
110 #define DMA0_TI_SRC_IGNORE_SET 0x00000800
111 #define DMA0_TI_SRC_IGNORE_CLR 0xfffff7ff
112 #define DMA0_TI_SRC_IGNORE_MSB 11
113 #define DMA0_TI_SRC_IGNORE_LSB 11
114 #define DMA0_TI_SRC_DREQ_BITS 10:10
115 #define DMA0_TI_SRC_DREQ_SET 0x00000400
116 #define DMA0_TI_SRC_DREQ_CLR 0xfffffbff
117 #define DMA0_TI_SRC_DREQ_MSB 10
118 #define DMA0_TI_SRC_DREQ_LSB 10
119 #define DMA0_TI_SRC_WIDTH_BITS 9:9
120 #define DMA0_TI_SRC_WIDTH_SET 0x00000200
121 #define DMA0_TI_SRC_WIDTH_CLR 0xfffffdff
122 #define DMA0_TI_SRC_WIDTH_MSB 9
123 #define DMA0_TI_SRC_WIDTH_LSB 9
124 #define DMA0_TI_SRC_INC_BITS 8:8
125 #define DMA0_TI_SRC_INC_SET 0x00000100
126 #define DMA0_TI_SRC_INC_CLR 0xfffffeff
127 #define DMA0_TI_SRC_INC_MSB 8
128 #define DMA0_TI_SRC_INC_LSB 8
129 #define DMA0_TI_DEST_IGNORE_BITS 7:7
130 #define DMA0_TI_DEST_IGNORE_SET 0x00000080
131 #define DMA0_TI_DEST_IGNORE_CLR 0xffffff7f
132 #define DMA0_TI_DEST_IGNORE_MSB 7
133 #define DMA0_TI_DEST_IGNORE_LSB 7
134 #define DMA0_TI_DEST_DREQ_BITS 6:6
135 #define DMA0_TI_DEST_DREQ_SET 0x00000040
136 #define DMA0_TI_DEST_DREQ_CLR 0xffffffbf
137 #define DMA0_TI_DEST_DREQ_MSB 6
138 #define DMA0_TI_DEST_DREQ_LSB 6
139 #define DMA0_TI_DEST_WIDTH_BITS 5:5
140 #define DMA0_TI_DEST_WIDTH_SET 0x00000020
141 #define DMA0_TI_DEST_WIDTH_CLR 0xffffffdf
142 #define DMA0_TI_DEST_WIDTH_MSB 5
143 #define DMA0_TI_DEST_WIDTH_LSB 5
144 #define DMA0_TI_DEST_INC_BITS 4:4
145 #define DMA0_TI_DEST_INC_SET 0x00000010
146 #define DMA0_TI_DEST_INC_CLR 0xffffffef
147 #define DMA0_TI_DEST_INC_MSB 4
148 #define DMA0_TI_DEST_INC_LSB 4
149 #define DMA0_TI_WAIT_RESP_BITS 3:3
150 #define DMA0_TI_WAIT_RESP_SET 0x00000008
151 #define DMA0_TI_WAIT_RESP_CLR 0xfffffff7
152 #define DMA0_TI_WAIT_RESP_MSB 3
153 #define DMA0_TI_WAIT_RESP_LSB 3
154 #define DMA0_TI_TDMODE_BITS 1:1
155 #define DMA0_TI_TDMODE_SET 0x00000002
156 #define DMA0_TI_TDMODE_CLR 0xfffffffd
157 #define DMA0_TI_TDMODE_MSB 1
158 #define DMA0_TI_TDMODE_LSB 1
159 #define DMA0_TI_INTEN_BITS 0:0
160 #define DMA0_TI_INTEN_SET 0x00000001
161 #define DMA0_TI_INTEN_CLR 0xfffffffe
162 #define DMA0_TI_INTEN_MSB 0
163 #define DMA0_TI_INTEN_LSB 0
164 #define DMA0_SOURCE_AD HW_REGISTER_RO( 0x7e00700c )
165 #define DMA0_SOURCE_AD_MASK 0xffffffff
166 #define DMA0_SOURCE_AD_WIDTH 32
167 #define DMA0_SOURCE_AD_S_ADDR_BITS 31:0
168 #define DMA0_SOURCE_AD_S_ADDR_SET 0xffffffff
169 #define DMA0_SOURCE_AD_S_ADDR_CLR 0x00000000
170 #define DMA0_SOURCE_AD_S_ADDR_MSB 31
171 #define DMA0_SOURCE_AD_S_ADDR_LSB 0
172 #define DMA0_DEST_AD HW_REGISTER_RO( 0x7e007010 )
173 #define DMA0_DEST_AD_MASK 0xffffffff
174 #define DMA0_DEST_AD_WIDTH 32
175 #define DMA0_DEST_AD_D_ADDR_BITS 31:0
176 #define DMA0_DEST_AD_D_ADDR_SET 0xffffffff
177 #define DMA0_DEST_AD_D_ADDR_CLR 0x00000000
178 #define DMA0_DEST_AD_D_ADDR_MSB 31
179 #define DMA0_DEST_AD_D_ADDR_LSB 0
180 #define DMA0_TXFR_LEN HW_REGISTER_RO( 0x7e007014 )
181 #define DMA0_TXFR_LEN_MASK 0x3fffffff
182 #define DMA0_TXFR_LEN_WIDTH 30
183 #define DMA0_TXFR_LEN_YLENGTH_BITS 29:16
184 #define DMA0_TXFR_LEN_YLENGTH_SET 0x3fff0000
185 #define DMA0_TXFR_LEN_YLENGTH_CLR 0xc000ffff
186 #define DMA0_TXFR_LEN_YLENGTH_MSB 29
187 #define DMA0_TXFR_LEN_YLENGTH_LSB 16
188 #define DMA0_TXFR_LEN_XLENGTH_BITS 15:0
189 #define DMA0_TXFR_LEN_XLENGTH_SET 0x0000ffff
190 #define DMA0_TXFR_LEN_XLENGTH_CLR 0xffff0000
191 #define DMA0_TXFR_LEN_XLENGTH_MSB 15
192 #define DMA0_TXFR_LEN_XLENGTH_LSB 0
193 #define DMA0_STRIDE HW_REGISTER_RO( 0x7e007018 )
194 #define DMA0_STRIDE_MASK 0xffffffff
195 #define DMA0_STRIDE_WIDTH 32
196 #define DMA0_STRIDE_D_STRIDE_BITS 31:16
197 #define DMA0_STRIDE_D_STRIDE_SET 0xffff0000
198 #define DMA0_STRIDE_D_STRIDE_CLR 0x0000ffff
199 #define DMA0_STRIDE_D_STRIDE_MSB 31
200 #define DMA0_STRIDE_D_STRIDE_LSB 16
201 #define DMA0_STRIDE_S_STRIDE_BITS 15:0
202 #define DMA0_STRIDE_S_STRIDE_SET 0x0000ffff
203 #define DMA0_STRIDE_S_STRIDE_CLR 0xffff0000
204 #define DMA0_STRIDE_S_STRIDE_MSB 15
205 #define DMA0_STRIDE_S_STRIDE_LSB 0
206 #define DMA0_NEXTCONBK HW_REGISTER_RO( 0x7e00701c )
207 #define DMA0_NEXTCONBK_MASK 0xffffffe0
208 #define DMA0_NEXTCONBK_WIDTH 32
209 #define DMA0_NEXTCONBK_ADDR_BITS 31:5
210 #define DMA0_NEXTCONBK_ADDR_SET 0xffffffe0
211 #define DMA0_NEXTCONBK_ADDR_CLR 0x0000001f
212 #define DMA0_NEXTCONBK_ADDR_MSB 31
213 #define DMA0_NEXTCONBK_ADDR_LSB 5
214 #define DMA0_DEBUG HW_REGISTER_RW( 0x7e007020 )
215 #define DMA0_DEBUG_MASK 0x1ffffff7
216 #define DMA0_DEBUG_WIDTH 29
217 #define DMA0_DEBUG_RESET 0000000000
218 #define DMA0_DEBUG_LITE_BITS 28:28
219 #define DMA0_DEBUG_LITE_SET 0x10000000
220 #define DMA0_DEBUG_LITE_CLR 0xefffffff
221 #define DMA0_DEBUG_LITE_MSB 28
222 #define DMA0_DEBUG_LITE_LSB 28
223 #define DMA0_DEBUG_VERSION_BITS 27:25
224 #define DMA0_DEBUG_VERSION_SET 0x0e000000
225 #define DMA0_DEBUG_VERSION_CLR 0xf1ffffff
226 #define DMA0_DEBUG_VERSION_MSB 27
227 #define DMA0_DEBUG_VERSION_LSB 25
228 #define DMA0_DEBUG_DMA_STATE_BITS 24:16
229 #define DMA0_DEBUG_DMA_STATE_SET 0x01ff0000
230 #define DMA0_DEBUG_DMA_STATE_CLR 0xfe00ffff
231 #define DMA0_DEBUG_DMA_STATE_MSB 24
232 #define DMA0_DEBUG_DMA_STATE_LSB 16
233 #define DMA0_DEBUG_DMA_ID_BITS 15:8
234 #define DMA0_DEBUG_DMA_ID_SET 0x0000ff00
235 #define DMA0_DEBUG_DMA_ID_CLR 0xffff00ff
236 #define DMA0_DEBUG_DMA_ID_MSB 15
237 #define DMA0_DEBUG_DMA_ID_LSB 8
238 #define DMA0_DEBUG_OUTSTANDING_WRITES_BITS 7:4
239 #define DMA0_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
240 #define DMA0_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
241 #define DMA0_DEBUG_OUTSTANDING_WRITES_MSB 7
242 #define DMA0_DEBUG_OUTSTANDING_WRITES_LSB 4
243 #define DMA0_DEBUG_READ_ERROR_BITS 2:2
244 #define DMA0_DEBUG_READ_ERROR_SET 0x00000004
245 #define DMA0_DEBUG_READ_ERROR_CLR 0xfffffffb
246 #define DMA0_DEBUG_READ_ERROR_MSB 2
247 #define DMA0_DEBUG_READ_ERROR_LSB 2
248 #define DMA0_DEBUG_FIFO_ERROR_BITS 1:1
249 #define DMA0_DEBUG_FIFO_ERROR_SET 0x00000002
250 #define DMA0_DEBUG_FIFO_ERROR_CLR 0xfffffffd
251 #define DMA0_DEBUG_FIFO_ERROR_MSB 1
252 #define DMA0_DEBUG_FIFO_ERROR_LSB 1
253 #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
254 #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
255 #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
256 #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
257 #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
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