Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / axi_dma_top.h
1 // This file was generated by the create_regs script
2 #define DMA_BASE 0x7e007fe0
3 #define DMA_INT_STATUS HW_REGISTER_RO( 0x7e007fe0 )
4 #define DMA_INT_STATUS_MASK 0x0000ffff
5 #define DMA_INT_STATUS_WIDTH 16
6 #define DMA_INT_STATUS_RESET 0000000000
7 #define DMA_INT_STATUS_INT0_BITS 0:0
8 #define DMA_INT_STATUS_INT0_SET 0x00000001
9 #define DMA_INT_STATUS_INT0_CLR 0xfffffffe
10 #define DMA_INT_STATUS_INT0_MSB 0
11 #define DMA_INT_STATUS_INT0_LSB 0
12 #define DMA_INT_STATUS_INT1_BITS 1:1
13 #define DMA_INT_STATUS_INT1_SET 0x00000002
14 #define DMA_INT_STATUS_INT1_CLR 0xfffffffd
15 #define DMA_INT_STATUS_INT1_MSB 1
16 #define DMA_INT_STATUS_INT1_LSB 1
17 #define DMA_INT_STATUS_INT2_BITS 2:2
18 #define DMA_INT_STATUS_INT2_SET 0x00000004
19 #define DMA_INT_STATUS_INT2_CLR 0xfffffffb
20 #define DMA_INT_STATUS_INT2_MSB 2
21 #define DMA_INT_STATUS_INT2_LSB 2
22 #define DMA_INT_STATUS_INT3_BITS 3:3
23 #define DMA_INT_STATUS_INT3_SET 0x00000008
24 #define DMA_INT_STATUS_INT3_CLR 0xfffffff7
25 #define DMA_INT_STATUS_INT3_MSB 3
26 #define DMA_INT_STATUS_INT3_LSB 3
27 #define DMA_INT_STATUS_INT4_BITS 4:4
28 #define DMA_INT_STATUS_INT4_SET 0x00000010
29 #define DMA_INT_STATUS_INT4_CLR 0xffffffef
30 #define DMA_INT_STATUS_INT4_MSB 4
31 #define DMA_INT_STATUS_INT4_LSB 4
32 #define DMA_INT_STATUS_INT5_BITS 5:5
33 #define DMA_INT_STATUS_INT5_SET 0x00000020
34 #define DMA_INT_STATUS_INT5_CLR 0xffffffdf
35 #define DMA_INT_STATUS_INT5_MSB 5
36 #define DMA_INT_STATUS_INT5_LSB 5
37 #define DMA_INT_STATUS_INT6_BITS 6:6
38 #define DMA_INT_STATUS_INT6_SET 0x00000040
39 #define DMA_INT_STATUS_INT6_CLR 0xffffffbf
40 #define DMA_INT_STATUS_INT6_MSB 6
41 #define DMA_INT_STATUS_INT6_LSB 6
42 #define DMA_INT_STATUS_INT7_BITS 7:7
43 #define DMA_INT_STATUS_INT7_SET 0x00000080
44 #define DMA_INT_STATUS_INT7_CLR 0xffffff7f
45 #define DMA_INT_STATUS_INT7_MSB 7
46 #define DMA_INT_STATUS_INT7_LSB 7
47 #define DMA_INT_STATUS_INT8_BITS 8:8
48 #define DMA_INT_STATUS_INT8_SET 0x00000100
49 #define DMA_INT_STATUS_INT8_CLR 0xfffffeff
50 #define DMA_INT_STATUS_INT8_MSB 8
51 #define DMA_INT_STATUS_INT8_LSB 8
52 #define DMA_INT_STATUS_INT9_BITS 9:9
53 #define DMA_INT_STATUS_INT9_SET 0x00000200
54 #define DMA_INT_STATUS_INT9_CLR 0xfffffdff
55 #define DMA_INT_STATUS_INT9_MSB 9
56 #define DMA_INT_STATUS_INT9_LSB 9
57 #define DMA_INT_STATUS_INT10_BITS 10:10
58 #define DMA_INT_STATUS_INT10_SET 0x00000400
59 #define DMA_INT_STATUS_INT10_CLR 0xfffffbff
60 #define DMA_INT_STATUS_INT10_MSB 10
61 #define DMA_INT_STATUS_INT10_LSB 10
62 #define DMA_INT_STATUS_INT11_BITS 11:11
63 #define DMA_INT_STATUS_INT11_SET 0x00000800
64 #define DMA_INT_STATUS_INT11_CLR 0xfffff7ff
65 #define DMA_INT_STATUS_INT11_MSB 11
66 #define DMA_INT_STATUS_INT11_LSB 11
67 #define DMA_INT_STATUS_INT12_BITS 12:12
68 #define DMA_INT_STATUS_INT12_SET 0x00001000
69 #define DMA_INT_STATUS_INT12_CLR 0xffffefff
70 #define DMA_INT_STATUS_INT12_MSB 12
71 #define DMA_INT_STATUS_INT12_LSB 12
72 #define DMA_INT_STATUS_INT13_BITS 13:13
73 #define DMA_INT_STATUS_INT13_SET 0x00002000
74 #define DMA_INT_STATUS_INT13_CLR 0xffffdfff
75 #define DMA_INT_STATUS_INT13_MSB 13
76 #define DMA_INT_STATUS_INT13_LSB 13
77 #define DMA_INT_STATUS_INT14_BITS 14:14
78 #define DMA_INT_STATUS_INT14_SET 0x00004000
79 #define DMA_INT_STATUS_INT14_CLR 0xffffbfff
80 #define DMA_INT_STATUS_INT14_MSB 14
81 #define DMA_INT_STATUS_INT14_LSB 14
82 #define DMA_INT_STATUS_INT15_BITS 15:15
83 #define DMA_INT_STATUS_INT15_SET 0x00008000
84 #define DMA_INT_STATUS_INT15_CLR 0xffff7fff
85 #define DMA_INT_STATUS_INT15_MSB 15
86 #define DMA_INT_STATUS_INT15_LSB 15
87 #define DMA_ENABLE HW_REGISTER_RW( 0x7e007ff0 )
88 #define DMA_ENABLE_MASK 0x00007fff
89 #define DMA_ENABLE_WIDTH 15
90 #define DMA_ENABLE_RESET 0x00007fff
91 #define DMA_ENABLE_EN0_BITS 0:0
92 #define DMA_ENABLE_EN0_SET 0x00000001
93 #define DMA_ENABLE_EN0_CLR 0xfffffffe
94 #define DMA_ENABLE_EN0_MSB 0
95 #define DMA_ENABLE_EN0_LSB 0
96 #define DMA_ENABLE_EN1_BITS 1:1
97 #define DMA_ENABLE_EN1_SET 0x00000002
98 #define DMA_ENABLE_EN1_CLR 0xfffffffd
99 #define DMA_ENABLE_EN1_MSB 1
100 #define DMA_ENABLE_EN1_LSB 1
101 #define DMA_ENABLE_EN2_BITS 2:2
102 #define DMA_ENABLE_EN2_SET 0x00000004
103 #define DMA_ENABLE_EN2_CLR 0xfffffffb
104 #define DMA_ENABLE_EN2_MSB 2
105 #define DMA_ENABLE_EN2_LSB 2
106 #define DMA_ENABLE_EN3_BITS 3:3
107 #define DMA_ENABLE_EN3_SET 0x00000008
108 #define DMA_ENABLE_EN3_CLR 0xfffffff7
109 #define DMA_ENABLE_EN3_MSB 3
110 #define DMA_ENABLE_EN3_LSB 3
111 #define DMA_ENABLE_EN4_BITS 4:4
112 #define DMA_ENABLE_EN4_SET 0x00000010
113 #define DMA_ENABLE_EN4_CLR 0xffffffef
114 #define DMA_ENABLE_EN4_MSB 4
115 #define DMA_ENABLE_EN4_LSB 4
116 #define DMA_ENABLE_EN5_BITS 5:5
117 #define DMA_ENABLE_EN5_SET 0x00000020
118 #define DMA_ENABLE_EN5_CLR 0xffffffdf
119 #define DMA_ENABLE_EN5_MSB 5
120 #define DMA_ENABLE_EN5_LSB 5
121 #define DMA_ENABLE_EN6_BITS 6:6
122 #define DMA_ENABLE_EN6_SET 0x00000040
123 #define DMA_ENABLE_EN6_CLR 0xffffffbf
124 #define DMA_ENABLE_EN6_MSB 6
125 #define DMA_ENABLE_EN6_LSB 6
126 #define DMA_ENABLE_EN7_BITS 7:7
127 #define DMA_ENABLE_EN7_SET 0x00000080
128 #define DMA_ENABLE_EN7_CLR 0xffffff7f
129 #define DMA_ENABLE_EN7_MSB 7
130 #define DMA_ENABLE_EN7_LSB 7
131 #define DMA_ENABLE_EN8_BITS 8:8
132 #define DMA_ENABLE_EN8_SET 0x00000100
133 #define DMA_ENABLE_EN8_CLR 0xfffffeff
134 #define DMA_ENABLE_EN8_MSB 8
135 #define DMA_ENABLE_EN8_LSB 8
136 #define DMA_ENABLE_EN9_BITS 9:9
137 #define DMA_ENABLE_EN9_SET 0x00000200
138 #define DMA_ENABLE_EN9_CLR 0xfffffdff
139 #define DMA_ENABLE_EN9_MSB 9
140 #define DMA_ENABLE_EN9_LSB 9
141 #define DMA_ENABLE_EN10_BITS 10:10
142 #define DMA_ENABLE_EN10_SET 0x00000400
143 #define DMA_ENABLE_EN10_CLR 0xfffffbff
144 #define DMA_ENABLE_EN10_MSB 10
145 #define DMA_ENABLE_EN10_LSB 10
146 #define DMA_ENABLE_EN11_BITS 11:11
147 #define DMA_ENABLE_EN11_SET 0x00000800
148 #define DMA_ENABLE_EN11_CLR 0xfffff7ff
149 #define DMA_ENABLE_EN11_MSB 11
150 #define DMA_ENABLE_EN11_LSB 11
151 #define DMA_ENABLE_EN12_BITS 12:12
152 #define DMA_ENABLE_EN12_SET 0x00001000
153 #define DMA_ENABLE_EN12_CLR 0xffffefff
154 #define DMA_ENABLE_EN12_MSB 12
155 #define DMA_ENABLE_EN12_LSB 12
156 #define DMA_ENABLE_EN13_BITS 13:13
157 #define DMA_ENABLE_EN13_SET 0x00002000
158 #define DMA_ENABLE_EN13_CLR 0xffffdfff
159 #define DMA_ENABLE_EN13_MSB 13
160 #define DMA_ENABLE_EN13_LSB 13
161 #define DMA_ENABLE_EN14_BITS 14:14
162 #define DMA_ENABLE_EN14_SET 0x00004000
163 #define DMA_ENABLE_EN14_CLR 0xffffbfff
164 #define DMA_ENABLE_EN14_MSB 14
165 #define DMA_ENABLE_EN14_LSB 14
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