Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / axi_performance0.h
1 // This file was generated by the create_regs script
2 #define APERF0_BASE 0x7e009800
3 #define APERF0_APB_ID 0x41584950
4 #define APERF0_GEN_CTRL HW_REGISTER_RW( 0x7e009800 )
5 #define APERF0_GEN_CTRL_MASK 0x00000003
6 #define APERF0_GEN_CTRL_WIDTH 2
7 #define APERF0_GEN_CTRL_RESET 0000000000
8 #define APERF0_GEN_CTRL_ENABLE_BITS 0:0
9 #define APERF0_GEN_CTRL_ENABLE_SET 0x00000001
10 #define APERF0_GEN_CTRL_ENABLE_CLR 0xfffffffe
11 #define APERF0_GEN_CTRL_ENABLE_MSB 0
12 #define APERF0_GEN_CTRL_ENABLE_LSB 0
13 #define APERF0_GEN_CTRL_ENABLE_RESET 0x0
14 #define APERF0_GEN_CTRL_RESET_BITS 1:1
15 #define APERF0_GEN_CTRL_RESET_SET 0x00000002
16 #define APERF0_GEN_CTRL_RESET_CLR 0xfffffffd
17 #define APERF0_GEN_CTRL_RESET_MSB 1
18 #define APERF0_GEN_CTRL_RESET_LSB 1
19 #define APERF0_GEN_CTRL_RESET_RESET 0x0
20 #define APERF0_BW0_CTRL HW_REGISTER_RW( 0x7e009840 )
21 #define APERF0_BW0_CTRL_MASK 0xf0001f1f
22 #define APERF0_BW0_CTRL_WIDTH 32
23 #define APERF0_BW0_CTRL_RESET 0000000000
24 #define APERF0_BW0_CTRL_BUS_BITS 4:0
25 #define APERF0_BW0_CTRL_BUS_SET 0x0000001f
26 #define APERF0_BW0_CTRL_BUS_CLR 0xffffffe0
27 #define APERF0_BW0_CTRL_BUS_MSB 4
28 #define APERF0_BW0_CTRL_BUS_LSB 0
29 #define APERF0_BW0_CTRL_BUS_RESET 0x0
30 #define APERF0_BW0_CTRL_ID_BITS 12:8
31 #define APERF0_BW0_CTRL_ID_SET 0x00001f00
32 #define APERF0_BW0_CTRL_ID_CLR 0xffffe0ff
33 #define APERF0_BW0_CTRL_ID_MSB 12
34 #define APERF0_BW0_CTRL_ID_LSB 8
35 #define APERF0_BW0_CTRL_ID_RESET 0x0
36 #define APERF0_BW0_CTRL_LATHALT_BITS 28:28
37 #define APERF0_BW0_CTRL_LATHALT_SET 0x10000000
38 #define APERF0_BW0_CTRL_LATHALT_CLR 0xefffffff
39 #define APERF0_BW0_CTRL_LATHALT_MSB 28
40 #define APERF0_BW0_CTRL_LATHALT_LSB 28
41 #define APERF0_BW0_CTRL_LATHALT_RESET 0x0
42 #define APERF0_BW0_CTRL_ID_EN_BITS 29:29
43 #define APERF0_BW0_CTRL_ID_EN_SET 0x20000000
44 #define APERF0_BW0_CTRL_ID_EN_CLR 0xdfffffff
45 #define APERF0_BW0_CTRL_ID_EN_MSB 29
46 #define APERF0_BW0_CTRL_ID_EN_LSB 29
47 #define APERF0_BW0_CTRL_ID_EN_RESET 0x0
48 #define APERF0_BW0_CTRL_EN_BITS 30:30
49 #define APERF0_BW0_CTRL_EN_SET 0x40000000
50 #define APERF0_BW0_CTRL_EN_CLR 0xbfffffff
51 #define APERF0_BW0_CTRL_EN_MSB 30
52 #define APERF0_BW0_CTRL_EN_LSB 30
53 #define APERF0_BW0_CTRL_EN_RESET 0x0
54 #define APERF0_BW0_CTRL_RESET_BITS 31:31
55 #define APERF0_BW0_CTRL_RESET_SET 0x80000000
56 #define APERF0_BW0_CTRL_RESET_CLR 0x7fffffff
57 #define APERF0_BW0_CTRL_RESET_MSB 31
58 #define APERF0_BW0_CTRL_RESET_LSB 31
59 #define APERF0_BW0_CTRL_RESET_RESET 0x0
60 #define APERF0_BW0_ATRANS HW_REGISTER_RO( 0x7e009844 )
61 #define APERF0_BW0_ATRANS_MASK 0xffffffff
62 #define APERF0_BW0_ATRANS_WIDTH 32
63 #define APERF0_BW0_ATRANS_RESET 0000000000
64 #define APERF0_BW0_ATWAIT HW_REGISTER_RO( 0x7e009848 )
65 #define APERF0_BW0_ATWAIT_MASK 0xffffffff
66 #define APERF0_BW0_ATWAIT_WIDTH 32
67 #define APERF0_BW0_ATWAIT_RESET 0000000000
68 #define APERF0_BW0_AMAX HW_REGISTER_RO( 0x7e00984c )
69 #define APERF0_BW0_AMAX_MASK 0x00ffffff
70 #define APERF0_BW0_AMAX_WIDTH 24
71 #define APERF0_BW0_AMAX_RESET 0000000000
72 #define APERF0_BW0_WTRANS HW_REGISTER_RO( 0x7e009850 )
73 #define APERF0_BW0_WTRANS_MASK 0xffffffff
74 #define APERF0_BW0_WTRANS_WIDTH 32
75 #define APERF0_BW0_WTRANS_RESET 0000000000
76 #define APERF0_BW0_WTWAIT HW_REGISTER_RO( 0x7e009854 )
77 #define APERF0_BW0_WTWAIT_MASK 0xffffffff
78 #define APERF0_BW0_WTWAIT_WIDTH 32
79 #define APERF0_BW0_WTWAIT_RESET 0000000000
80 #define APERF0_BW0_WMAX HW_REGISTER_RO( 0x7e009858 )
81 #define APERF0_BW0_WMAX_MASK 0x00ffffff
82 #define APERF0_BW0_WMAX_WIDTH 24
83 #define APERF0_BW0_WMAX_RESET 0000000000
84 #define APERF0_BW0_RTRANS HW_REGISTER_RO( 0x7e00985c )
85 #define APERF0_BW0_RTRANS_MASK 0xffffffff
86 #define APERF0_BW0_RTRANS_WIDTH 32
87 #define APERF0_BW0_RTRANS_RESET 0000000000
88 #define APERF0_BW0_RTWAIT HW_REGISTER_RO( 0x7e009860 )
89 #define APERF0_BW0_RTWAIT_MASK 0xffffffff
90 #define APERF0_BW0_RTWAIT_WIDTH 32
91 #define APERF0_BW0_RTWAIT_RESET 0000000000
92 #define APERF0_BW0_RMAX HW_REGISTER_RO( 0x7e009864 )
93 #define APERF0_BW0_RMAX_MASK 0x00ffffff
94 #define APERF0_BW0_RMAX_WIDTH 24
95 #define APERF0_BW0_RMAX_RESET 0000000000
96 #define APERF0_BW0_RPEND HW_REGISTER_RO( 0x7e009868 )
97 #define APERF0_BW0_RPEND_MASK 0x000000ff
98 #define APERF0_BW0_RPEND_WIDTH 8
99 #define APERF0_BW0_RPEND_RESET 0000000000
100 #define APERF0_BW1_CTRL HW_REGISTER_RW( 0x7e009880 )
101 #define APERF0_BW1_CTRL_MASK 0xf0001f1f
102 #define APERF0_BW1_CTRL_WIDTH 32
103 #define APERF0_BW1_CTRL_RESET 0000000000
104 #define APERF0_BW1_CTRL_BUS_BITS 4:0
105 #define APERF0_BW1_CTRL_BUS_SET 0x0000001f
106 #define APERF0_BW1_CTRL_BUS_CLR 0xffffffe0
107 #define APERF0_BW1_CTRL_BUS_MSB 4
108 #define APERF0_BW1_CTRL_BUS_LSB 0
109 #define APERF0_BW1_CTRL_BUS_RESET 0x0
110 #define APERF0_BW1_CTRL_ID_BITS 12:8
111 #define APERF0_BW1_CTRL_ID_SET 0x00001f00
112 #define APERF0_BW1_CTRL_ID_CLR 0xffffe0ff
113 #define APERF0_BW1_CTRL_ID_MSB 12
114 #define APERF0_BW1_CTRL_ID_LSB 8
115 #define APERF0_BW1_CTRL_ID_RESET 0x0
116 #define APERF0_BW1_CTRL_LATHALT_BITS 28:28
117 #define APERF0_BW1_CTRL_LATHALT_SET 0x10000000
118 #define APERF0_BW1_CTRL_LATHALT_CLR 0xefffffff
119 #define APERF0_BW1_CTRL_LATHALT_MSB 28
120 #define APERF0_BW1_CTRL_LATHALT_LSB 28
121 #define APERF0_BW1_CTRL_LATHALT_RESET 0x0
122 #define APERF0_BW1_CTRL_ID_EN_BITS 29:29
123 #define APERF0_BW1_CTRL_ID_EN_SET 0x20000000
124 #define APERF0_BW1_CTRL_ID_EN_CLR 0xdfffffff
125 #define APERF0_BW1_CTRL_ID_EN_MSB 29
126 #define APERF0_BW1_CTRL_ID_EN_LSB 29
127 #define APERF0_BW1_CTRL_ID_EN_RESET 0x0
128 #define APERF0_BW1_CTRL_EN_BITS 30:30
129 #define APERF0_BW1_CTRL_EN_SET 0x40000000
130 #define APERF0_BW1_CTRL_EN_CLR 0xbfffffff
131 #define APERF0_BW1_CTRL_EN_MSB 30
132 #define APERF0_BW1_CTRL_EN_LSB 30
133 #define APERF0_BW1_CTRL_EN_RESET 0x0
134 #define APERF0_BW1_CTRL_RESET_BITS 31:31
135 #define APERF0_BW1_CTRL_RESET_SET 0x80000000
136 #define APERF0_BW1_CTRL_RESET_CLR 0x7fffffff
137 #define APERF0_BW1_CTRL_RESET_MSB 31
138 #define APERF0_BW1_CTRL_RESET_LSB 31
139 #define APERF0_BW1_CTRL_RESET_RESET 0x0
140 #define APERF0_BW1_ATRANS HW_REGISTER_RO( 0x7e009884 )
141 #define APERF0_BW1_ATRANS_MASK 0xffffffff
142 #define APERF0_BW1_ATRANS_WIDTH 32
143 #define APERF0_BW1_ATRANS_RESET 0000000000
144 #define APERF0_BW1_ATWAIT HW_REGISTER_RO( 0x7e009888 )
145 #define APERF0_BW1_ATWAIT_MASK 0xffffffff
146 #define APERF0_BW1_ATWAIT_WIDTH 32
147 #define APERF0_BW1_ATWAIT_RESET 0000000000
148 #define APERF0_BW1_AMAX HW_REGISTER_RO( 0x7e00988c )
149 #define APERF0_BW1_AMAX_MASK 0x00ffffff
150 #define APERF0_BW1_AMAX_WIDTH 24
151 #define APERF0_BW1_AMAX_RESET 0000000000
152 #define APERF0_BW1_WTRANS HW_REGISTER_RO( 0x7e009890 )
153 #define APERF0_BW1_WTRANS_MASK 0xffffffff
154 #define APERF0_BW1_WTRANS_WIDTH 32
155 #define APERF0_BW1_WTRANS_RESET 0000000000
156 #define APERF0_BW1_WTWAIT HW_REGISTER_RO( 0x7e009894 )
157 #define APERF0_BW1_WTWAIT_MASK 0xffffffff
158 #define APERF0_BW1_WTWAIT_WIDTH 32
159 #define APERF0_BW1_WTWAIT_RESET 0000000000
160 #define APERF0_BW1_WMAX HW_REGISTER_RO( 0x7e009898 )
161 #define APERF0_BW1_WMAX_MASK 0x0000ffff
162 #define APERF0_BW1_WMAX_WIDTH 16
163 #define APERF0_BW1_WMAX_RESET 0000000000
164 #define APERF0_BW1_RTRANS HW_REGISTER_RO( 0x7e00989c )
165 #define APERF0_BW1_RTRANS_MASK 0xffffffff
166 #define APERF0_BW1_RTRANS_WIDTH 32
167 #define APERF0_BW1_RTRANS_RESET 0000000000
168 #define APERF0_BW1_RTWAIT HW_REGISTER_RO( 0x7e0098a0 )
169 #define APERF0_BW1_RTWAIT_MASK 0xffffffff
170 #define APERF0_BW1_RTWAIT_WIDTH 32
171 #define APERF0_BW1_RTWAIT_RESET 0000000000
172 #define APERF0_BW1_RMAX HW_REGISTER_RO( 0x7e0098a4 )
173 #define APERF0_BW1_RMAX_MASK 0x00ffffff
174 #define APERF0_BW1_RMAX_WIDTH 24
175 #define APERF0_BW1_RMAX_RESET 0000000000
176 #define APERF0_BW1_RPEND HW_REGISTER_RO( 0x7e009868 )
177 #define APERF0_BW1_RPEND_MASK 0x000000ff
178 #define APERF0_BW1_RPEND_WIDTH 8
179 #define APERF0_BW1_RPEND_RESET 0000000000
180 #define APERF0_BW2_CTRL HW_REGISTER_RW( 0x7e0098c0 )
181 #define APERF0_BW2_CTRL_MASK 0xf0001f1f
182 #define APERF0_BW2_CTRL_WIDTH 32
183 #define APERF0_BW2_CTRL_RESET 0000000000
184 #define APERF0_BW2_CTRL_BUS_BITS 4:0
185 #define APERF0_BW2_CTRL_BUS_SET 0x0000001f
186 #define APERF0_BW2_CTRL_BUS_CLR 0xffffffe0
187 #define APERF0_BW2_CTRL_BUS_MSB 4
188 #define APERF0_BW2_CTRL_BUS_LSB 0
189 #define APERF0_BW2_CTRL_BUS_RESET 0x0
190 #define APERF0_BW2_CTRL_ID_BITS 12:8
191 #define APERF0_BW2_CTRL_ID_SET 0x00001f00
192 #define APERF0_BW2_CTRL_ID_CLR 0xffffe0ff
193 #define APERF0_BW2_CTRL_ID_MSB 12
194 #define APERF0_BW2_CTRL_ID_LSB 8
195 #define APERF0_BW2_CTRL_ID_RESET 0x0
196 #define APERF0_BW2_CTRL_LATHALT_BITS 28:28
197 #define APERF0_BW2_CTRL_LATHALT_SET 0x10000000
198 #define APERF0_BW2_CTRL_LATHALT_CLR 0xefffffff
199 #define APERF0_BW2_CTRL_LATHALT_MSB 28
200 #define APERF0_BW2_CTRL_LATHALT_LSB 28
201 #define APERF0_BW2_CTRL_LATHALT_RESET 0x0
202 #define APERF0_BW2_CTRL_ID_EN_BITS 29:29
203 #define APERF0_BW2_CTRL_ID_EN_SET 0x20000000
204 #define APERF0_BW2_CTRL_ID_EN_CLR 0xdfffffff
205 #define APERF0_BW2_CTRL_ID_EN_MSB 29
206 #define APERF0_BW2_CTRL_ID_EN_LSB 29
207 #define APERF0_BW2_CTRL_ID_EN_RESET 0x0
208 #define APERF0_BW2_CTRL_EN_BITS 30:30
209 #define APERF0_BW2_CTRL_EN_SET 0x40000000
210 #define APERF0_BW2_CTRL_EN_CLR 0xbfffffff
211 #define APERF0_BW2_CTRL_EN_MSB 30
212 #define APERF0_BW2_CTRL_EN_LSB 30
213 #define APERF0_BW2_CTRL_EN_RESET 0x0
214 #define APERF0_BW2_CTRL_RESET_BITS 31:31
215 #define APERF0_BW2_CTRL_RESET_SET 0x80000000
216 #define APERF0_BW2_CTRL_RESET_CLR 0x7fffffff
217 #define APERF0_BW2_CTRL_RESET_MSB 31
218 #define APERF0_BW2_CTRL_RESET_LSB 31
219 #define APERF0_BW2_CTRL_RESET_RESET 0x0
220 #define APERF0_BW2_ATRANS HW_REGISTER_RO( 0x7e0098c4 )
221 #define APERF0_BW2_ATRANS_MASK 0xffffffff
222 #define APERF0_BW2_ATRANS_WIDTH 32
223 #define APERF0_BW2_ATRANS_RESET 0000000000
224 #define APERF0_BW2_ATWAIT HW_REGISTER_RO( 0x7e0098c8 )
225 #define APERF0_BW2_ATWAIT_MASK 0xffffffff
226 #define APERF0_BW2_ATWAIT_WIDTH 32
227 #define APERF0_BW2_ATWAIT_RESET 0000000000
228 #define APERF0_BW2_AMAX HW_REGISTER_RO( 0x7e0098cc )
229 #define APERF0_BW2_AMAX_MASK 0x00ffffff
230 #define APERF0_BW2_AMAX_WIDTH 24
231 #define APERF0_BW2_AMAX_RESET 0000000000
232 #define APERF0_BW2_WTRANS HW_REGISTER_RO( 0x7e0098d0 )
233 #define APERF0_BW2_WTRANS_MASK 0xffffffff
234 #define APERF0_BW2_WTRANS_WIDTH 32
235 #define APERF0_BW2_WTRANS_RESET 0000000000
236 #define APERF0_BW2_WTWAIT HW_REGISTER_RO( 0x7e0098d4 )
237 #define APERF0_BW2_WTWAIT_MASK 0xffffffff
238 #define APERF0_BW2_WTWAIT_WIDTH 32
239 #define APERF0_BW2_WTWAIT_RESET 0000000000
240 #define APERF0_BW2_WMAX HW_REGISTER_RO( 0x7e0098d8 )
241 #define APERF0_BW2_WMAX_MASK 0x0ff0ffff
242 #define APERF0_BW2_WMAX_WIDTH 28
243 #define APERF0_BW2_WMAX_RESET 0000000000
244 #define APERF0_BW2_RTRANS HW_REGISTER_RO( 0x7e0098dc )
245 #define APERF0_BW2_RTRANS_MASK 0xffffffff
246 #define APERF0_BW2_RTRANS_WIDTH 32
247 #define APERF0_BW2_RTRANS_RESET 0000000000
248 #define APERF0_BW2_RTWAIT HW_REGISTER_RO( 0x7e0098e0 )
249 #define APERF0_BW2_RTWAIT_MASK 0xffffffff
250 #define APERF0_BW2_RTWAIT_WIDTH 32
251 #define APERF0_BW2_RTWAIT_RESET 0000000000
252 #define APERF0_BW2_RMAX HW_REGISTER_RO( 0x7e0098e4 )
253 #define APERF0_BW2_RMAX_MASK 0x00ffffff
254 #define APERF0_BW2_RMAX_WIDTH 24
255 #define APERF0_BW2_RMAX_RESET 0000000000
256 #define APERF0_BW2_RPEND HW_REGISTER_RO( 0x7e009868 )
257 #define APERF0_BW2_RPEND_MASK 0x000000ff
258 #define APERF0_BW2_RPEND_WIDTH 8
259 #define APERF0_BW2_RPEND_RESET 0000000000
This page took 0.0947 seconds and 5 git commands to generate.