1236d8e3476483ff4434308ab73bf7a7ff84a8f3
[rpi-open-firmware.git] / bcm2708_chip / cam0.h
1 // This file was generated by the create_regs script
2 #define CAM0_BASE 0x7e800000
3 #define CAM0_APB_ID 0x7563616d
4 #define CAM0_CAMCTL HW_REGISTER_RW( 0x7e800000 )
5 #define CAM0_CAMCTL_MASK 0xffffffff
6 #define CAM0_CAMCTL_WIDTH 32
7 #define CAM0_CAMCTL_RESET 0000000000
8 #define CAM0_CAMSTA HW_REGISTER_RW( 0x7e800004 )
9 #define CAM0_CAMSTA_MASK 0xffffffff
10 #define CAM0_CAMSTA_WIDTH 32
11 #define CAM0_CAMSTA_RESET 0000000000
12 #define CAM0_CAMANA HW_REGISTER_RW( 0x7e800008 )
13 #define CAM0_CAMANA_MASK 0xffffffff
14 #define CAM0_CAMANA_WIDTH 32
15 #define CAM0_CAMANA_RESET 0x00000777
16 #define CAM0_CAMPRI HW_REGISTER_RW( 0x7e80000c )
17 #define CAM0_CAMPRI_MASK 0xffffffff
18 #define CAM0_CAMPRI_WIDTH 32
19 #define CAM0_CAMPRI_RESET 0000000000
20 #define CAM0_CAMCLK HW_REGISTER_RW( 0x7e800010 )
21 #define CAM0_CAMCLK_MASK 0xffffffff
22 #define CAM0_CAMCLK_WIDTH 32
23 #define CAM0_CAMCLK_RESET 0x00000002
24 #define CAM0_CAMCLT HW_REGISTER_RW( 0x7e800014 )
25 #define CAM0_CAMCLT_MASK 0xffffffff
26 #define CAM0_CAMCLT_WIDTH 32
27 #define CAM0_CAMCLT_RESET 0000000000
28 #define CAM0_CAMDAT0 HW_REGISTER_RW( 0x7e800018 )
29 #define CAM0_CAMDAT0_MASK 0xffffffff
30 #define CAM0_CAMDAT0_WIDTH 32
31 #define CAM0_CAMDAT0_RESET 0x00000002
32 #define CAM0_CAMDAT1 HW_REGISTER_RW( 0x7e80001c )
33 #define CAM0_CAMDAT1_MASK 0xffffffff
34 #define CAM0_CAMDAT1_WIDTH 32
35 #define CAM0_CAMDAT1_RESET 0x00000002
36 #define CAM0_CAMDAT2 HW_REGISTER_RW( 0x7e800020 )
37 #define CAM0_CAMDAT2_MASK 0xffffffff
38 #define CAM0_CAMDAT2_WIDTH 32
39 #define CAM0_CAMDAT2_RESET 0x00000002
40 #define CAM0_CAMDAT3 HW_REGISTER_RW( 0x7e800024 )
41 #define CAM0_CAMDAT3_MASK 0xffffffff
42 #define CAM0_CAMDAT3_WIDTH 32
43 #define CAM0_CAMDAT3_RESET 0x00000002
44 #define CAM0_CAMDLT HW_REGISTER_RW( 0x7e800028 )
45 #define CAM0_CAMDLT_MASK 0xffffffff
46 #define CAM0_CAMDLT_WIDTH 32
47 #define CAM0_CAMDLT_RESET 0000000000
48 #define CAM0_CAMCMP0 HW_REGISTER_RW( 0x7e80002c )
49 #define CAM0_CAMCMP0_MASK 0xffffffff
50 #define CAM0_CAMCMP0_WIDTH 32
51 #define CAM0_CAMCMP0_RESET 0000000000
52 #define CAM0_CAMCMP1 HW_REGISTER_RW( 0x7e800030 )
53 #define CAM0_CAMCMP1_MASK 0xffffffff
54 #define CAM0_CAMCMP1_WIDTH 32
55 #define CAM0_CAMCMP1_RESET 0000000000
56 #define CAM0_CAMCAP0 HW_REGISTER_RW( 0x7e800034 )
57 #define CAM0_CAMCAP0_MASK 0xffffffff
58 #define CAM0_CAMCAP0_WIDTH 32
59 #define CAM0_CAMCAP0_RESET 0000000000
60 #define CAM0_CAMCAP1 HW_REGISTER_RW( 0x7e800038 )
61 #define CAM0_CAMCAP1_MASK 0xffffffff
62 #define CAM0_CAMCAP1_WIDTH 32
63 #define CAM0_CAMCAP1_RESET 0000000000
64 #define CAM0_CAMDBG0 HW_REGISTER_RW( 0x7e8000f0 )
65 #define CAM0_CAMDBG0_MASK 0xffffffff
66 #define CAM0_CAMDBG0_WIDTH 32
67 #define CAM0_CAMDBG0_RESET 0000000000
68 #define CAM0_CAMDBG1 HW_REGISTER_RW( 0x7e8000f4 )
69 #define CAM0_CAMDBG1_MASK 0xffffffff
70 #define CAM0_CAMDBG1_WIDTH 32
71 #define CAM0_CAMDBG1_RESET 0000000000
72 #define CAM0_CAMDBG2 HW_REGISTER_RW( 0x7e8000f8 )
73 #define CAM0_CAMDBG2_MASK 0xffffffff
74 #define CAM0_CAMDBG2_WIDTH 32
75 #define CAM0_CAMDBG2_RESET 0000000000
76 #define CAM0_CAMDBG3 HW_REGISTER_RW( 0x7e8000fc )
77 #define CAM0_CAMDBG3_MASK 0xffffffff
78 #define CAM0_CAMDBG3_WIDTH 32
79 #define CAM0_CAMDBG3_RESET 0000000000
80 #define CAM0_CAMICTL HW_REGISTER_RW( 0x7e800100 )
81 #define CAM0_CAMICTL_MASK 0xffffffff
82 #define CAM0_CAMICTL_WIDTH 32
83 #define CAM0_CAMICTL_RESET 0000000000
84 #define CAM0_CAMISTA HW_REGISTER_RW( 0x7e800104 )
85 #define CAM0_CAMISTA_MASK 0xffffffff
86 #define CAM0_CAMISTA_WIDTH 32
87 #define CAM0_CAMISTA_RESET 0000000000
88 #define CAM0_CAMIDI0 HW_REGISTER_RW( 0x7e800108 )
89 #define CAM0_CAMIDI0_MASK 0xffffffff
90 #define CAM0_CAMIDI0_WIDTH 32
91 #define CAM0_CAMIDI0_RESET 0000000000
92 #define CAM0_CAMIPIPE HW_REGISTER_RW( 0x7e80010c )
93 #define CAM0_CAMIPIPE_MASK 0xffffffff
94 #define CAM0_CAMIPIPE_WIDTH 32
95 #define CAM0_CAMIPIPE_RESET 0000000000
96 #define CAM0_CAMIBSA0 HW_REGISTER_RW( 0x7e800110 )
97 #define CAM0_CAMIBSA0_MASK 0xffffffff
98 #define CAM0_CAMIBSA0_WIDTH 32
99 #define CAM0_CAMIBSA0_RESET 0000000000
100 #define CAM0_CAMIBEA0 HW_REGISTER_RW( 0x7e800114 )
101 #define CAM0_CAMIBEA0_MASK 0xffffffff
102 #define CAM0_CAMIBEA0_WIDTH 32
103 #define CAM0_CAMIBEA0_RESET 0000000000
104 #define CAM0_CAMIBLS HW_REGISTER_RW( 0x7e800118 )
105 #define CAM0_CAMIBLS_MASK 0xffffffff
106 #define CAM0_CAMIBLS_WIDTH 32
107 #define CAM0_CAMIBLS_RESET 0000000000
108 #define CAM0_CAMIBWP HW_REGISTER_RW( 0x7e80011c )
109 #define CAM0_CAMIBWP_MASK 0xffffffff
110 #define CAM0_CAMIBWP_WIDTH 32
111 #define CAM0_CAMIBWP_RESET 0000000000
112 #define CAM0_CAMIHWIN HW_REGISTER_RW( 0x7e800120 )
113 #define CAM0_CAMIHWIN_MASK 0xffffffff
114 #define CAM0_CAMIHWIN_WIDTH 32
115 #define CAM0_CAMIHWIN_RESET 0000000000
116 #define CAM0_CAMIHSTA HW_REGISTER_RW( 0x7e800124 )
117 #define CAM0_CAMIHSTA_MASK 0xffffffff
118 #define CAM0_CAMIHSTA_WIDTH 32
119 #define CAM0_CAMIHSTA_RESET 0000000000
120 #define CAM0_CAMIVWIN HW_REGISTER_RW( 0x7e800128 )
121 #define CAM0_CAMIVWIN_MASK 0xffffffff
122 #define CAM0_CAMIVWIN_WIDTH 32
123 #define CAM0_CAMIVWIN_RESET 0000000000
124 #define CAM0_CAMIVSTA HW_REGISTER_RW( 0x7e80012c )
125 #define CAM0_CAMIVSTA_MASK 0xffffffff
126 #define CAM0_CAMIVSTA_WIDTH 32
127 #define CAM0_CAMIVSTA_RESET 0000000000
128 #define CAM0_CAMICC HW_REGISTER_RW( 0x7e800130 )
129 #define CAM0_CAMICC_MASK 0xffffffff
130 #define CAM0_CAMICC_WIDTH 32
131 #define CAM0_CAMICC_RESET 0000000000
132 #define CAM0_CAMICS HW_REGISTER_RW( 0x7e800134 )
133 #define CAM0_CAMICS_MASK 0xffffffff
134 #define CAM0_CAMICS_WIDTH 32
135 #define CAM0_CAMICS_RESET 0000000000
136 #define CAM0_CAMIDC HW_REGISTER_RW( 0x7e800138 )
137 #define CAM0_CAMIDC_MASK 0xffffffff
138 #define CAM0_CAMIDC_WIDTH 32
139 #define CAM0_CAMIDC_RESET 0000000000
140 #define CAM0_CAMIDPO HW_REGISTER_RW( 0x7e80013c )
141 #define CAM0_CAMIDPO_MASK 0xffffffff
142 #define CAM0_CAMIDPO_WIDTH 32
143 #define CAM0_CAMIDPO_RESET 0000000000
144 #define CAM0_CAMIDCA HW_REGISTER_RW( 0x7e800140 )
145 #define CAM0_CAMIDCA_MASK 0xffffffff
146 #define CAM0_CAMIDCA_WIDTH 32
147 #define CAM0_CAMIDCA_RESET 0000000000
148 #define CAM0_CAMIDCD HW_REGISTER_RW( 0x7e800144 )
149 #define CAM0_CAMIDCD_MASK 0xffffffff
150 #define CAM0_CAMIDCD_WIDTH 32
151 #define CAM0_CAMIDCD_RESET 0000000000
152 #define CAM0_CAMIDS HW_REGISTER_RW( 0x7e800148 )
153 #define CAM0_CAMIDS_MASK 0xffffffff
154 #define CAM0_CAMIDS_WIDTH 32
155 #define CAM0_CAMIDS_RESET 0000000000
156 #define CAM0_CAMDCS HW_REGISTER_RW( 0x7e800200 )
157 #define CAM0_CAMDCS_MASK 0xffffffff
158 #define CAM0_CAMDCS_WIDTH 32
159 #define CAM0_CAMDCS_RESET 0000000000
160 #define CAM0_CAMDBSA0 HW_REGISTER_RW( 0x7e800204 )
161 #define CAM0_CAMDBSA0_MASK 0xffffffff
162 #define CAM0_CAMDBSA0_WIDTH 32
163 #define CAM0_CAMDBSA0_RESET 0000000000
164 #define CAM0_CAMDBEA0 HW_REGISTER_RW( 0x7e800208 )
165 #define CAM0_CAMDBEA0_MASK 0xffffffff
166 #define CAM0_CAMDBEA0_WIDTH 32
167 #define CAM0_CAMDBEA0_RESET 0000000000
168 #define CAM0_CAMDBWP HW_REGISTER_RW( 0x7e80020c )
169 #define CAM0_CAMDBWP_MASK 0xffffffff
170 #define CAM0_CAMDBWP_WIDTH 32
171 #define CAM0_CAMDBWP_RESET 0000000000
172 #define CAM0_CAMDBCTL HW_REGISTER_RW( 0x7e800300 )
173 #define CAM0_CAMDBCTL_MASK 0xffffffff
174 #define CAM0_CAMDBCTL_WIDTH 32
175 #define CAM0_CAMDBCTL_RESET 0000000000
176 #define CAM0_CAMIBSA1 HW_REGISTER_RW( 0x7e800304 )
177 #define CAM0_CAMIBSA1_MASK 0xffffffff
178 #define CAM0_CAMIBSA1_WIDTH 32
179 #define CAM0_CAMIBSA1_RESET 0000000000
180 #define CAM0_CAMIBEA1 HW_REGISTER_RW( 0x7e800308 )
181 #define CAM0_CAMIBEA1_MASK 0xffffffff
182 #define CAM0_CAMIBEA1_WIDTH 32
183 #define CAM0_CAMIBEA1_RESET 0000000000
184 #define CAM0_CAMIDI1 HW_REGISTER_RW( 0x7e80030c )
185 #define CAM0_CAMIDI1_MASK 0xffffffff
186 #define CAM0_CAMIDI1_WIDTH 32
187 #define CAM0_CAMIDI1_RESET 0000000000
188 #define CAM0_CAMDBSA1 HW_REGISTER_RW( 0x7e800310 )
189 #define CAM0_CAMDBSA1_MASK 0xffffffff
190 #define CAM0_CAMDBSA1_WIDTH 32
191 #define CAM0_CAMDBSA1_RESET 0000000000
192 #define CAM0_CAMDBEA1 HW_REGISTER_RW( 0x7e800314 )
193 #define CAM0_CAMDBEA1_MASK 0xffffffff
194 #define CAM0_CAMDBEA1_WIDTH 32
195 #define CAM0_CAMDBEA1_RESET 0000000000
196 #define CAM0_CAMMISC HW_REGISTER_RW( 0x7e800400 )
197 #define CAM0_CAMMISC_MASK 0xffffffff
198 #define CAM0_CAMMISC_WIDTH 32
199 #define CAM0_CAMMISC_RESET 0000000000
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