Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / cam0_a0.h
1 // This file was generated by the create_regs script
2 #define CAM0_BASE 0x7e800000
3 #define CAM0_APB_ID 0x7563616d
4 #define CAM0_CTL HW_REGISTER_RW( 0x7e800000 )
5 #define CAM0_CTL_MASK 0xffffffff
6 #define CAM0_CTL_WIDTH 32
7 #define CAM0_CTL_RESET 0000000000
8 #define CAM0_STA HW_REGISTER_RW( 0x7e800004 )
9 #define CAM0_STA_MASK 0xffffffff
10 #define CAM0_STA_WIDTH 32
11 #define CAM0_STA_RESET 0000000000
12 #define CAM0_ANA HW_REGISTER_RW( 0x7e800008 )
13 #define CAM0_ANA_MASK 0xffffffff
14 #define CAM0_ANA_WIDTH 32
15 #define CAM0_ANA_RESET 0000000000
16 #define CAM0_PRI HW_REGISTER_RW( 0x7e80000c )
17 #define CAM0_PRI_MASK 0xffffffff
18 #define CAM0_PRI_WIDTH 32
19 #define CAM0_PRI_RESET 0000000000
20 #define CAM0_CLK HW_REGISTER_RW( 0x7e800010 )
21 #define CAM0_CLK_MASK 0xffffffff
22 #define CAM0_CLK_WIDTH 32
23 #define CAM0_CLK_RESET 0000000000
24 #define CAM0_DAT0 HW_REGISTER_RW( 0x7e800014 )
25 #define CAM0_DAT0_MASK 0xffffffff
26 #define CAM0_DAT0_WIDTH 32
27 #define CAM0_DAT0_RESET 0000000000
28 #define CAM0_DAT1 HW_REGISTER_RW( 0x7e800018 )
29 #define CAM0_DAT1_MASK 0xffffffff
30 #define CAM0_DAT1_WIDTH 32
31 #define CAM0_DAT1_RESET 0000000000
32 #define CAM0_DAT2 HW_REGISTER_RW( 0x7e80001c )
33 #define CAM0_DAT2_MASK 0xffffffff
34 #define CAM0_DAT2_WIDTH 32
35 #define CAM0_DAT2_RESET 0000000000
36 #define CAM0_DAT3 HW_REGISTER_RW( 0x7e800020 )
37 #define CAM0_DAT3_MASK 0xffffffff
38 #define CAM0_DAT3_WIDTH 32
39 #define CAM0_DAT3_RESET 0000000000
40 #define CAM0_CMP0 HW_REGISTER_RW( 0x7e800024 )
41 #define CAM0_CMP0_MASK 0xffffffff
42 #define CAM0_CMP0_WIDTH 32
43 #define CAM0_CMP0_RESET 0000000000
44 #define CAM0_CMP1 HW_REGISTER_RW( 0x7e800028 )
45 #define CAM0_CMP1_MASK 0xffffffff
46 #define CAM0_CMP1_WIDTH 32
47 #define CAM0_CMP1_RESET 0000000000
48 #define CAM0_CAP0 HW_REGISTER_RW( 0x7e80002c )
49 #define CAM0_CAP0_MASK 0xffffffff
50 #define CAM0_CAP0_WIDTH 32
51 #define CAM0_CAP0_RESET 0000000000
52 #define CAM0_CAP1 HW_REGISTER_RW( 0x7e800030 )
53 #define CAM0_CAP1_MASK 0xffffffff
54 #define CAM0_CAP1_WIDTH 32
55 #define CAM0_CAP1_RESET 0000000000
56 #define CAM0_DBG0 HW_REGISTER_RW( 0x7e8000f0 )
57 #define CAM0_DBG0_MASK 0xffffffff
58 #define CAM0_DBG0_WIDTH 32
59 #define CAM0_DBG0_RESET 0000000000
60 #define CAM0_DBG1 HW_REGISTER_RW( 0x7e8000f4 )
61 #define CAM0_DBG1_MASK 0xffffffff
62 #define CAM0_DBG1_WIDTH 32
63 #define CAM0_DBG1_RESET 0000000000
64 #define CAM0_DBG2 HW_REGISTER_RW( 0x7e8000f8 )
65 #define CAM0_DBG2_MASK 0xffffffff
66 #define CAM0_DBG2_WIDTH 32
67 #define CAM0_DBG2_RESET 0000000000
68 #define CAM0_ICTL HW_REGISTER_RW( 0x7e800100 )
69 #define CAM0_ICTL_MASK 0xffffffff
70 #define CAM0_ICTL_WIDTH 32
71 #define CAM0_ICTL_RESET 0000000000
72 #define CAM0_ISTA HW_REGISTER_RW( 0x7e800104 )
73 #define CAM0_ISTA_MASK 0xffffffff
74 #define CAM0_ISTA_WIDTH 32
75 #define CAM0_ISTA_RESET 0000000000
76 #define CAM0_IDI HW_REGISTER_RW( 0x7e800108 )
77 #define CAM0_IDI_MASK 0xffffffff
78 #define CAM0_IDI_WIDTH 32
79 #define CAM0_IDI_RESET 0000000000
80 #define CAM0_IPIPE HW_REGISTER_RW( 0x7e80010c )
81 #define CAM0_IPIPE_MASK 0xffffffff
82 #define CAM0_IPIPE_WIDTH 32
83 #define CAM0_IPIPE_RESET 0000000000
84 #define CAM0_IBSA HW_REGISTER_RW( 0x7e800110 )
85 #define CAM0_IBSA_MASK 0xffffffff
86 #define CAM0_IBSA_WIDTH 32
87 #define CAM0_IBSA_RESET 0000000000
88 #define CAM0_IBEA HW_REGISTER_RW( 0x7e800114 )
89 #define CAM0_IBEA_MASK 0xffffffff
90 #define CAM0_IBEA_WIDTH 32
91 #define CAM0_IBEA_RESET 0000000000
92 #define CAM0_IBLS HW_REGISTER_RW( 0x7e800118 )
93 #define CAM0_IBLS_MASK 0xffffffff
94 #define CAM0_IBLS_WIDTH 32
95 #define CAM0_IBLS_RESET 0000000000
96 #define CAM0_IBWP HW_REGISTER_RW( 0x7e80011c )
97 #define CAM0_IBWP_MASK 0xffffffff
98 #define CAM0_IBWP_WIDTH 32
99 #define CAM0_IBWP_RESET 0000000000
100 #define CAM0_IHWIN HW_REGISTER_RW( 0x7e800120 )
101 #define CAM0_IHWIN_MASK 0xffffffff
102 #define CAM0_IHWIN_WIDTH 32
103 #define CAM0_IHWIN_RESET 0000000000
104 #define CAM0_IHSTA HW_REGISTER_RW( 0x7e800124 )
105 #define CAM0_IHSTA_MASK 0xffffffff
106 #define CAM0_IHSTA_WIDTH 32
107 #define CAM0_IHSTA_RESET 0000000000
108 #define CAM0_IVWIN HW_REGISTER_RW( 0x7e800128 )
109 #define CAM0_IVWIN_MASK 0xffffffff
110 #define CAM0_IVWIN_WIDTH 32
111 #define CAM0_IVWIN_RESET 0000000000
112 #define CAM0_IVSTA HW_REGISTER_RW( 0x7e80012c )
113 #define CAM0_IVSTA_MASK 0xffffffff
114 #define CAM0_IVSTA_WIDTH 32
115 #define CAM0_IVSTA_RESET 0000000000
116 #define CAM0_DCS HW_REGISTER_RW( 0x7e800200 )
117 #define CAM0_DCS_MASK 0xffffffff
118 #define CAM0_DCS_WIDTH 32
119 #define CAM0_DCS_RESET 0000000000
120 #define CAM0_DBSA HW_REGISTER_RW( 0x7e800204 )
121 #define CAM0_DBSA_MASK 0xffffffff
122 #define CAM0_DBSA_WIDTH 32
123 #define CAM0_DBSA_RESET 0000000000
124 #define CAM0_DBEA HW_REGISTER_RW( 0x7e800208 )
125 #define CAM0_DBEA_MASK 0xffffffff
126 #define CAM0_DBEA_WIDTH 32
127 #define CAM0_DBEA_RESET 0000000000
128 #define CAM0_DBWP HW_REGISTER_RW( 0x7e800208 )
129 #define CAM0_DBWP_MASK 0xffffffff
130 #define CAM0_DBWP_WIDTH 32
131 #define CAM0_DBWP_RESET 0000000000
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