Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / cam1.h
1 // This file was generated by the create_regs script
2 #define CAM1_BASE 0x7e801000
3 #define CAM1_APB_ID 0x7563616d
4 #define CAM1_CAMCTL HW_REGISTER_RW( 0x7e801000 )
5 #define CAM1_CAMCTL_MASK 0xffffffff
6 #define CAM1_CAMCTL_WIDTH 32
7 #define CAM1_CAMCTL_RESET 0000000000
8 #define CAM1_CAMSTA HW_REGISTER_RW( 0x7e801004 )
9 #define CAM1_CAMSTA_MASK 0xffffffff
10 #define CAM1_CAMSTA_WIDTH 32
11 #define CAM1_CAMSTA_RESET 0000000000
12 #define CAM1_CAMANA HW_REGISTER_RW( 0x7e801008 )
13 #define CAM1_CAMANA_MASK 0xffffffff
14 #define CAM1_CAMANA_WIDTH 32
15 #define CAM1_CAMANA_RESET 0x00000777
16 #define CAM1_CAMPRI HW_REGISTER_RW( 0x7e80100c )
17 #define CAM1_CAMPRI_MASK 0xffffffff
18 #define CAM1_CAMPRI_WIDTH 32
19 #define CAM1_CAMPRI_RESET 0000000000
20 #define CAM1_CAMCLK HW_REGISTER_RW( 0x7e801010 )
21 #define CAM1_CAMCLK_MASK 0xffffffff
22 #define CAM1_CAMCLK_WIDTH 32
23 #define CAM1_CAMCLK_RESET 0x00000002
24 #define CAM1_CAMCLT HW_REGISTER_RW( 0x7e801014 )
25 #define CAM1_CAMCLT_MASK 0xffffffff
26 #define CAM1_CAMCLT_WIDTH 32
27 #define CAM1_CAMCLT_RESET 0000000000
28 #define CAM1_CAMDAT0 HW_REGISTER_RW( 0x7e801018 )
29 #define CAM1_CAMDAT0_MASK 0xffffffff
30 #define CAM1_CAMDAT0_WIDTH 32
31 #define CAM1_CAMDAT0_RESET 0x00000002
32 #define CAM1_CAMDAT1 HW_REGISTER_RW( 0x7e80101c )
33 #define CAM1_CAMDAT1_MASK 0xffffffff
34 #define CAM1_CAMDAT1_WIDTH 32
35 #define CAM1_CAMDAT1_RESET 0x00000002
36 #define CAM1_CAMDAT2 HW_REGISTER_RW( 0x7e801020 )
37 #define CAM1_CAMDAT2_MASK 0xffffffff
38 #define CAM1_CAMDAT2_WIDTH 32
39 #define CAM1_CAMDAT2_RESET 0x00000002
40 #define CAM1_CAMDAT3 HW_REGISTER_RW( 0x7e801024 )
41 #define CAM1_CAMDAT3_MASK 0xffffffff
42 #define CAM1_CAMDAT3_WIDTH 32
43 #define CAM1_CAMDAT3_RESET 0x00000002
44 #define CAM1_CAMDLT HW_REGISTER_RW( 0x7e801028 )
45 #define CAM1_CAMDLT_MASK 0xffffffff
46 #define CAM1_CAMDLT_WIDTH 32
47 #define CAM1_CAMDLT_RESET 0000000000
48 #define CAM1_CAMCMP0 HW_REGISTER_RW( 0x7e80102c )
49 #define CAM1_CAMCMP0_MASK 0xffffffff
50 #define CAM1_CAMCMP0_WIDTH 32
51 #define CAM1_CAMCMP0_RESET 0000000000
52 #define CAM1_CAMCMP1 HW_REGISTER_RW( 0x7e801030 )
53 #define CAM1_CAMCMP1_MASK 0xffffffff
54 #define CAM1_CAMCMP1_WIDTH 32
55 #define CAM1_CAMCMP1_RESET 0000000000
56 #define CAM1_CAMCAP0 HW_REGISTER_RW( 0x7e801034 )
57 #define CAM1_CAMCAP0_MASK 0xffffffff
58 #define CAM1_CAMCAP0_WIDTH 32
59 #define CAM1_CAMCAP0_RESET 0000000000
60 #define CAM1_CAMCAP1 HW_REGISTER_RW( 0x7e801038 )
61 #define CAM1_CAMCAP1_MASK 0xffffffff
62 #define CAM1_CAMCAP1_WIDTH 32
63 #define CAM1_CAMCAP1_RESET 0000000000
64 #define CAM1_CAMDBG0 HW_REGISTER_RW( 0x7e8010f0 )
65 #define CAM1_CAMDBG0_MASK 0xffffffff
66 #define CAM1_CAMDBG0_WIDTH 32
67 #define CAM1_CAMDBG0_RESET 0000000000
68 #define CAM1_CAMDBG1 HW_REGISTER_RW( 0x7e8010f4 )
69 #define CAM1_CAMDBG1_MASK 0xffffffff
70 #define CAM1_CAMDBG1_WIDTH 32
71 #define CAM1_CAMDBG1_RESET 0000000000
72 #define CAM1_CAMDBG2 HW_REGISTER_RW( 0x7e8010f8 )
73 #define CAM1_CAMDBG2_MASK 0xffffffff
74 #define CAM1_CAMDBG2_WIDTH 32
75 #define CAM1_CAMDBG2_RESET 0000000000
76 #define CAM1_CAMDBG3 HW_REGISTER_RW( 0x7e8010fc )
77 #define CAM1_CAMDBG3_MASK 0xffffffff
78 #define CAM1_CAMDBG3_WIDTH 32
79 #define CAM1_CAMDBG3_RESET 0000000000
80 #define CAM1_CAMICTL HW_REGISTER_RW( 0x7e801100 )
81 #define CAM1_CAMICTL_MASK 0xffffffff
82 #define CAM1_CAMICTL_WIDTH 32
83 #define CAM1_CAMICTL_RESET 0000000000
84 #define CAM1_CAMISTA HW_REGISTER_RW( 0x7e801104 )
85 #define CAM1_CAMISTA_MASK 0xffffffff
86 #define CAM1_CAMISTA_WIDTH 32
87 #define CAM1_CAMISTA_RESET 0000000000
88 #define CAM1_CAMIDI0 HW_REGISTER_RW( 0x7e801108 )
89 #define CAM1_CAMIDI0_MASK 0xffffffff
90 #define CAM1_CAMIDI0_WIDTH 32
91 #define CAM1_CAMIDI0_RESET 0000000000
92 #define CAM1_CAMIPIPE HW_REGISTER_RW( 0x7e80110c )
93 #define CAM1_CAMIPIPE_MASK 0xffffffff
94 #define CAM1_CAMIPIPE_WIDTH 32
95 #define CAM1_CAMIPIPE_RESET 0000000000
96 #define CAM1_CAMIBSA0 HW_REGISTER_RW( 0x7e801110 )
97 #define CAM1_CAMIBSA0_MASK 0xffffffff
98 #define CAM1_CAMIBSA0_WIDTH 32
99 #define CAM1_CAMIBSA0_RESET 0000000000
100 #define CAM1_CAMIBEA0 HW_REGISTER_RW( 0x7e801114 )
101 #define CAM1_CAMIBEA0_MASK 0xffffffff
102 #define CAM1_CAMIBEA0_WIDTH 32
103 #define CAM1_CAMIBEA0_RESET 0000000000
104 #define CAM1_CAMIBLS HW_REGISTER_RW( 0x7e801118 )
105 #define CAM1_CAMIBLS_MASK 0xffffffff
106 #define CAM1_CAMIBLS_WIDTH 32
107 #define CAM1_CAMIBLS_RESET 0000000000
108 #define CAM1_CAMIBWP HW_REGISTER_RW( 0x7e80111c )
109 #define CAM1_CAMIBWP_MASK 0xffffffff
110 #define CAM1_CAMIBWP_WIDTH 32
111 #define CAM1_CAMIBWP_RESET 0000000000
112 #define CAM1_CAMIHWIN HW_REGISTER_RW( 0x7e801120 )
113 #define CAM1_CAMIHWIN_MASK 0xffffffff
114 #define CAM1_CAMIHWIN_WIDTH 32
115 #define CAM1_CAMIHWIN_RESET 0000000000
116 #define CAM1_CAMIHSTA HW_REGISTER_RW( 0x7e801124 )
117 #define CAM1_CAMIHSTA_MASK 0xffffffff
118 #define CAM1_CAMIHSTA_WIDTH 32
119 #define CAM1_CAMIHSTA_RESET 0000000000
120 #define CAM1_CAMIVWIN HW_REGISTER_RW( 0x7e801128 )
121 #define CAM1_CAMIVWIN_MASK 0xffffffff
122 #define CAM1_CAMIVWIN_WIDTH 32
123 #define CAM1_CAMIVWIN_RESET 0000000000
124 #define CAM1_CAMIVSTA HW_REGISTER_RW( 0x7e80112c )
125 #define CAM1_CAMIVSTA_MASK 0xffffffff
126 #define CAM1_CAMIVSTA_WIDTH 32
127 #define CAM1_CAMIVSTA_RESET 0000000000
128 #define CAM1_CAMICC HW_REGISTER_RW( 0x7e801130 )
129 #define CAM1_CAMICC_MASK 0xffffffff
130 #define CAM1_CAMICC_WIDTH 32
131 #define CAM1_CAMICC_RESET 0000000000
132 #define CAM1_CAMICS HW_REGISTER_RW( 0x7e801134 )
133 #define CAM1_CAMICS_MASK 0xffffffff
134 #define CAM1_CAMICS_WIDTH 32
135 #define CAM1_CAMICS_RESET 0000000000
136 #define CAM1_CAMIDC HW_REGISTER_RW( 0x7e801138 )
137 #define CAM1_CAMIDC_MASK 0xffffffff
138 #define CAM1_CAMIDC_WIDTH 32
139 #define CAM1_CAMIDC_RESET 0000000000
140 #define CAM1_CAMIDPO HW_REGISTER_RW( 0x7e80113c )
141 #define CAM1_CAMIDPO_MASK 0xffffffff
142 #define CAM1_CAMIDPO_WIDTH 32
143 #define CAM1_CAMIDPO_RESET 0000000000
144 #define CAM1_CAMIDCA HW_REGISTER_RW( 0x7e801140 )
145 #define CAM1_CAMIDCA_MASK 0xffffffff
146 #define CAM1_CAMIDCA_WIDTH 32
147 #define CAM1_CAMIDCA_RESET 0000000000
148 #define CAM1_CAMIDCD HW_REGISTER_RW( 0x7e801144 )
149 #define CAM1_CAMIDCD_MASK 0xffffffff
150 #define CAM1_CAMIDCD_WIDTH 32
151 #define CAM1_CAMIDCD_RESET 0000000000
152 #define CAM1_CAMIDS HW_REGISTER_RW( 0x7e801148 )
153 #define CAM1_CAMIDS_MASK 0xffffffff
154 #define CAM1_CAMIDS_WIDTH 32
155 #define CAM1_CAMIDS_RESET 0000000000
156 #define CAM1_CAMDCS HW_REGISTER_RW( 0x7e801200 )
157 #define CAM1_CAMDCS_MASK 0xffffffff
158 #define CAM1_CAMDCS_WIDTH 32
159 #define CAM1_CAMDCS_RESET 0000000000
160 #define CAM1_CAMDBSA0 HW_REGISTER_RW( 0x7e801204 )
161 #define CAM1_CAMDBSA0_MASK 0xffffffff
162 #define CAM1_CAMDBSA0_WIDTH 32
163 #define CAM1_CAMDBSA0_RESET 0000000000
164 #define CAM1_CAMDBEA0 HW_REGISTER_RW( 0x7e801208 )
165 #define CAM1_CAMDBEA0_MASK 0xffffffff
166 #define CAM1_CAMDBEA0_WIDTH 32
167 #define CAM1_CAMDBEA0_RESET 0000000000
168 #define CAM1_CAMDBWP HW_REGISTER_RW( 0x7e80120c )
169 #define CAM1_CAMDBWP_MASK 0xffffffff
170 #define CAM1_CAMDBWP_WIDTH 32
171 #define CAM1_CAMDBWP_RESET 0000000000
172 #define CAM1_CAMDBCTL HW_REGISTER_RW( 0x7e801300 )
173 #define CAM1_CAMDBCTL_MASK 0xffffffff
174 #define CAM1_CAMDBCTL_WIDTH 32
175 #define CAM1_CAMDBCTL_RESET 0000000000
176 #define CAM1_CAMIBSA1 HW_REGISTER_RW( 0x7e801304 )
177 #define CAM1_CAMIBSA1_MASK 0xffffffff
178 #define CAM1_CAMIBSA1_WIDTH 32
179 #define CAM1_CAMIBSA1_RESET 0000000000
180 #define CAM1_CAMIBEA1 HW_REGISTER_RW( 0x7e801308 )
181 #define CAM1_CAMIBEA1_MASK 0xffffffff
182 #define CAM1_CAMIBEA1_WIDTH 32
183 #define CAM1_CAMIBEA1_RESET 0000000000
184 #define CAM1_CAMIDI1 HW_REGISTER_RW( 0x7e80130c )
185 #define CAM1_CAMIDI1_MASK 0xffffffff
186 #define CAM1_CAMIDI1_WIDTH 32
187 #define CAM1_CAMIDI1_RESET 0000000000
188 #define CAM1_CAMDBSA1 HW_REGISTER_RW( 0x7e801310 )
189 #define CAM1_CAMDBSA1_MASK 0xffffffff
190 #define CAM1_CAMDBSA1_WIDTH 32
191 #define CAM1_CAMDBSA1_RESET 0000000000
192 #define CAM1_CAMDBEA1 HW_REGISTER_RW( 0x7e801314 )
193 #define CAM1_CAMDBEA1_MASK 0xffffffff
194 #define CAM1_CAMDBEA1_WIDTH 32
195 #define CAM1_CAMDBEA1_RESET 0000000000
196 #define CAM1_CAMMISC HW_REGISTER_RW( 0x7e801400 )
197 #define CAM1_CAMMISC_MASK 0xffffffff
198 #define CAM1_CAMMISC_WIDTH 32
199 #define CAM1_CAMMISC_RESET 0000000000
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