Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / cam1_a0.h
1 // This file was generated by the create_regs script
2 #define CAM1_BASE 0x7e801000
3 #define CAM1_APB_ID 0x7563616d
4 #define CAM1_CTL HW_REGISTER_RW( 0x7e801000 )
5 #define CAM1_CTL_MASK 0xffffffff
6 #define CAM1_CTL_WIDTH 32
7 #define CAM1_CTL_RESET 0000000000
8 #define CAM1_STA HW_REGISTER_RW( 0x7e801004 )
9 #define CAM1_STA_MASK 0xffffffff
10 #define CAM1_STA_WIDTH 32
11 #define CAM1_STA_RESET 0000000000
12 #define CAM1_ANA HW_REGISTER_RW( 0x7e801008 )
13 #define CAM1_ANA_MASK 0xffffffff
14 #define CAM1_ANA_WIDTH 32
15 #define CAM1_ANA_RESET 0000000000
16 #define CAM1_PRI HW_REGISTER_RW( 0x7e80100c )
17 #define CAM1_PRI_MASK 0xffffffff
18 #define CAM1_PRI_WIDTH 32
19 #define CAM1_PRI_RESET 0000000000
20 #define CAM1_CLK HW_REGISTER_RW( 0x7e801010 )
21 #define CAM1_CLK_MASK 0xffffffff
22 #define CAM1_CLK_WIDTH 32
23 #define CAM1_CLK_RESET 0000000000
24 #define CAM1_DAT0 HW_REGISTER_RW( 0x7e801014 )
25 #define CAM1_DAT0_MASK 0xffffffff
26 #define CAM1_DAT0_WIDTH 32
27 #define CAM1_DAT0_RESET 0000000000
28 #define CAM1_DAT1 HW_REGISTER_RW( 0x7e801018 )
29 #define CAM1_DAT1_MASK 0xffffffff
30 #define CAM1_DAT1_WIDTH 32
31 #define CAM1_DAT1_RESET 0000000000
32 #define CAM1_DAT2 HW_REGISTER_RW( 0x7e80101c )
33 #define CAM1_DAT2_MASK 0xffffffff
34 #define CAM1_DAT2_WIDTH 32
35 #define CAM1_DAT2_RESET 0000000000
36 #define CAM1_DAT3 HW_REGISTER_RW( 0x7e801020 )
37 #define CAM1_DAT3_MASK 0xffffffff
38 #define CAM1_DAT3_WIDTH 32
39 #define CAM1_DAT3_RESET 0000000000
40 #define CAM1_CMP0 HW_REGISTER_RW( 0x7e801024 )
41 #define CAM1_CMP0_MASK 0xffffffff
42 #define CAM1_CMP0_WIDTH 32
43 #define CAM1_CMP0_RESET 0000000000
44 #define CAM1_CMP1 HW_REGISTER_RW( 0x7e801028 )
45 #define CAM1_CMP1_MASK 0xffffffff
46 #define CAM1_CMP1_WIDTH 32
47 #define CAM1_CMP1_RESET 0000000000
48 #define CAM1_CAP0 HW_REGISTER_RW( 0x7e80102c )
49 #define CAM1_CAP0_MASK 0xffffffff
50 #define CAM1_CAP0_WIDTH 32
51 #define CAM1_CAP0_RESET 0000000000
52 #define CAM1_CAP1 HW_REGISTER_RW( 0x7e801030 )
53 #define CAM1_CAP1_MASK 0xffffffff
54 #define CAM1_CAP1_WIDTH 32
55 #define CAM1_CAP1_RESET 0000000000
56 #define CAM1_DBG0 HW_REGISTER_RW( 0x7e8010f0 )
57 #define CAM1_DBG0_MASK 0xffffffff
58 #define CAM1_DBG0_WIDTH 32
59 #define CAM1_DBG0_RESET 0000000000
60 #define CAM1_DBG1 HW_REGISTER_RW( 0x7e8010f4 )
61 #define CAM1_DBG1_MASK 0xffffffff
62 #define CAM1_DBG1_WIDTH 32
63 #define CAM1_DBG1_RESET 0000000000
64 #define CAM1_DBG2 HW_REGISTER_RW( 0x7e8010f8 )
65 #define CAM1_DBG2_MASK 0xffffffff
66 #define CAM1_DBG2_WIDTH 32
67 #define CAM1_DBG2_RESET 0000000000
68 #define CAM1_ICTL HW_REGISTER_RW( 0x7e801100 )
69 #define CAM1_ICTL_MASK 0xffffffff
70 #define CAM1_ICTL_WIDTH 32
71 #define CAM1_ICTL_RESET 0000000000
72 #define CAM1_ISTA HW_REGISTER_RW( 0x7e801104 )
73 #define CAM1_ISTA_MASK 0xffffffff
74 #define CAM1_ISTA_WIDTH 32
75 #define CAM1_ISTA_RESET 0000000000
76 #define CAM1_IDI HW_REGISTER_RW( 0x7e801108 )
77 #define CAM1_IDI_MASK 0xffffffff
78 #define CAM1_IDI_WIDTH 32
79 #define CAM1_IDI_RESET 0000000000
80 #define CAM1_IPIPE HW_REGISTER_RW( 0x7e80110c )
81 #define CAM1_IPIPE_MASK 0xffffffff
82 #define CAM1_IPIPE_WIDTH 32
83 #define CAM1_IPIPE_RESET 0000000000
84 #define CAM1_IBSA HW_REGISTER_RW( 0x7e801110 )
85 #define CAM1_IBSA_MASK 0xffffffff
86 #define CAM1_IBSA_WIDTH 32
87 #define CAM1_IBSA_RESET 0000000000
88 #define CAM1_IBEA HW_REGISTER_RW( 0x7e801114 )
89 #define CAM1_IBEA_MASK 0xffffffff
90 #define CAM1_IBEA_WIDTH 32
91 #define CAM1_IBEA_RESET 0000000000
92 #define CAM1_IBLS HW_REGISTER_RW( 0x7e801118 )
93 #define CAM1_IBLS_MASK 0xffffffff
94 #define CAM1_IBLS_WIDTH 32
95 #define CAM1_IBLS_RESET 0000000000
96 #define CAM1_IBWP HW_REGISTER_RW( 0x7e80111c )
97 #define CAM1_IBWP_MASK 0xffffffff
98 #define CAM1_IBWP_WIDTH 32
99 #define CAM1_IBWP_RESET 0000000000
100 #define CAM1_IHWIN HW_REGISTER_RW( 0x7e801120 )
101 #define CAM1_IHWIN_MASK 0xffffffff
102 #define CAM1_IHWIN_WIDTH 32
103 #define CAM1_IHWIN_RESET 0000000000
104 #define CAM1_IHSTA HW_REGISTER_RW( 0x7e801124 )
105 #define CAM1_IHSTA_MASK 0xffffffff
106 #define CAM1_IHSTA_WIDTH 32
107 #define CAM1_IHSTA_RESET 0000000000
108 #define CAM1_IVWIN HW_REGISTER_RW( 0x7e801128 )
109 #define CAM1_IVWIN_MASK 0xffffffff
110 #define CAM1_IVWIN_WIDTH 32
111 #define CAM1_IVWIN_RESET 0000000000
112 #define CAM1_IVSTA HW_REGISTER_RW( 0x7e80112c )
113 #define CAM1_IVSTA_MASK 0xffffffff
114 #define CAM1_IVSTA_WIDTH 32
115 #define CAM1_IVSTA_RESET 0000000000
116 #define CAM1_DCS HW_REGISTER_RW( 0x7e801200 )
117 #define CAM1_DCS_MASK 0xffffffff
118 #define CAM1_DCS_WIDTH 32
119 #define CAM1_DCS_RESET 0000000000
120 #define CAM1_DBSA HW_REGISTER_RW( 0x7e801204 )
121 #define CAM1_DBSA_MASK 0xffffffff
122 #define CAM1_DBSA_WIDTH 32
123 #define CAM1_DBSA_RESET 0000000000
124 #define CAM1_DBEA HW_REGISTER_RW( 0x7e801208 )
125 #define CAM1_DBEA_MASK 0xffffffff
126 #define CAM1_DBEA_WIDTH 32
127 #define CAM1_DBEA_RESET 0000000000
128 #define CAM1_DBWP HW_REGISTER_RW( 0x7e801208 )
129 #define CAM1_DBWP_MASK 0xffffffff
130 #define CAM1_DBWP_WIDTH 32
131 #define CAM1_DBWP_RESET 0000000000
This page took 0.079217 seconds and 4 git commands to generate.