Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / camccp.h
1 // This file was generated by the create_regs script
2 #define CCP_BASE 0x7e801000
3 #define CCP_APB_ID 0x63637032
4 #define CCP_RC HW_REGISTER_RW( 0x7e801000 )
5 #define CCP_RC_MASK 0xffffffff
6 #define CCP_RC_WIDTH 32
7 #define CCP_RC__MSB 31
8 #define CCP_RC__LSB 0
9 #define CCP_RS HW_REGISTER_RW( 0x7e801004 )
10 #define CCP_RS_MASK 0xffffffff
11 #define CCP_RS_WIDTH 32
12 #define CCP_RS__MSB 31
13 #define CCP_RS__LSB 0
14 #define CCP_RDR1 HW_REGISTER_RW( 0x7e801080 )
15 #define CCP_RDR1_MASK 0xffffffff
16 #define CCP_RDR1_WIDTH 32
17 #define CCP_RDR1__MSB 31
18 #define CCP_RDR1__LSB 0
19 #define CCP_RDR2 HW_REGISTER_RW( 0x7e801084 )
20 #define CCP_RDR2_MASK 0xffffffff
21 #define CCP_RDR2_WIDTH 32
22 #define CCP_RDR2__MSB 31
23 #define CCP_RDR2__LSB 0
24 #define CCP_RDR3 HW_REGISTER_RW( 0x7e801088 )
25 #define CCP_RDR3_MASK 0xffffffff
26 #define CCP_RDR3_WIDTH 32
27 #define CCP_RDR3__MSB 31
28 #define CCP_RDR3__LSB 0
29 #define CCP_RC0 HW_REGISTER_RW( 0x7e801100 )
30 #define CCP_RC0_MASK 0xffffffff
31 #define CCP_RC0_WIDTH 32
32 #define CCP_RC0__MSB 31
33 #define CCP_RC0__LSB 0
34 #define CCP_RPC0 HW_REGISTER_RW( 0x7e801104 )
35 #define CCP_RPC0_MASK 0xffffffff
36 #define CCP_RPC0_WIDTH 32
37 #define CCP_RPC0__MSB 31
38 #define CCP_RPC0__LSB 0
39 #define CCP_RS0 HW_REGISTER_RW( 0x7e801108 )
40 #define CCP_RS0_MASK 0xffffffff
41 #define CCP_RS0_WIDTH 32
42 #define CCP_RS0__MSB 31
43 #define CCP_RS0__LSB 0
44 #define CCP_RSA0 HW_REGISTER_RW( 0x7e80110c )
45 #define CCP_RSA0_MASK 0xffffffff
46 #define CCP_RSA0_WIDTH 32
47 #define CCP_RSA0__MSB 31
48 #define CCP_RSA0__LSB 0
49 #define CCP_REA0 HW_REGISTER_RW( 0x7e801110 )
50 #define CCP_REA0_MASK 0xffffffff
51 #define CCP_REA0_WIDTH 32
52 #define CCP_REA0__MSB 31
53 #define CCP_REA0__LSB 0
54 #define CCP_RWP0 HW_REGISTER_RW( 0x7e801114 )
55 #define CCP_RWP0_MASK 0xffffffff
56 #define CCP_RWP0_WIDTH 32
57 #define CCP_RWP0__MSB 31
58 #define CCP_RWP0__LSB 0
59 #define CCP_RBC0 HW_REGISTER_RW( 0x7e801118 )
60 #define CCP_RBC0_MASK 0xffffffff
61 #define CCP_RBC0_WIDTH 32
62 #define CCP_RBC0__MSB 31
63 #define CCP_RBC0__LSB 0
64 #define CCP_RLS0 HW_REGISTER_RW( 0x7e80111c )
65 #define CCP_RLS0_MASK 0xffffffff
66 #define CCP_RLS0_WIDTH 32
67 #define CCP_RLS0__MSB 31
68 #define CCP_RLS0__LSB 0
69 #define CCP_RDSA0 HW_REGISTER_RW( 0x7e801120 )
70 #define CCP_RDSA0_MASK 0xffffffff
71 #define CCP_RDSA0_WIDTH 32
72 #define CCP_RDSA0__MSB 31
73 #define CCP_RDSA0__LSB 0
74 #define CCP_RDEA0 HW_REGISTER_RW( 0x7e801124 )
75 #define CCP_RDEA0_MASK 0xffffffff
76 #define CCP_RDEA0_WIDTH 32
77 #define CCP_RDEA0__MSB 31
78 #define CCP_RDEA0__LSB 0
79 #define CCP_RDS0 HW_REGISTER_RW( 0x7e801128 )
80 #define CCP_RDS0_MASK 0xffffffff
81 #define CCP_RDS0_WIDTH 32
82 #define CCP_RDS0__MSB 31
83 #define CCP_RDS0__LSB 0
84 #define CCP_RC1 HW_REGISTER_RW( 0x7e801200 )
85 #define CCP_RC1_MASK 0xffffffff
86 #define CCP_RC1_WIDTH 32
87 #define CCP_RC1__MSB 31
88 #define CCP_RC1__LSB 0
89 #define CCP_RPC1 HW_REGISTER_RW( 0x7e801204 )
90 #define CCP_RPC1_MASK 0xffffffff
91 #define CCP_RPC1_WIDTH 32
92 #define CCP_RPC1__MSB 31
93 #define CCP_RPC1__LSB 0
94 #define CCP_RS1 HW_REGISTER_RW( 0x7e801208 )
95 #define CCP_RS1_MASK 0xffffffff
96 #define CCP_RS1_WIDTH 32
97 #define CCP_RS1__MSB 31
98 #define CCP_RS1__LSB 0
99 #define CCP_RSA1 HW_REGISTER_RW( 0x7e80120c )
100 #define CCP_RSA1_MASK 0xffffffff
101 #define CCP_RSA1_WIDTH 32
102 #define CCP_RSA1__MSB 31
103 #define CCP_RSA1__LSB 0
104 #define CCP_REA1 HW_REGISTER_RW( 0x7e801210 )
105 #define CCP_REA1_MASK 0xffffffff
106 #define CCP_REA1_WIDTH 32
107 #define CCP_REA1__MSB 31
108 #define CCP_REA1__LSB 0
109 #define CCP_RWP1 HW_REGISTER_RW( 0x7e801214 )
110 #define CCP_RWP1_MASK 0xffffffff
111 #define CCP_RWP1_WIDTH 32
112 #define CCP_RWP1__MSB 31
113 #define CCP_RWP1__LSB 0
114 #define CCP_RBC1 HW_REGISTER_RW( 0x7e801218 )
115 #define CCP_RBC1_MASK 0xffffffff
116 #define CCP_RBC1_WIDTH 32
117 #define CCP_RBC1__MSB 31
118 #define CCP_RBC1__LSB 0
119 #define CCP_RLS1 HW_REGISTER_RW( 0x7e80121c )
120 #define CCP_RLS1_MASK 0xffffffff
121 #define CCP_RLS1_WIDTH 32
122 #define CCP_RLS1__MSB 31
123 #define CCP_RLS1__LSB 0
124 #define CCP_RDSA1 HW_REGISTER_RW( 0x7e801220 )
125 #define CCP_RDSA1_MASK 0xffffffff
126 #define CCP_RDSA1_WIDTH 32
127 #define CCP_RDSA1__MSB 31
128 #define CCP_RDSA1__LSB 0
129 #define CCP_RDEA1 HW_REGISTER_RW( 0x7e801224 )
130 #define CCP_RDEA1_MASK 0xffffffff
131 #define CCP_RDEA1_WIDTH 32
132 #define CCP_RDEA1__MSB 31
133 #define CCP_RDEA1__LSB 0
134 #define CCP_RDS1 HW_REGISTER_RW( 0x7e801228 )
135 #define CCP_RDS1_MASK 0xffffffff
136 #define CCP_RDS1_WIDTH 32
137 #define CCP_RDS1__MSB 31
138 #define CCP_RDS1__LSB 0
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