19b3f77610f6fbdcb4f5347a158c634ac9576311
[rpi-open-firmware.git] / bcm2708_chip / ccp2tx.h
1 // This file was generated by the create_regs script
2 #define CCP2TX_BASE 0x7e001000
3 #define CCP2TX_APB_ID 0x63637032
4 #define CCP2TX_TC HW_REGISTER_RW( 0x7e001000 )
5 #define CCP2TX_TC_MASK 0x8000ff07
6 #define CCP2TX_TC_WIDTH 32
7 #define CCP2TX_TC_RESET 0x0000ff00
8 #define CCP2TX_TC_SWR_BITS 31:31
9 #define CCP2TX_TC_SWR_SET 0x80000000
10 #define CCP2TX_TC_SWR_CLR 0x7fffffff
11 #define CCP2TX_TC_SWR_MSB 31
12 #define CCP2TX_TC_SWR_LSB 31
13 #define CCP2TX_TC_TIP_BITS 15:8
14 #define CCP2TX_TC_TIP_SET 0x0000ff00
15 #define CCP2TX_TC_TIP_CLR 0xffff00ff
16 #define CCP2TX_TC_TIP_MSB 15
17 #define CCP2TX_TC_TIP_LSB 8
18 #define CCP2TX_TC_CLKM_BITS 2:2
19 #define CCP2TX_TC_CLKM_SET 0x00000004
20 #define CCP2TX_TC_CLKM_CLR 0xfffffffb
21 #define CCP2TX_TC_CLKM_MSB 2
22 #define CCP2TX_TC_CLKM_LSB 2
23 #define CCP2TX_TC_MEN_BITS 1:1
24 #define CCP2TX_TC_MEN_SET 0x00000002
25 #define CCP2TX_TC_MEN_CLR 0xfffffffd
26 #define CCP2TX_TC_MEN_MSB 1
27 #define CCP2TX_TC_MEN_LSB 1
28 #define CCP2TX_TC_TEN_BITS 0:0
29 #define CCP2TX_TC_TEN_SET 0x00000001
30 #define CCP2TX_TC_TEN_CLR 0xfffffffe
31 #define CCP2TX_TC_TEN_MSB 0
32 #define CCP2TX_TC_TEN_LSB 0
33 #define CCP2TX_TS HW_REGISTER_RW( 0x7e001004 )
34 #define CCP2TX_TS_MASK 0x000f1f7f
35 #define CCP2TX_TS_WIDTH 20
36 #define CCP2TX_TS_RESET 0000000000
37 #define CCP2TX_TS_TQI_BITS 19:19
38 #define CCP2TX_TS_TQI_SET 0x00080000
39 #define CCP2TX_TS_TQI_CLR 0xfff7ffff
40 #define CCP2TX_TS_TQI_MSB 19
41 #define CCP2TX_TS_TQI_LSB 19
42 #define CCP2TX_TS_TEI_BITS 18:18
43 #define CCP2TX_TS_TEI_SET 0x00040000
44 #define CCP2TX_TS_TEI_CLR 0xfffbffff
45 #define CCP2TX_TS_TEI_MSB 18
46 #define CCP2TX_TS_TEI_LSB 18
47 #define CCP2TX_TS_TII_BITS 17:17
48 #define CCP2TX_TS_TII_SET 0x00020000
49 #define CCP2TX_TS_TII_CLR 0xfffdffff
50 #define CCP2TX_TS_TII_MSB 17
51 #define CCP2TX_TS_TII_LSB 17
52 #define CCP2TX_TS_IS_BITS 16:16
53 #define CCP2TX_TS_IS_SET 0x00010000
54 #define CCP2TX_TS_IS_CLR 0xfffeffff
55 #define CCP2TX_TS_IS_MSB 16
56 #define CCP2TX_TS_IS_LSB 16
57 #define CCP2TX_TS_TQL_BITS 12:8
58 #define CCP2TX_TS_TQL_SET 0x00001f00
59 #define CCP2TX_TS_TQL_CLR 0xffffe0ff
60 #define CCP2TX_TS_TQL_MSB 12
61 #define CCP2TX_TS_TQL_LSB 8
62 #define CCP2TX_TS_TFP_BITS 6:6
63 #define CCP2TX_TS_TFP_SET 0x00000040
64 #define CCP2TX_TS_TFP_CLR 0xffffffbf
65 #define CCP2TX_TS_TFP_MSB 6
66 #define CCP2TX_TS_TFP_LSB 6
67 #define CCP2TX_TS_TFF_BITS 5:5
68 #define CCP2TX_TS_TFF_SET 0x00000020
69 #define CCP2TX_TS_TFF_CLR 0xffffffdf
70 #define CCP2TX_TS_TFF_MSB 5
71 #define CCP2TX_TS_TFF_LSB 5
72 #define CCP2TX_TS_TFE_BITS 4:4
73 #define CCP2TX_TS_TFE_SET 0x00000010
74 #define CCP2TX_TS_TFE_CLR 0xffffffef
75 #define CCP2TX_TS_TFE_MSB 4
76 #define CCP2TX_TS_TFE_LSB 4
77 #define CCP2TX_TS_TUE_BITS 3:3
78 #define CCP2TX_TS_TUE_SET 0x00000008
79 #define CCP2TX_TS_TUE_CLR 0xfffffff7
80 #define CCP2TX_TS_TUE_MSB 3
81 #define CCP2TX_TS_TUE_LSB 3
82 #define CCP2TX_TS_ARE_BITS 2:2
83 #define CCP2TX_TS_ARE_SET 0x00000004
84 #define CCP2TX_TS_ARE_CLR 0xfffffffb
85 #define CCP2TX_TS_ARE_MSB 2
86 #define CCP2TX_TS_ARE_LSB 2
87 #define CCP2TX_TS_IEB_BITS 1:1
88 #define CCP2TX_TS_IEB_SET 0x00000002
89 #define CCP2TX_TS_IEB_CLR 0xfffffffd
90 #define CCP2TX_TS_IEB_MSB 1
91 #define CCP2TX_TS_IEB_LSB 1
92 #define CCP2TX_TS_TXB_BITS 0:0
93 #define CCP2TX_TS_TXB_SET 0x00000001
94 #define CCP2TX_TS_TXB_CLR 0xfffffffe
95 #define CCP2TX_TS_TXB_MSB 0
96 #define CCP2TX_TS_TXB_LSB 0
97 #define CCP2TX_TAC HW_REGISTER_RW( 0x7e001008 )
98 #define CCP2TX_TAC_MASK 0xffffff0f
99 #define CCP2TX_TAC_WIDTH 32
100 #define CCP2TX_TAC_RESET 0x77434307
101 #define CCP2TX_TAC_CTATADJ_BITS 31:28
102 #define CCP2TX_TAC_CTATADJ_SET 0xf0000000
103 #define CCP2TX_TAC_CTATADJ_CLR 0x0fffffff
104 #define CCP2TX_TAC_CTATADJ_MSB 31
105 #define CCP2TX_TAC_CTATADJ_LSB 28
106 #define CCP2TX_TAC_PTATADJ_BITS 27:24
107 #define CCP2TX_TAC_PTATADJ_SET 0x0f000000
108 #define CCP2TX_TAC_PTATADJ_CLR 0xf0ffffff
109 #define CCP2TX_TAC_PTATADJ_MSB 27
110 #define CCP2TX_TAC_PTATADJ_LSB 24
111 #define CCP2TX_TAC_CLAC_BITS 23:16
112 #define CCP2TX_TAC_CLAC_SET 0x00ff0000
113 #define CCP2TX_TAC_CLAC_CLR 0xff00ffff
114 #define CCP2TX_TAC_CLAC_MSB 23
115 #define CCP2TX_TAC_CLAC_LSB 16
116 #define CCP2TX_TAC_DLAC_BITS 15:8
117 #define CCP2TX_TAC_DLAC_SET 0x0000ff00
118 #define CCP2TX_TAC_DLAC_CLR 0xffff00ff
119 #define CCP2TX_TAC_DLAC_MSB 15
120 #define CCP2TX_TAC_DLAC_LSB 8
121 #define CCP2TX_TAC_TPC_BITS 3:3
122 #define CCP2TX_TAC_TPC_SET 0x00000008
123 #define CCP2TX_TAC_TPC_CLR 0xfffffff7
124 #define CCP2TX_TAC_TPC_MSB 3
125 #define CCP2TX_TAC_TPC_LSB 3
126 #define CCP2TX_TAC_BPD_BITS 2:2
127 #define CCP2TX_TAC_BPD_SET 0x00000004
128 #define CCP2TX_TAC_BPD_CLR 0xfffffffb
129 #define CCP2TX_TAC_BPD_MSB 2
130 #define CCP2TX_TAC_BPD_LSB 2
131 #define CCP2TX_TAC_APD_BITS 1:1
132 #define CCP2TX_TAC_APD_SET 0x00000002
133 #define CCP2TX_TAC_APD_CLR 0xfffffffd
134 #define CCP2TX_TAC_APD_MSB 1
135 #define CCP2TX_TAC_APD_LSB 1
136 #define CCP2TX_TAC_ARST_BITS 0:0
137 #define CCP2TX_TAC_ARST_SET 0x00000001
138 #define CCP2TX_TAC_ARST_CLR 0xfffffffe
139 #define CCP2TX_TAC_ARST_MSB 0
140 #define CCP2TX_TAC_ARST_LSB 0
141 #define CCP2TX_TPC HW_REGISTER_RW( 0x7e00100c )
142 #define CCP2TX_TPC_MASK 0x0000ffff
143 #define CCP2TX_TPC_WIDTH 16
144 #define CCP2TX_TPC_RESET 0000000000
145 #define CCP2TX_TPC_TPT_BITS 15:8
146 #define CCP2TX_TPC_TPT_SET 0x0000ff00
147 #define CCP2TX_TPC_TPT_CLR 0xffff00ff
148 #define CCP2TX_TPC_TPT_MSB 15
149 #define CCP2TX_TPC_TPT_LSB 8
150 #define CCP2TX_TPC_TPP_BITS 7:4
151 #define CCP2TX_TPC_TPP_SET 0x000000f0
152 #define CCP2TX_TPC_TPP_CLR 0xffffff0f
153 #define CCP2TX_TPC_TPP_MSB 7
154 #define CCP2TX_TPC_TPP_LSB 4
155 #define CCP2TX_TPC_TNP_BITS 3:0
156 #define CCP2TX_TPC_TNP_SET 0x0000000f
157 #define CCP2TX_TPC_TNP_CLR 0xfffffff0
158 #define CCP2TX_TPC_TNP_MSB 3
159 #define CCP2TX_TPC_TNP_LSB 0
160 #define CCP2TX_TSC HW_REGISTER_RW( 0x7e001010 )
161 #define CCP2TX_TSC_MASK 0x0000000f
162 #define CCP2TX_TSC_WIDTH 4
163 #define CCP2TX_TSC_RESET 0x00000002
164 #define CCP2TX_TSC_TSM_BITS 3:0
165 #define CCP2TX_TSC_TSM_SET 0x0000000f
166 #define CCP2TX_TSC_TSM_CLR 0xfffffff0
167 #define CCP2TX_TSC_TSM_MSB 3
168 #define CCP2TX_TSC_TSM_LSB 0
169 #define CCP2TX_TIC HW_REGISTER_RW( 0x7e001014 )
170 #define CCP2TX_TIC_MASK 0x000000f7
171 #define CCP2TX_TIC_WIDTH 8
172 #define CCP2TX_TIC_RESET 0000000000
173 #define CCP2TX_TIC_TQIT_BITS 7:4
174 #define CCP2TX_TIC_TQIT_SET 0x000000f0
175 #define CCP2TX_TIC_TQIT_CLR 0xffffff0f
176 #define CCP2TX_TIC_TQIT_MSB 7
177 #define CCP2TX_TIC_TQIT_LSB 4
178 #define CCP2TX_TIC_TQIE_BITS 2:2
179 #define CCP2TX_TIC_TQIE_SET 0x00000004
180 #define CCP2TX_TIC_TQIE_CLR 0xfffffffb
181 #define CCP2TX_TIC_TQIE_MSB 2
182 #define CCP2TX_TIC_TQIE_LSB 2
183 #define CCP2TX_TIC_TEIE_BITS 1:1
184 #define CCP2TX_TIC_TEIE_SET 0x00000002
185 #define CCP2TX_TIC_TEIE_CLR 0xfffffffd
186 #define CCP2TX_TIC_TEIE_MSB 1
187 #define CCP2TX_TIC_TEIE_LSB 1
188 #define CCP2TX_TIC_TIIE_BITS 0:0
189 #define CCP2TX_TIC_TIIE_SET 0x00000001
190 #define CCP2TX_TIC_TIIE_CLR 0xfffffffe
191 #define CCP2TX_TIC_TIIE_MSB 0
192 #define CCP2TX_TIC_TIIE_LSB 0
193 #define CCP2TX_TTC HW_REGISTER_RW( 0x7e001018 )
194 #define CCP2TX_TTC_MASK 0x80ff1fff
195 #define CCP2TX_TTC_WIDTH 32
196 #define CCP2TX_TTC_RESET 0x00000100
197 #define CCP2TX_TTC_ATX_BITS 31:31
198 #define CCP2TX_TTC_ATX_SET 0x80000000
199 #define CCP2TX_TTC_ATX_CLR 0x7fffffff
200 #define CCP2TX_TTC_ATX_MSB 31
201 #define CCP2TX_TTC_ATX_LSB 31
202 #define CCP2TX_TTC_BI_BITS 23:16
203 #define CCP2TX_TTC_BI_SET 0x00ff0000
204 #define CCP2TX_TTC_BI_CLR 0xff00ffff
205 #define CCP2TX_TTC_BI_MSB 23
206 #define CCP2TX_TTC_BI_LSB 16
207 #define CCP2TX_TTC_FSP_BITS 12:12
208 #define CCP2TX_TTC_FSP_SET 0x00001000
209 #define CCP2TX_TTC_FSP_CLR 0xffffefff
210 #define CCP2TX_TTC_FSP_MSB 12
211 #define CCP2TX_TTC_FSP_LSB 12
212 #define CCP2TX_TTC_LEC_BITS 11:8
213 #define CCP2TX_TTC_LEC_SET 0x00000f00
214 #define CCP2TX_TTC_LEC_CLR 0xfffff0ff
215 #define CCP2TX_TTC_LEC_MSB 11
216 #define CCP2TX_TTC_LEC_LSB 8
217 #define CCP2TX_TTC_LSC_BITS 7:4
218 #define CCP2TX_TTC_LSC_SET 0x000000f0
219 #define CCP2TX_TTC_LSC_CLR 0xffffff0f
220 #define CCP2TX_TTC_LSC_MSB 7
221 #define CCP2TX_TTC_LSC_LSB 4
222 #define CCP2TX_TTC_LCN_BITS 3:0
223 #define CCP2TX_TTC_LCN_SET 0x0000000f
224 #define CCP2TX_TTC_LCN_CLR 0xfffffff0
225 #define CCP2TX_TTC_LCN_MSB 3
226 #define CCP2TX_TTC_LCN_LSB 0
227 #define CCP2TX_TBA HW_REGISTER_RW( 0x7e00101c )
228 #define CCP2TX_TBA_MASK 0x3fffffff
229 #define CCP2TX_TBA_WIDTH 30
230 #define CCP2TX_TBA_RESET 0000000000
231 #define CCP2TX_TBA_ADDR_BITS 29:0
232 #define CCP2TX_TBA_ADDR_SET 0x3fffffff
233 #define CCP2TX_TBA_ADDR_CLR 0xc0000000
234 #define CCP2TX_TBA_ADDR_MSB 29
235 #define CCP2TX_TBA_ADDR_LSB 0
236 #define CCP2TX_TDL HW_REGISTER_RW( 0x7e001020 )
237 #define CCP2TX_TDL_MASK 0x3fffffff
238 #define CCP2TX_TDL_WIDTH 30
239 #define CCP2TX_TDL_RESET 0000000000
240 #define CCP2TX_TDL_LEN_BITS 29:0
241 #define CCP2TX_TDL_LEN_SET 0x3fffffff
242 #define CCP2TX_TDL_LEN_CLR 0xc0000000
243 #define CCP2TX_TDL_LEN_MSB 29
244 #define CCP2TX_TDL_LEN_LSB 0
245 #define CCP2TX_TD HW_REGISTER_RW( 0x7e001024 )
246 #define CCP2TX_TD_MASK 0x000000ff
247 #define CCP2TX_TD_WIDTH 8
248 #define CCP2TX_TD_IES_BITS 6:5
249 #define CCP2TX_TD_IES_SET 0x00000060
250 #define CCP2TX_TD_IES_CLR 0xffffff9f
251 #define CCP2TX_TD_IES_MSB 6
252 #define CCP2TX_TD_IES_LSB 5
253 #define CCP2TX_TD_TCS_BITS 4:0
254 #define CCP2TX_TD_TCS_SET 0x0000001f
255 #define CCP2TX_TD_TCS_CLR 0xffffffe0
256 #define CCP2TX_TD_TCS_MSB 4
257 #define CCP2TX_TD_TCS_LSB 0
258 #define CCP2TX_TSPARE HW_REGISTER_RW( 0x7e001028 )
259 #define CCP2TX_TSPARE_MASK 0xffffffff
260 #define CCP2TX_TSPARE_WIDTH 32
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