Initial commit
[rpi-open-firmware.git] / bcm2708_chip / clkman_image.h
1 // This file was generated by the create_regs script
2 #define CMI_PASSWORD 0x5a000000
3 #define CMI_BASE 0x7e802000
4 #define CMI_APB_ID 0x00636d69
5 #define CMI_CAM0 HW_REGISTER_RW( 0x7e802000 )
6 #define CMI_CAM0_MASK 0x0000003f
7 #define CMI_CAM0_WIDTH 6
8 #define CMI_CAM0_RESET 0000000000
9 #define CMI_CAM0_RX1SRC_BITS 5:4
10 #define CMI_CAM0_RX1SRC_SET 0x00000030
11 #define CMI_CAM0_RX1SRC_CLR 0xffffffcf
12 #define CMI_CAM0_RX1SRC_MSB 5
13 #define CMI_CAM0_RX1SRC_LSB 4
14 #define CMI_CAM0_RX0SRC_BITS 3:2
15 #define CMI_CAM0_RX0SRC_SET 0x0000000c
16 #define CMI_CAM0_RX0SRC_CLR 0xfffffff3
17 #define CMI_CAM0_RX0SRC_MSB 3
18 #define CMI_CAM0_RX0SRC_LSB 2
19 #define CMI_CAM0_HSSRC_BITS 1:0
20 #define CMI_CAM0_HSSRC_SET 0x00000003
21 #define CMI_CAM0_HSSRC_CLR 0xfffffffc
22 #define CMI_CAM0_HSSRC_MSB 1
23 #define CMI_CAM0_HSSRC_LSB 0
24 #define CMI_CAM1 HW_REGISTER_RW( 0x7e802004 )
25 #define CMI_CAM1_MASK 0x000003ff
26 #define CMI_CAM1_WIDTH 10
27 #define CMI_CAM1_RESET 0000000000
28 #define CMI_CAM1_RX3SRC_BITS 9:8
29 #define CMI_CAM1_RX3SRC_SET 0x00000300
30 #define CMI_CAM1_RX3SRC_CLR 0xfffffcff
31 #define CMI_CAM1_RX3SRC_MSB 9
32 #define CMI_CAM1_RX3SRC_LSB 8
33 #define CMI_CAM1_RX2SRC_BITS 7:6
34 #define CMI_CAM1_RX2SRC_SET 0x000000c0
35 #define CMI_CAM1_RX2SRC_CLR 0xffffff3f
36 #define CMI_CAM1_RX2SRC_MSB 7
37 #define CMI_CAM1_RX2SRC_LSB 6
38 #define CMI_CAM1_RX1SRC_BITS 5:4
39 #define CMI_CAM1_RX1SRC_SET 0x00000030
40 #define CMI_CAM1_RX1SRC_CLR 0xffffffcf
41 #define CMI_CAM1_RX1SRC_MSB 5
42 #define CMI_CAM1_RX1SRC_LSB 4
43 #define CMI_CAM1_RX0SRC_BITS 3:2
44 #define CMI_CAM1_RX0SRC_SET 0x0000000c
45 #define CMI_CAM1_RX0SRC_CLR 0xfffffff3
46 #define CMI_CAM1_RX0SRC_MSB 3
47 #define CMI_CAM1_RX0SRC_LSB 2
48 #define CMI_CAM1_HSSRC_BITS 1:0
49 #define CMI_CAM1_HSSRC_SET 0x00000003
50 #define CMI_CAM1_HSSRC_CLR 0xfffffffc
51 #define CMI_CAM1_HSSRC_MSB 1
52 #define CMI_CAM1_HSSRC_LSB 0
53 #define CMI_CAMTEST HW_REGISTER_RW( 0x7e802008 )
54 #define CMI_CAMTEST_MASK 0x0000001f
55 #define CMI_CAMTEST_WIDTH 5
56 #define CMI_CAMTEST_RESET 0000000000
57 #define CMI_CAMTEST_ENAB_BITS 4:4
58 #define CMI_CAMTEST_ENAB_SET 0x00000010
59 #define CMI_CAMTEST_ENAB_CLR 0xffffffef
60 #define CMI_CAMTEST_ENAB_MSB 4
61 #define CMI_CAMTEST_ENAB_LSB 4
62 #define CMI_CAMTEST_SRC_BITS 3:0
63 #define CMI_CAMTEST_SRC_SET 0x0000000f
64 #define CMI_CAMTEST_SRC_CLR 0xfffffff0
65 #define CMI_CAMTEST_SRC_MSB 3
66 #define CMI_CAMTEST_SRC_LSB 0
67 #define CMI_USBCTL HW_REGISTER_RW( 0x7e802010 )
68 #define CMI_USBCTL_MASK 0x00000040
69 #define CMI_USBCTL_WIDTH 7
70 #define CMI_USBCTL_RESET 0x00000040
71 #define CMI_USBCTL_GATE_BITS 6:6
72 #define CMI_USBCTL_GATE_SET 0x00000040
73 #define CMI_USBCTL_GATE_CLR 0xffffffbf
74 #define CMI_USBCTL_GATE_MSB 6
75 #define CMI_USBCTL_GATE_LSB 6
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