154bcf6b5263dcd1ac67eb681424aa785174693a
[rpi-open-firmware.git] / bcm2708_chip / cpr_apb2wtap.h
1 // This file was generated by the create_regs script
2 #define A2W_PASSWORD 0x5a000000
3 #define A2W_BASE 0x7e102000
4 #define A2W_APB_ID 0x00613277
5 #define A2W_PLLA_DIG0 HW_REGISTER_RW( 0x7e102000 )
6 #define A2W_PLLA_DIG0_MASK 0x00ffffff
7 #define A2W_PLLA_DIG0_WIDTH 24
8 #define A2W_PLLA_DIG0_RESET 0000000000
9 #define A2W_PLLA_DIG1 HW_REGISTER_RW( 0x7e102004 )
10 #define A2W_PLLA_DIG1_MASK 0x00ffffff
11 #define A2W_PLLA_DIG1_WIDTH 24
12 #define A2W_PLLA_DIG1_RESET 0x00004000
13 #define A2W_PLLA_DIG2 HW_REGISTER_RW( 0x7e102008 )
14 #define A2W_PLLA_DIG2_MASK 0x00ffffff
15 #define A2W_PLLA_DIG2_WIDTH 24
16 #define A2W_PLLA_DIG2_RESET 0x00100401
17 #define A2W_PLLA_DIG3 HW_REGISTER_RW( 0x7e10200c )
18 #define A2W_PLLA_DIG3_MASK 0x00ffffff
19 #define A2W_PLLA_DIG3_WIDTH 24
20 #define A2W_PLLA_DIG3_RESET 0x00000004
21 #define A2W_PLLA_ANA0 HW_REGISTER_RW( 0x7e102010 )
22 #define A2W_PLLA_ANA0_MASK 0x00ffffff
23 #define A2W_PLLA_ANA0_WIDTH 24
24 #define A2W_PLLA_ANA0_RESET 0000000000
25 #define A2W_PLLA_ANA1 HW_REGISTER_RW( 0x7e102014 )
26 #define A2W_PLLA_ANA1_MASK 0x00ffffff
27 #define A2W_PLLA_ANA1_WIDTH 24
28 #define A2W_PLLA_ANA1_RESET 0x001d0000
29 #define A2W_PLLA_ANA2 HW_REGISTER_RW( 0x7e102018 )
30 #define A2W_PLLA_ANA2_MASK 0x00ffffff
31 #define A2W_PLLA_ANA2_WIDTH 24
32 #define A2W_PLLA_ANA2_RESET 0000000000
33 #define A2W_PLLA_ANA3 HW_REGISTER_RW( 0x7e10201c )
34 #define A2W_PLLA_ANA3_MASK 0x00ffffff
35 #define A2W_PLLA_ANA3_WIDTH 24
36 #define A2W_PLLA_ANA3_RESET 0x00000180
37 #define A2W_PLLB_DIG0 HW_REGISTER_RW( 0x7e1020e0 )
38 #define A2W_PLLB_DIG0_MASK 0x00ffffff
39 #define A2W_PLLB_DIG0_WIDTH 24
40 #define A2W_PLLB_DIG0_RESET 0000000000
41 #define A2W_PLLB_DIG1 HW_REGISTER_RW( 0x7e1020e4 )
42 #define A2W_PLLB_DIG1_MASK 0x00ffffff
43 #define A2W_PLLB_DIG1_WIDTH 24
44 #define A2W_PLLB_DIG1_RESET 0x00004000
45 #define A2W_PLLB_DIG2 HW_REGISTER_RW( 0x7e1020e8 )
46 #define A2W_PLLB_DIG2_MASK 0x00ffffff
47 #define A2W_PLLB_DIG2_WIDTH 24
48 #define A2W_PLLB_DIG2_RESET 0x00100401
49 #define A2W_PLLB_DIG3 HW_REGISTER_RW( 0x7e1020ec )
50 #define A2W_PLLB_DIG3_MASK 0x00ffffff
51 #define A2W_PLLB_DIG3_WIDTH 24
52 #define A2W_PLLB_DIG3_RESET 0x00000004
53 #define A2W_PLLB_ANA0 HW_REGISTER_RW( 0x7e1020f0 )
54 #define A2W_PLLB_ANA0_MASK 0x00ffffff
55 #define A2W_PLLB_ANA0_WIDTH 24
56 #define A2W_PLLB_ANA0_RESET 0000000000
57 #define A2W_PLLB_ANA1 HW_REGISTER_RW( 0x7e1020f4 )
58 #define A2W_PLLB_ANA1_MASK 0x00ffffff
59 #define A2W_PLLB_ANA1_WIDTH 24
60 #define A2W_PLLB_ANA1_RESET 0x001d0000
61 #define A2W_PLLB_ANA2 HW_REGISTER_RW( 0x7e1020f8 )
62 #define A2W_PLLB_ANA2_MASK 0x00ffffff
63 #define A2W_PLLB_ANA2_WIDTH 24
64 #define A2W_PLLB_ANA2_RESET 0000000000
65 #define A2W_PLLB_ANA3 HW_REGISTER_RW( 0x7e1020fc )
66 #define A2W_PLLB_ANA3_MASK 0x00ffffff
67 #define A2W_PLLB_ANA3_WIDTH 24
68 #define A2W_PLLB_ANA3_RESET 0x00000180
69 #define A2W_PLLC_DIG0 HW_REGISTER_RW( 0x7e102020 )
70 #define A2W_PLLC_DIG0_MASK 0x00ffffff
71 #define A2W_PLLC_DIG0_WIDTH 24
72 #define A2W_PLLC_DIG0_RESET 0000000000
73 #define A2W_PLLC_DIG1 HW_REGISTER_RW( 0x7e102024 )
74 #define A2W_PLLC_DIG1_MASK 0x00ffffff
75 #define A2W_PLLC_DIG1_WIDTH 24
76 #define A2W_PLLC_DIG1_RESET 0x00004000
77 #define A2W_PLLC_DIG2 HW_REGISTER_RW( 0x7e102028 )
78 #define A2W_PLLC_DIG2_MASK 0x00ffffff
79 #define A2W_PLLC_DIG2_WIDTH 24
80 #define A2W_PLLC_DIG2_RESET 0x00100401
81 #define A2W_PLLC_DIG3 HW_REGISTER_RW( 0x7e10202c )
82 #define A2W_PLLC_DIG3_MASK 0x00ffffff
83 #define A2W_PLLC_DIG3_WIDTH 24
84 #define A2W_PLLC_DIG3_RESET 0x00000004
85 #define A2W_PLLC_ANA0 HW_REGISTER_RW( 0x7e102030 )
86 #define A2W_PLLC_ANA0_MASK 0x00ffffff
87 #define A2W_PLLC_ANA0_WIDTH 24
88 #define A2W_PLLC_ANA0_RESET 0000000000
89 #define A2W_PLLC_ANA1 HW_REGISTER_RW( 0x7e102034 )
90 #define A2W_PLLC_ANA1_MASK 0x00ffffff
91 #define A2W_PLLC_ANA1_WIDTH 24
92 #define A2W_PLLC_ANA1_RESET 0x001d0000
93 #define A2W_PLLC_ANA2 HW_REGISTER_RW( 0x7e102038 )
94 #define A2W_PLLC_ANA2_MASK 0x00ffffff
95 #define A2W_PLLC_ANA2_WIDTH 24
96 #define A2W_PLLC_ANA2_RESET 0000000000
97 #define A2W_PLLC_ANA3 HW_REGISTER_RW( 0x7e10203c )
98 #define A2W_PLLC_ANA3_MASK 0x00ffffff
99 #define A2W_PLLC_ANA3_WIDTH 24
100 #define A2W_PLLC_ANA3_RESET 0x00000180
101 #define A2W_PLLD_DIG0 HW_REGISTER_RW( 0x7e102040 )
102 #define A2W_PLLD_DIG0_MASK 0x00ffffff
103 #define A2W_PLLD_DIG0_WIDTH 24
104 #define A2W_PLLD_DIG0_RESET 0000000000
105 #define A2W_PLLD_DIG1 HW_REGISTER_RW( 0x7e102044 )
106 #define A2W_PLLD_DIG1_MASK 0x00ffffff
107 #define A2W_PLLD_DIG1_WIDTH 24
108 #define A2W_PLLD_DIG1_RESET 0x00004000
109 #define A2W_PLLD_DIG2 HW_REGISTER_RW( 0x7e102048 )
110 #define A2W_PLLD_DIG2_MASK 0x00ffffff
111 #define A2W_PLLD_DIG2_WIDTH 24
112 #define A2W_PLLD_DIG2_RESET 0x00100401
113 #define A2W_PLLD_DIG3 HW_REGISTER_RW( 0x7e10204c )
114 #define A2W_PLLD_DIG3_MASK 0x00ffffff
115 #define A2W_PLLD_DIG3_WIDTH 24
116 #define A2W_PLLD_DIG3_RESET 0x00000004
117 #define A2W_PLLD_ANA0 HW_REGISTER_RW( 0x7e102050 )
118 #define A2W_PLLD_ANA0_MASK 0x00ffffff
119 #define A2W_PLLD_ANA0_WIDTH 24
120 #define A2W_PLLD_ANA0_RESET 0000000000
121 #define A2W_PLLD_ANA1 HW_REGISTER_RW( 0x7e102054 )
122 #define A2W_PLLD_ANA1_MASK 0x00ffffff
123 #define A2W_PLLD_ANA1_WIDTH 24
124 #define A2W_PLLD_ANA1_RESET 0x001d0000
125 #define A2W_PLLD_ANA2 HW_REGISTER_RW( 0x7e102058 )
126 #define A2W_PLLD_ANA2_MASK 0x00ffffff
127 #define A2W_PLLD_ANA2_WIDTH 24
128 #define A2W_PLLD_ANA2_RESET 0000000000
129 #define A2W_PLLD_ANA3 HW_REGISTER_RW( 0x7e10205c )
130 #define A2W_PLLD_ANA3_MASK 0x00ffffff
131 #define A2W_PLLD_ANA3_WIDTH 24
132 #define A2W_PLLD_ANA3_RESET 0x00000180
133 #define A2W_PLLH_DIG0 HW_REGISTER_RW( 0x7e102060 )
134 #define A2W_PLLH_DIG0_MASK 0x00ffffff
135 #define A2W_PLLH_DIG0_WIDTH 24
136 #define A2W_PLLH_DIG0_RESET 0000000000
137 #define A2W_PLLH_DIG1 HW_REGISTER_RW( 0x7e102064 )
138 #define A2W_PLLH_DIG1_MASK 0x00ffffff
139 #define A2W_PLLH_DIG1_WIDTH 24
140 #define A2W_PLLH_DIG1_RESET 0000000000
141 #define A2W_PLLH_DIG2 HW_REGISTER_RW( 0x7e102068 )
142 #define A2W_PLLH_DIG2_MASK 0x00ffffff
143 #define A2W_PLLH_DIG2_WIDTH 24
144 #define A2W_PLLH_DIG2_RESET 0x000000aa
145 #define A2W_PLLH_DIG3 HW_REGISTER_RW( 0x7e10206c )
146 #define A2W_PLLH_DIG3_MASK 0x00ffffff
147 #define A2W_PLLH_DIG3_WIDTH 24
148 #define A2W_PLLH_DIG3_RESET 0000000000
149 #define A2W_PLLH_ANA0 HW_REGISTER_RW( 0x7e102070 )
150 #define A2W_PLLH_ANA0_MASK 0x00ffffff
151 #define A2W_PLLH_ANA0_WIDTH 24
152 #define A2W_PLLH_ANA0_RESET 0x00d80000
153 #define A2W_PLLH_ANA1 HW_REGISTER_RW( 0x7e102074 )
154 #define A2W_PLLH_ANA1_MASK 0x00ffffff
155 #define A2W_PLLH_ANA1_WIDTH 24
156 #define A2W_PLLH_ANA1_RESET 0x00000014
157 #define A2W_PLLH_ANA2 HW_REGISTER_RW( 0x7e102078 )
158 #define A2W_PLLH_ANA2_MASK 0x00ffffff
159 #define A2W_PLLH_ANA2_WIDTH 24
160 #define A2W_PLLH_ANA2_RESET 0000000000
161 #define A2W_PLLH_ANA3 HW_REGISTER_RW( 0x7e10207c )
162 #define A2W_PLLH_ANA3_MASK 0x00ffffff
163 #define A2W_PLLH_ANA3_WIDTH 24
164 #define A2W_PLLH_ANA3_RESET 0000000000
165 #define A2W_HDMI_CTL0 HW_REGISTER_RW( 0x7e102080 )
166 #define A2W_HDMI_CTL0_MASK 0x00ffffff
167 #define A2W_HDMI_CTL0_WIDTH 24
168 #define A2W_HDMI_CTL0_RESET 0x00470238
169 #define A2W_HDMI_CTL1 HW_REGISTER_RW( 0x7e102084 )
170 #define A2W_HDMI_CTL1_MASK 0x00ffffff
171 #define A2W_HDMI_CTL1_WIDTH 24
172 #define A2W_HDMI_CTL1_RESET 0x00011c00
173 #define A2W_HDMI_CTL2 HW_REGISTER_RW( 0x7e102088 )
174 #define A2W_HDMI_CTL2_MASK 0x00ffffff
175 #define A2W_HDMI_CTL2_WIDTH 24
176 #define A2W_HDMI_CTL2_RESET 0x0018048e
177 #define A2W_HDMI_CTL3 HW_REGISTER_RW( 0x7e10208c )
178 #define A2W_HDMI_CTL3_MASK 0x00ffffff
179 #define A2W_HDMI_CTL3_WIDTH 24
180 #define A2W_HDMI_CTL3_RESET 0x00000040
181 #define A2W_XOSC0 HW_REGISTER_RW( 0x7e102090 )
182 #define A2W_XOSC0_MASK 0x00ffffff
183 #define A2W_XOSC0_WIDTH 24
184 #define A2W_XOSC0_RESET 0x00820080
185 #define A2W_XOSC1 HW_REGISTER_RW( 0x7e102094 )
186 #define A2W_XOSC1_MASK 0x00ffffff
187 #define A2W_XOSC1_WIDTH 24
188 #define A2W_XOSC1_RESET 0x00000006
189 #define A2W_SMPS_CTLA0 HW_REGISTER_RW( 0x7e1020a0 )
190 #define A2W_SMPS_CTLA0_MASK 0x00ffffff
191 #define A2W_SMPS_CTLA0_WIDTH 24
192 #define A2W_SMPS_CTLA0_RESET 0000000000
193 #define A2W_SMPS_CTLA1 HW_REGISTER_RW( 0x7e1020a4 )
194 #define A2W_SMPS_CTLA1_MASK 0x00ffffff
195 #define A2W_SMPS_CTLA1_WIDTH 24
196 #define A2W_SMPS_CTLA1_RESET 0000000000
197 #define A2W_SMPS_CTLA2 HW_REGISTER_RW( 0x7e1020a8 )
198 #define A2W_SMPS_CTLA2_MASK 0x00ffffff
199 #define A2W_SMPS_CTLA2_WIDTH 24
200 #define A2W_SMPS_CTLA2_RESET 0000000000
201 #define A2W_SMPS_CTLB0 HW_REGISTER_RW( 0x7e1020b0 )
202 #define A2W_SMPS_CTLB0_MASK 0x00ffffff
203 #define A2W_SMPS_CTLB0_WIDTH 24
204 #define A2W_SMPS_CTLB0_RESET 0000000000
205 #define A2W_SMPS_CTLB1 HW_REGISTER_RW( 0x7e1020b4 )
206 #define A2W_SMPS_CTLB1_MASK 0x00ffffff
207 #define A2W_SMPS_CTLB1_WIDTH 24
208 #define A2W_SMPS_CTLB1_RESET 0000000000
209 #define A2W_SMPS_CTLB2 HW_REGISTER_RW( 0x7e1020b8 )
210 #define A2W_SMPS_CTLB2_MASK 0x00ffffff
211 #define A2W_SMPS_CTLB2_WIDTH 24
212 #define A2W_SMPS_CTLB2_RESET 0000000000
213 #define A2W_SMPS_CTLC0 HW_REGISTER_RW( 0x7e1020c0 )
214 #define A2W_SMPS_CTLC0_MASK 0x00ffffff
215 #define A2W_SMPS_CTLC0_WIDTH 24
216 #define A2W_SMPS_CTLC0_RESET 0000000000
217 #define A2W_SMPS_CTLC1 HW_REGISTER_RW( 0x7e1020c4 )
218 #define A2W_SMPS_CTLC1_MASK 0x00ffffff
219 #define A2W_SMPS_CTLC1_WIDTH 24
220 #define A2W_SMPS_CTLC1_RESET 0000000000
221 #define A2W_SMPS_CTLC2 HW_REGISTER_RW( 0x7e1020c8 )
222 #define A2W_SMPS_CTLC2_MASK 0x00ffffff
223 #define A2W_SMPS_CTLC2_WIDTH 24
224 #define A2W_SMPS_CTLC2_RESET 0000000000
225 #define A2W_SMPS_CTLC3 HW_REGISTER_RW( 0x7e1020cc )
226 #define A2W_SMPS_CTLC3_MASK 0x00ffffff
227 #define A2W_SMPS_CTLC3_WIDTH 24
228 #define A2W_SMPS_CTLC3_RESET 0000000000
229 #define A2W_SMPS_LDO0 HW_REGISTER_RW( 0x7e1020d0 )
230 #define A2W_SMPS_LDO0_MASK 0x00ffffff
231 #define A2W_SMPS_LDO0_WIDTH 24
232 #define A2W_SMPS_LDO0_RESET 0000000000
233 #define A2W_SMPS_LDO1 HW_REGISTER_RW( 0x7e1020d4 )
234 #define A2W_SMPS_LDO1_MASK 0x00ffffff
235 #define A2W_SMPS_LDO1_WIDTH 24
236 #define A2W_SMPS_LDO1_RESET 0000000000
237 #define A2W_PLLA_CTRL HW_REGISTER_RW( 0x7e102100 )
238 #define A2W_PLLA_CTRL_MASK 0x000373ff
239 #define A2W_PLLA_CTRL_WIDTH 18
240 #define A2W_PLLA_CTRL_RESET 0x00010000
241 #define A2W_PLLA_CTRL_PRSTN_BITS 17:17
242 #define A2W_PLLA_CTRL_PRSTN_SET 0x00020000
243 #define A2W_PLLA_CTRL_PRSTN_CLR 0xfffdffff
244 #define A2W_PLLA_CTRL_PRSTN_MSB 17
245 #define A2W_PLLA_CTRL_PRSTN_LSB 17
246 #define A2W_PLLA_CTRL_PWRDN_BITS 16:16
247 #define A2W_PLLA_CTRL_PWRDN_SET 0x00010000
248 #define A2W_PLLA_CTRL_PWRDN_CLR 0xfffeffff
249 #define A2W_PLLA_CTRL_PWRDN_MSB 16
250 #define A2W_PLLA_CTRL_PWRDN_LSB 16
251 #define A2W_PLLA_CTRL_PDIV_BITS 14:12
252 #define A2W_PLLA_CTRL_PDIV_SET 0x00007000
253 #define A2W_PLLA_CTRL_PDIV_CLR 0xffff8fff
254 #define A2W_PLLA_CTRL_PDIV_MSB 14
255 #define A2W_PLLA_CTRL_PDIV_LSB 12
256 #define A2W_PLLA_CTRL_NDIV_BITS 9:0
257 #define A2W_PLLA_CTRL_NDIV_SET 0x000003ff
258 #define A2W_PLLA_CTRL_NDIV_CLR 0xfffffc00
259 #define A2W_PLLA_CTRL_NDIV_MSB 9
260 #define A2W_PLLA_CTRL_NDIV_LSB 0
261 #define A2W_PLLA_FRAC HW_REGISTER_RW( 0x7e102200 )
262 #define A2W_PLLA_FRAC_MASK 0x000fffff
263 #define A2W_PLLA_FRAC_WIDTH 20
264 #define A2W_PLLA_FRAC_RESET 0000000000
265 #define A2W_PLLA_FRAC_FRAC_BITS 19:0
266 #define A2W_PLLA_FRAC_FRAC_SET 0x000fffff
267 #define A2W_PLLA_FRAC_FRAC_CLR 0xfff00000
268 #define A2W_PLLA_FRAC_FRAC_MSB 19
269 #define A2W_PLLA_FRAC_FRAC_LSB 0
270 #define A2W_PLLA_DSI0 HW_REGISTER_RW( 0x7e102300 )
271 #define A2W_PLLA_DSI0_MASK 0x000003ff
272 #define A2W_PLLA_DSI0_WIDTH 10
273 #define A2W_PLLA_DSI0_RESET 0x00000100
274 #define A2W_PLLA_DSI0_BYPEN_BITS 9:9
275 #define A2W_PLLA_DSI0_BYPEN_SET 0x00000200
276 #define A2W_PLLA_DSI0_BYPEN_CLR 0xfffffdff
277 #define A2W_PLLA_DSI0_BYPEN_MSB 9
278 #define A2W_PLLA_DSI0_BYPEN_LSB 9
279 #define A2W_PLLA_DSI0_CHENB_BITS 8:8
280 #define A2W_PLLA_DSI0_CHENB_SET 0x00000100
281 #define A2W_PLLA_DSI0_CHENB_CLR 0xfffffeff
282 #define A2W_PLLA_DSI0_CHENB_MSB 8
283 #define A2W_PLLA_DSI0_CHENB_LSB 8
284 #define A2W_PLLA_DSI0_DIV_BITS 7:0
285 #define A2W_PLLA_DSI0_DIV_SET 0x000000ff
286 #define A2W_PLLA_DSI0_DIV_CLR 0xffffff00
287 #define A2W_PLLA_DSI0_DIV_MSB 7
288 #define A2W_PLLA_DSI0_DIV_LSB 0
289 #define A2W_PLLA_CORE HW_REGISTER_RW( 0x7e102400 )
290 #define A2W_PLLA_CORE_MASK 0x000003ff
291 #define A2W_PLLA_CORE_WIDTH 10
292 #define A2W_PLLA_CORE_RESET 0x00000100
293 #define A2W_PLLA_CORE_BYPEN_BITS 9:9
294 #define A2W_PLLA_CORE_BYPEN_SET 0x00000200
295 #define A2W_PLLA_CORE_BYPEN_CLR 0xfffffdff
296 #define A2W_PLLA_CORE_BYPEN_MSB 9
297 #define A2W_PLLA_CORE_BYPEN_LSB 9
298 #define A2W_PLLA_CORE_CHENB_BITS 8:8
299 #define A2W_PLLA_CORE_CHENB_SET 0x00000100
300 #define A2W_PLLA_CORE_CHENB_CLR 0xfffffeff
301 #define A2W_PLLA_CORE_CHENB_MSB 8
302 #define A2W_PLLA_CORE_CHENB_LSB 8
303 #define A2W_PLLA_CORE_DIV_BITS 7:0
304 #define A2W_PLLA_CORE_DIV_SET 0x000000ff
305 #define A2W_PLLA_CORE_DIV_CLR 0xffffff00
306 #define A2W_PLLA_CORE_DIV_MSB 7
307 #define A2W_PLLA_CORE_DIV_LSB 0
308 #define A2W_PLLA_PER HW_REGISTER_RW( 0x7e102500 )
309 #define A2W_PLLA_PER_MASK 0x000003ff
310 #define A2W_PLLA_PER_WIDTH 10
311 #define A2W_PLLA_PER_RESET 0x00000100
312 #define A2W_PLLA_PER_BYPEN_BITS 9:9
313 #define A2W_PLLA_PER_BYPEN_SET 0x00000200
314 #define A2W_PLLA_PER_BYPEN_CLR 0xfffffdff
315 #define A2W_PLLA_PER_BYPEN_MSB 9
316 #define A2W_PLLA_PER_BYPEN_LSB 9
317 #define A2W_PLLA_PER_CHENB_BITS 8:8
318 #define A2W_PLLA_PER_CHENB_SET 0x00000100
319 #define A2W_PLLA_PER_CHENB_CLR 0xfffffeff
320 #define A2W_PLLA_PER_CHENB_MSB 8
321 #define A2W_PLLA_PER_CHENB_LSB 8
322 #define A2W_PLLA_PER_DIV_BITS 7:0
323 #define A2W_PLLA_PER_DIV_SET 0x000000ff
324 #define A2W_PLLA_PER_DIV_CLR 0xffffff00
325 #define A2W_PLLA_PER_DIV_MSB 7
326 #define A2W_PLLA_PER_DIV_LSB 0
327 #define A2W_PLLA_CCP2 HW_REGISTER_RW( 0x7e102600 )
328 #define A2W_PLLA_CCP2_MASK 0x000003ff
329 #define A2W_PLLA_CCP2_WIDTH 10
330 #define A2W_PLLA_CCP2_RESET 0x00000100
331 #define A2W_PLLA_CCP2_BYPEN_BITS 9:9
332 #define A2W_PLLA_CCP2_BYPEN_SET 0x00000200
333 #define A2W_PLLA_CCP2_BYPEN_CLR 0xfffffdff
334 #define A2W_PLLA_CCP2_BYPEN_MSB 9
335 #define A2W_PLLA_CCP2_BYPEN_LSB 9
336 #define A2W_PLLA_CCP2_CHENB_BITS 8:8
337 #define A2W_PLLA_CCP2_CHENB_SET 0x00000100
338 #define A2W_PLLA_CCP2_CHENB_CLR 0xfffffeff
339 #define A2W_PLLA_CCP2_CHENB_MSB 8
340 #define A2W_PLLA_CCP2_CHENB_LSB 8
341 #define A2W_PLLA_CCP2_DIV_BITS 7:0
342 #define A2W_PLLA_CCP2_DIV_SET 0x000000ff
343 #define A2W_PLLA_CCP2_DIV_CLR 0xffffff00
344 #define A2W_PLLA_CCP2_DIV_MSB 7
345 #define A2W_PLLA_CCP2_DIV_LSB 0
346 #define A2W_PLLB_CTRL HW_REGISTER_RW( 0x7e1021e0 )
347 #define A2W_PLLB_CTRL_MASK 0x000373ff
348 #define A2W_PLLB_CTRL_WIDTH 18
349 #define A2W_PLLB_CTRL_RESET 0x00010000
350 #define A2W_PLLB_CTRL_PRSTN_BITS 17:17
351 #define A2W_PLLB_CTRL_PRSTN_SET 0x00020000
352 #define A2W_PLLB_CTRL_PRSTN_CLR 0xfffdffff
353 #define A2W_PLLB_CTRL_PRSTN_MSB 17
354 #define A2W_PLLB_CTRL_PRSTN_LSB 17
355 #define A2W_PLLB_CTRL_PWRDN_BITS 16:16
356 #define A2W_PLLB_CTRL_PWRDN_SET 0x00010000
357 #define A2W_PLLB_CTRL_PWRDN_CLR 0xfffeffff
358 #define A2W_PLLB_CTRL_PWRDN_MSB 16
359 #define A2W_PLLB_CTRL_PWRDN_LSB 16
360 #define A2W_PLLB_CTRL_PDIV_BITS 14:12
361 #define A2W_PLLB_CTRL_PDIV_SET 0x00007000
362 #define A2W_PLLB_CTRL_PDIV_CLR 0xffff8fff
363 #define A2W_PLLB_CTRL_PDIV_MSB 14
364 #define A2W_PLLB_CTRL_PDIV_LSB 12
365 #define A2W_PLLB_CTRL_NDIV_BITS 9:0
366 #define A2W_PLLB_CTRL_NDIV_SET 0x000003ff
367 #define A2W_PLLB_CTRL_NDIV_CLR 0xfffffc00
368 #define A2W_PLLB_CTRL_NDIV_MSB 9
369 #define A2W_PLLB_CTRL_NDIV_LSB 0
370 #define A2W_PLLB_FRAC HW_REGISTER_RW( 0x7e1022e0 )
371 #define A2W_PLLB_FRAC_MASK 0x000fffff
372 #define A2W_PLLB_FRAC_WIDTH 20
373 #define A2W_PLLB_FRAC_RESET 0000000000
374 #define A2W_PLLB_FRAC_FRAC_BITS 19:0
375 #define A2W_PLLB_FRAC_FRAC_SET 0x000fffff
376 #define A2W_PLLB_FRAC_FRAC_CLR 0xfff00000
377 #define A2W_PLLB_FRAC_FRAC_MSB 19
378 #define A2W_PLLB_FRAC_FRAC_LSB 0
379 #define A2W_PLLB_ARM HW_REGISTER_RW( 0x7e1023e0 )
380 #define A2W_PLLB_ARM_MASK 0x000003ff
381 #define A2W_PLLB_ARM_WIDTH 10
382 #define A2W_PLLB_ARM_RESET 0x00000100
383 #define A2W_PLLB_ARM_BYPEN_BITS 9:9
384 #define A2W_PLLB_ARM_BYPEN_SET 0x00000200
385 #define A2W_PLLB_ARM_BYPEN_CLR 0xfffffdff
386 #define A2W_PLLB_ARM_BYPEN_MSB 9
387 #define A2W_PLLB_ARM_BYPEN_LSB 9
388 #define A2W_PLLB_ARM_CHENB_BITS 8:8
389 #define A2W_PLLB_ARM_CHENB_SET 0x00000100
390 #define A2W_PLLB_ARM_CHENB_CLR 0xfffffeff
391 #define A2W_PLLB_ARM_CHENB_MSB 8
392 #define A2W_PLLB_ARM_CHENB_LSB 8
393 #define A2W_PLLB_ARM_DIV_BITS 7:0
394 #define A2W_PLLB_ARM_DIV_SET 0x000000ff
395 #define A2W_PLLB_ARM_DIV_CLR 0xffffff00
396 #define A2W_PLLB_ARM_DIV_MSB 7
397 #define A2W_PLLB_ARM_DIV_LSB 0
398 #define A2W_PLLB_SP0 HW_REGISTER_RW( 0x7e1024e0 )
399 #define A2W_PLLB_SP0_MASK 0x000003ff
400 #define A2W_PLLB_SP0_WIDTH 10
401 #define A2W_PLLB_SP0_RESET 0x00000100
402 #define A2W_PLLB_SP0_BYPEN_BITS 9:9
403 #define A2W_PLLB_SP0_BYPEN_SET 0x00000200
404 #define A2W_PLLB_SP0_BYPEN_CLR 0xfffffdff
405 #define A2W_PLLB_SP0_BYPEN_MSB 9
406 #define A2W_PLLB_SP0_BYPEN_LSB 9
407 #define A2W_PLLB_SP0_CHENB_BITS 8:8
408 #define A2W_PLLB_SP0_CHENB_SET 0x00000100
409 #define A2W_PLLB_SP0_CHENB_CLR 0xfffffeff
410 #define A2W_PLLB_SP0_CHENB_MSB 8
411 #define A2W_PLLB_SP0_CHENB_LSB 8
412 #define A2W_PLLB_SP0_DIV_BITS 7:0
413 #define A2W_PLLB_SP0_DIV_SET 0x000000ff
414 #define A2W_PLLB_SP0_DIV_CLR 0xffffff00
415 #define A2W_PLLB_SP0_DIV_MSB 7
416 #define A2W_PLLB_SP0_DIV_LSB 0
417 #define A2W_PLLB_SP1 HW_REGISTER_RW( 0x7e1025e0 )
418 #define A2W_PLLB_SP1_MASK 0x000003ff
419 #define A2W_PLLB_SP1_WIDTH 10
420 #define A2W_PLLB_SP1_RESET 0x00000100
421 #define A2W_PLLB_SP1_BYPEN_BITS 9:9
422 #define A2W_PLLB_SP1_BYPEN_SET 0x00000200
423 #define A2W_PLLB_SP1_BYPEN_CLR 0xfffffdff
424 #define A2W_PLLB_SP1_BYPEN_MSB 9
425 #define A2W_PLLB_SP1_BYPEN_LSB 9
426 #define A2W_PLLB_SP1_CHENB_BITS 8:8
427 #define A2W_PLLB_SP1_CHENB_SET 0x00000100
428 #define A2W_PLLB_SP1_CHENB_CLR 0xfffffeff
429 #define A2W_PLLB_SP1_CHENB_MSB 8
430 #define A2W_PLLB_SP1_CHENB_LSB 8
431 #define A2W_PLLB_SP1_DIV_BITS 7:0
432 #define A2W_PLLB_SP1_DIV_SET 0x000000ff
433 #define A2W_PLLB_SP1_DIV_CLR 0xffffff00
434 #define A2W_PLLB_SP1_DIV_MSB 7
435 #define A2W_PLLB_SP1_DIV_LSB 0
436 #define A2W_PLLB_SP2 HW_REGISTER_RW( 0x7e1026e0 )
437 #define A2W_PLLB_SP2_MASK 0x000003ff
438 #define A2W_PLLB_SP2_WIDTH 10
439 #define A2W_PLLB_SP2_RESET 0x00000100
440 #define A2W_PLLB_SP2_BYPEN_BITS 9:9
441 #define A2W_PLLB_SP2_BYPEN_SET 0x00000200
442 #define A2W_PLLB_SP2_BYPEN_CLR 0xfffffdff
443 #define A2W_PLLB_SP2_BYPEN_MSB 9
444 #define A2W_PLLB_SP2_BYPEN_LSB 9
445 #define A2W_PLLB_SP2_CHENB_BITS 8:8
446 #define A2W_PLLB_SP2_CHENB_SET 0x00000100
447 #define A2W_PLLB_SP2_CHENB_CLR 0xfffffeff
448 #define A2W_PLLB_SP2_CHENB_MSB 8
449 #define A2W_PLLB_SP2_CHENB_LSB 8
450 #define A2W_PLLB_SP2_DIV_BITS 7:0
451 #define A2W_PLLB_SP2_DIV_SET 0x000000ff
452 #define A2W_PLLB_SP2_DIV_CLR 0xffffff00
453 #define A2W_PLLB_SP2_DIV_MSB 7
454 #define A2W_PLLB_SP2_DIV_LSB 0
455 #define A2W_PLLC_CTRL HW_REGISTER_RW( 0x7e102120 )
456 #define A2W_PLLC_CTRL_MASK 0x000373ff
457 #define A2W_PLLC_CTRL_WIDTH 18
458 #define A2W_PLLC_CTRL_RESET 0x00010000
459 #define A2W_PLLC_CTRL_PRSTN_BITS 17:17
460 #define A2W_PLLC_CTRL_PRSTN_SET 0x00020000
461 #define A2W_PLLC_CTRL_PRSTN_CLR 0xfffdffff
462 #define A2W_PLLC_CTRL_PRSTN_MSB 17
463 #define A2W_PLLC_CTRL_PRSTN_LSB 17
464 #define A2W_PLLC_CTRL_PWRDN_BITS 16:16
465 #define A2W_PLLC_CTRL_PWRDN_SET 0x00010000
466 #define A2W_PLLC_CTRL_PWRDN_CLR 0xfffeffff
467 #define A2W_PLLC_CTRL_PWRDN_MSB 16
468 #define A2W_PLLC_CTRL_PWRDN_LSB 16
469 #define A2W_PLLC_CTRL_PDIV_BITS 14:12
470 #define A2W_PLLC_CTRL_PDIV_SET 0x00007000
471 #define A2W_PLLC_CTRL_PDIV_CLR 0xffff8fff
472 #define A2W_PLLC_CTRL_PDIV_MSB 14
473 #define A2W_PLLC_CTRL_PDIV_LSB 12
474 #define A2W_PLLC_CTRL_NDIV_BITS 9:0
475 #define A2W_PLLC_CTRL_NDIV_SET 0x000003ff
476 #define A2W_PLLC_CTRL_NDIV_CLR 0xfffffc00
477 #define A2W_PLLC_CTRL_NDIV_MSB 9
478 #define A2W_PLLC_CTRL_NDIV_LSB 0
479 #define A2W_PLLC_FRAC HW_REGISTER_RW( 0x7e102220 )
480 #define A2W_PLLC_FRAC_MASK 0x000fffff
481 #define A2W_PLLC_FRAC_WIDTH 20
482 #define A2W_PLLC_FRAC_RESET 0000000000
483 #define A2W_PLLC_FRAC_FRAC_BITS 19:0
484 #define A2W_PLLC_FRAC_FRAC_SET 0x000fffff
485 #define A2W_PLLC_FRAC_FRAC_CLR 0xfff00000
486 #define A2W_PLLC_FRAC_FRAC_MSB 19
487 #define A2W_PLLC_FRAC_FRAC_LSB 0
488 #define A2W_PLLC_CORE2 HW_REGISTER_RW( 0x7e102320 )
489 #define A2W_PLLC_CORE2_MASK 0x000003ff
490 #define A2W_PLLC_CORE2_WIDTH 10
491 #define A2W_PLLC_CORE2_RESET 0x00000100
492 #define A2W_PLLC_CORE2_BYPEN_BITS 9:9
493 #define A2W_PLLC_CORE2_BYPEN_SET 0x00000200
494 #define A2W_PLLC_CORE2_BYPEN_CLR 0xfffffdff
495 #define A2W_PLLC_CORE2_BYPEN_MSB 9
496 #define A2W_PLLC_CORE2_BYPEN_LSB 9
497 #define A2W_PLLC_CORE2_CHENB_BITS 8:8
498 #define A2W_PLLC_CORE2_CHENB_SET 0x00000100
499 #define A2W_PLLC_CORE2_CHENB_CLR 0xfffffeff
500 #define A2W_PLLC_CORE2_CHENB_MSB 8
501 #define A2W_PLLC_CORE2_CHENB_LSB 8
502 #define A2W_PLLC_CORE2_DIV_BITS 7:0
503 #define A2W_PLLC_CORE2_DIV_SET 0x000000ff
504 #define A2W_PLLC_CORE2_DIV_CLR 0xffffff00
505 #define A2W_PLLC_CORE2_DIV_MSB 7
506 #define A2W_PLLC_CORE2_DIV_LSB 0
507 #define A2W_PLLC_CORE1 HW_REGISTER_RW( 0x7e102420 )
508 #define A2W_PLLC_CORE1_MASK 0x000003ff
509 #define A2W_PLLC_CORE1_WIDTH 10
510 #define A2W_PLLC_CORE1_RESET 0x00000100
511 #define A2W_PLLC_CORE1_BYPEN_BITS 9:9
512 #define A2W_PLLC_CORE1_BYPEN_SET 0x00000200
513 #define A2W_PLLC_CORE1_BYPEN_CLR 0xfffffdff
514 #define A2W_PLLC_CORE1_BYPEN_MSB 9
515 #define A2W_PLLC_CORE1_BYPEN_LSB 9
516 #define A2W_PLLC_CORE1_CHENB_BITS 8:8
517 #define A2W_PLLC_CORE1_CHENB_SET 0x00000100
518 #define A2W_PLLC_CORE1_CHENB_CLR 0xfffffeff
519 #define A2W_PLLC_CORE1_CHENB_MSB 8
520 #define A2W_PLLC_CORE1_CHENB_LSB 8
521 #define A2W_PLLC_CORE1_DIV_BITS 7:0
522 #define A2W_PLLC_CORE1_DIV_SET 0x000000ff
523 #define A2W_PLLC_CORE1_DIV_CLR 0xffffff00
524 #define A2W_PLLC_CORE1_DIV_MSB 7
525 #define A2W_PLLC_CORE1_DIV_LSB 0
526 #define A2W_PLLC_PER HW_REGISTER_RW( 0x7e102520 )
527 #define A2W_PLLC_PER_MASK 0x000003ff
528 #define A2W_PLLC_PER_WIDTH 10
529 #define A2W_PLLC_PER_RESET 0x00000100
530 #define A2W_PLLC_PER_BYPEN_BITS 9:9
531 #define A2W_PLLC_PER_BYPEN_SET 0x00000200
532 #define A2W_PLLC_PER_BYPEN_CLR 0xfffffdff
533 #define A2W_PLLC_PER_BYPEN_MSB 9
534 #define A2W_PLLC_PER_BYPEN_LSB 9
535 #define A2W_PLLC_PER_CHENB_BITS 8:8
536 #define A2W_PLLC_PER_CHENB_SET 0x00000100
537 #define A2W_PLLC_PER_CHENB_CLR 0xfffffeff
538 #define A2W_PLLC_PER_CHENB_MSB 8
539 #define A2W_PLLC_PER_CHENB_LSB 8
540 #define A2W_PLLC_PER_DIV_BITS 7:0
541 #define A2W_PLLC_PER_DIV_SET 0x000000ff
542 #define A2W_PLLC_PER_DIV_CLR 0xffffff00
543 #define A2W_PLLC_PER_DIV_MSB 7
544 #define A2W_PLLC_PER_DIV_LSB 0
545 #define A2W_PLLC_CORE0 HW_REGISTER_RW( 0x7e102620 )
546 #define A2W_PLLC_CORE0_MASK 0x000003ff
547 #define A2W_PLLC_CORE0_WIDTH 10
548 #define A2W_PLLC_CORE0_RESET 0x00000100
549 #define A2W_PLLC_CORE0_BYPEN_BITS 9:9
550 #define A2W_PLLC_CORE0_BYPEN_SET 0x00000200
551 #define A2W_PLLC_CORE0_BYPEN_CLR 0xfffffdff
552 #define A2W_PLLC_CORE0_BYPEN_MSB 9
553 #define A2W_PLLC_CORE0_BYPEN_LSB 9
554 #define A2W_PLLC_CORE0_CHENB_BITS 8:8
555 #define A2W_PLLC_CORE0_CHENB_SET 0x00000100
556 #define A2W_PLLC_CORE0_CHENB_CLR 0xfffffeff
557 #define A2W_PLLC_CORE0_CHENB_MSB 8
558 #define A2W_PLLC_CORE0_CHENB_LSB 8
559 #define A2W_PLLC_CORE0_DIV_BITS 7:0
560 #define A2W_PLLC_CORE0_DIV_SET 0x000000ff
561 #define A2W_PLLC_CORE0_DIV_CLR 0xffffff00
562 #define A2W_PLLC_CORE0_DIV_MSB 7
563 #define A2W_PLLC_CORE0_DIV_LSB 0
564 #define A2W_PLLD_CTRL HW_REGISTER_RW( 0x7e102140 )
565 #define A2W_PLLD_CTRL_MASK 0x000373ff
566 #define A2W_PLLD_CTRL_WIDTH 18
567 #define A2W_PLLD_CTRL_RESET 0x00010000
568 #define A2W_PLLD_CTRL_PRSTN_BITS 17:17
569 #define A2W_PLLD_CTRL_PRSTN_SET 0x00020000
570 #define A2W_PLLD_CTRL_PRSTN_CLR 0xfffdffff
571 #define A2W_PLLD_CTRL_PRSTN_MSB 17
572 #define A2W_PLLD_CTRL_PRSTN_LSB 17
573 #define A2W_PLLD_CTRL_PWRDN_BITS 16:16
574 #define A2W_PLLD_CTRL_PWRDN_SET 0x00010000
575 #define A2W_PLLD_CTRL_PWRDN_CLR 0xfffeffff
576 #define A2W_PLLD_CTRL_PWRDN_MSB 16
577 #define A2W_PLLD_CTRL_PWRDN_LSB 16
578 #define A2W_PLLD_CTRL_PDIV_BITS 14:12
579 #define A2W_PLLD_CTRL_PDIV_SET 0x00007000
580 #define A2W_PLLD_CTRL_PDIV_CLR 0xffff8fff
581 #define A2W_PLLD_CTRL_PDIV_MSB 14
582 #define A2W_PLLD_CTRL_PDIV_LSB 12
583 #define A2W_PLLD_CTRL_NDIV_BITS 9:0
584 #define A2W_PLLD_CTRL_NDIV_SET 0x000003ff
585 #define A2W_PLLD_CTRL_NDIV_CLR 0xfffffc00
586 #define A2W_PLLD_CTRL_NDIV_MSB 9
587 #define A2W_PLLD_CTRL_NDIV_LSB 0
588 #define A2W_PLLD_FRAC HW_REGISTER_RW( 0x7e102240 )
589 #define A2W_PLLD_FRAC_MASK 0x000fffff
590 #define A2W_PLLD_FRAC_WIDTH 20
591 #define A2W_PLLD_FRAC_RESET 0000000000
592 #define A2W_PLLD_FRAC_FRAC_BITS 19:0
593 #define A2W_PLLD_FRAC_FRAC_SET 0x000fffff
594 #define A2W_PLLD_FRAC_FRAC_CLR 0xfff00000
595 #define A2W_PLLD_FRAC_FRAC_MSB 19
596 #define A2W_PLLD_FRAC_FRAC_LSB 0
597 #define A2W_PLLD_DSI0 HW_REGISTER_RW( 0x7e102340 )
598 #define A2W_PLLD_DSI0_MASK 0x000003ff
599 #define A2W_PLLD_DSI0_WIDTH 10
600 #define A2W_PLLD_DSI0_RESET 0x00000100
601 #define A2W_PLLD_DSI0_BYPEN_BITS 9:9
602 #define A2W_PLLD_DSI0_BYPEN_SET 0x00000200
603 #define A2W_PLLD_DSI0_BYPEN_CLR 0xfffffdff
604 #define A2W_PLLD_DSI0_BYPEN_MSB 9
605 #define A2W_PLLD_DSI0_BYPEN_LSB 9
606 #define A2W_PLLD_DSI0_CHENB_BITS 8:8
607 #define A2W_PLLD_DSI0_CHENB_SET 0x00000100
608 #define A2W_PLLD_DSI0_CHENB_CLR 0xfffffeff
609 #define A2W_PLLD_DSI0_CHENB_MSB 8
610 #define A2W_PLLD_DSI0_CHENB_LSB 8
611 #define A2W_PLLD_DSI0_DIV_BITS 7:0
612 #define A2W_PLLD_DSI0_DIV_SET 0x000000ff
613 #define A2W_PLLD_DSI0_DIV_CLR 0xffffff00
614 #define A2W_PLLD_DSI0_DIV_MSB 7
615 #define A2W_PLLD_DSI0_DIV_LSB 0
616 #define A2W_PLLD_CORE HW_REGISTER_RW( 0x7e102440 )
617 #define A2W_PLLD_CORE_MASK 0x000003ff
618 #define A2W_PLLD_CORE_WIDTH 10
619 #define A2W_PLLD_CORE_RESET 0x00000100
620 #define A2W_PLLD_CORE_BYPEN_BITS 9:9
621 #define A2W_PLLD_CORE_BYPEN_SET 0x00000200
622 #define A2W_PLLD_CORE_BYPEN_CLR 0xfffffdff
623 #define A2W_PLLD_CORE_BYPEN_MSB 9
624 #define A2W_PLLD_CORE_BYPEN_LSB 9
625 #define A2W_PLLD_CORE_CHENB_BITS 8:8
626 #define A2W_PLLD_CORE_CHENB_SET 0x00000100
627 #define A2W_PLLD_CORE_CHENB_CLR 0xfffffeff
628 #define A2W_PLLD_CORE_CHENB_MSB 8
629 #define A2W_PLLD_CORE_CHENB_LSB 8
630 #define A2W_PLLD_CORE_DIV_BITS 7:0
631 #define A2W_PLLD_CORE_DIV_SET 0x000000ff
632 #define A2W_PLLD_CORE_DIV_CLR 0xffffff00
633 #define A2W_PLLD_CORE_DIV_MSB 7
634 #define A2W_PLLD_CORE_DIV_LSB 0
635 #define A2W_PLLD_PER HW_REGISTER_RW( 0x7e102540 )
636 #define A2W_PLLD_PER_MASK 0x000003ff
637 #define A2W_PLLD_PER_WIDTH 10
638 #define A2W_PLLD_PER_RESET 0x00000100
639 #define A2W_PLLD_PER_BYPEN_BITS 9:9
640 #define A2W_PLLD_PER_BYPEN_SET 0x00000200
641 #define A2W_PLLD_PER_BYPEN_CLR 0xfffffdff
642 #define A2W_PLLD_PER_BYPEN_MSB 9
643 #define A2W_PLLD_PER_BYPEN_LSB 9
644 #define A2W_PLLD_PER_CHENB_BITS 8:8
645 #define A2W_PLLD_PER_CHENB_SET 0x00000100
646 #define A2W_PLLD_PER_CHENB_CLR 0xfffffeff
647 #define A2W_PLLD_PER_CHENB_MSB 8
648 #define A2W_PLLD_PER_CHENB_LSB 8
649 #define A2W_PLLD_PER_DIV_BITS 7:0
650 #define A2W_PLLD_PER_DIV_SET 0x000000ff
651 #define A2W_PLLD_PER_DIV_CLR 0xffffff00
652 #define A2W_PLLD_PER_DIV_MSB 7
653 #define A2W_PLLD_PER_DIV_LSB 0
654 #define A2W_PLLD_DSI1 HW_REGISTER_RW( 0x7e102640 )
655 #define A2W_PLLD_DSI1_MASK 0x000003ff
656 #define A2W_PLLD_DSI1_WIDTH 10
657 #define A2W_PLLD_DSI1_RESET 0x00000100
658 #define A2W_PLLD_DSI1_BYPEN_BITS 9:9
659 #define A2W_PLLD_DSI1_BYPEN_SET 0x00000200
660 #define A2W_PLLD_DSI1_BYPEN_CLR 0xfffffdff
661 #define A2W_PLLD_DSI1_BYPEN_MSB 9
662 #define A2W_PLLD_DSI1_BYPEN_LSB 9
663 #define A2W_PLLD_DSI1_CHENB_BITS 8:8
664 #define A2W_PLLD_DSI1_CHENB_SET 0x00000100
665 #define A2W_PLLD_DSI1_CHENB_CLR 0xfffffeff
666 #define A2W_PLLD_DSI1_CHENB_MSB 8
667 #define A2W_PLLD_DSI1_CHENB_LSB 8
668 #define A2W_PLLD_DSI1_DIV_BITS 7:0
669 #define A2W_PLLD_DSI1_DIV_SET 0x000000ff
670 #define A2W_PLLD_DSI1_DIV_CLR 0xffffff00
671 #define A2W_PLLD_DSI1_DIV_MSB 7
672 #define A2W_PLLD_DSI1_DIV_LSB 0
673 #define A2W_PLLH_CTRL HW_REGISTER_RW( 0x7e102160 )
674 #define A2W_PLLH_CTRL_MASK 0x000370ff
675 #define A2W_PLLH_CTRL_WIDTH 18
676 #define A2W_PLLH_CTRL_RESET 0x00010000
677 #define A2W_PLLH_CTRL_PRSTN_BITS 17:17
678 #define A2W_PLLH_CTRL_PRSTN_SET 0x00020000
679 #define A2W_PLLH_CTRL_PRSTN_CLR 0xfffdffff
680 #define A2W_PLLH_CTRL_PRSTN_MSB 17
681 #define A2W_PLLH_CTRL_PRSTN_LSB 17
682 #define A2W_PLLH_CTRL_PWRDN_BITS 16:16
683 #define A2W_PLLH_CTRL_PWRDN_SET 0x00010000
684 #define A2W_PLLH_CTRL_PWRDN_CLR 0xfffeffff
685 #define A2W_PLLH_CTRL_PWRDN_MSB 16
686 #define A2W_PLLH_CTRL_PWRDN_LSB 16
687 #define A2W_PLLH_CTRL_PDIV_BITS 14:12
688 #define A2W_PLLH_CTRL_PDIV_SET 0x00007000
689 #define A2W_PLLH_CTRL_PDIV_CLR 0xffff8fff
690 #define A2W_PLLH_CTRL_PDIV_MSB 14
691 #define A2W_PLLH_CTRL_PDIV_LSB 12
692 #define A2W_PLLH_CTRL_NDIV_BITS 7:0
693 #define A2W_PLLH_CTRL_NDIV_SET 0x000000ff
694 #define A2W_PLLH_CTRL_NDIV_CLR 0xffffff00
695 #define A2W_PLLH_CTRL_NDIV_MSB 7
696 #define A2W_PLLH_CTRL_NDIV_LSB 0
697 #define A2W_PLLH_FRAC HW_REGISTER_RW( 0x7e102260 )
698 #define A2W_PLLH_FRAC_MASK 0x000fffff
699 #define A2W_PLLH_FRAC_WIDTH 20
700 #define A2W_PLLH_FRAC_RESET 0000000000
701 #define A2W_PLLH_FRAC_FRAC_BITS 19:0
702 #define A2W_PLLH_FRAC_FRAC_SET 0x000fffff
703 #define A2W_PLLH_FRAC_FRAC_CLR 0xfff00000
704 #define A2W_PLLH_FRAC_FRAC_MSB 19
705 #define A2W_PLLH_FRAC_FRAC_LSB 0
706 #define A2W_PLLH_AUX HW_REGISTER_RW( 0x7e102360 )
707 #define A2W_PLLH_AUX_MASK 0x000003ff
708 #define A2W_PLLH_AUX_WIDTH 10
709 #define A2W_PLLH_AUX_RESET 0x00000100
710 #define A2W_PLLH_AUX_BYPEN_BITS 9:9
711 #define A2W_PLLH_AUX_BYPEN_SET 0x00000200
712 #define A2W_PLLH_AUX_BYPEN_CLR 0xfffffdff
713 #define A2W_PLLH_AUX_BYPEN_MSB 9
714 #define A2W_PLLH_AUX_BYPEN_LSB 9
715 #define A2W_PLLH_AUX_CHENB_BITS 8:8
716 #define A2W_PLLH_AUX_CHENB_SET 0x00000100
717 #define A2W_PLLH_AUX_CHENB_CLR 0xfffffeff
718 #define A2W_PLLH_AUX_CHENB_MSB 8
719 #define A2W_PLLH_AUX_CHENB_LSB 8
720 #define A2W_PLLH_AUX_DIV_BITS 7:0
721 #define A2W_PLLH_AUX_DIV_SET 0x000000ff
722 #define A2W_PLLH_AUX_DIV_CLR 0xffffff00
723 #define A2W_PLLH_AUX_DIV_MSB 7
724 #define A2W_PLLH_AUX_DIV_LSB 0
725 #define A2W_PLLH_RCAL HW_REGISTER_RW( 0x7e102460 )
726 #define A2W_PLLH_RCAL_MASK 0x000003ff
727 #define A2W_PLLH_RCAL_WIDTH 10
728 #define A2W_PLLH_RCAL_RESET 0x00000100
729 #define A2W_PLLH_RCAL_BYPEN_BITS 9:9
730 #define A2W_PLLH_RCAL_BYPEN_SET 0x00000200
731 #define A2W_PLLH_RCAL_BYPEN_CLR 0xfffffdff
732 #define A2W_PLLH_RCAL_BYPEN_MSB 9
733 #define A2W_PLLH_RCAL_BYPEN_LSB 9
734 #define A2W_PLLH_RCAL_CHENB_BITS 8:8
735 #define A2W_PLLH_RCAL_CHENB_SET 0x00000100
736 #define A2W_PLLH_RCAL_CHENB_CLR 0xfffffeff
737 #define A2W_PLLH_RCAL_CHENB_MSB 8
738 #define A2W_PLLH_RCAL_CHENB_LSB 8
739 #define A2W_PLLH_RCAL_DIV_BITS 7:0
740 #define A2W_PLLH_RCAL_DIV_SET 0x000000ff
741 #define A2W_PLLH_RCAL_DIV_CLR 0xffffff00
742 #define A2W_PLLH_RCAL_DIV_MSB 7
743 #define A2W_PLLH_RCAL_DIV_LSB 0
744 #define A2W_PLLH_PIX HW_REGISTER_RW( 0x7e102560 )
745 #define A2W_PLLH_PIX_MASK 0x000003ff
746 #define A2W_PLLH_PIX_WIDTH 10
747 #define A2W_PLLH_PIX_RESET 0x00000100
748 #define A2W_PLLH_PIX_BYPEN_BITS 9:9
749 #define A2W_PLLH_PIX_BYPEN_SET 0x00000200
750 #define A2W_PLLH_PIX_BYPEN_CLR 0xfffffdff
751 #define A2W_PLLH_PIX_BYPEN_MSB 9
752 #define A2W_PLLH_PIX_BYPEN_LSB 9
753 #define A2W_PLLH_PIX_CHENB_BITS 8:8
754 #define A2W_PLLH_PIX_CHENB_SET 0x00000100
755 #define A2W_PLLH_PIX_CHENB_CLR 0xfffffeff
756 #define A2W_PLLH_PIX_CHENB_MSB 8
757 #define A2W_PLLH_PIX_CHENB_LSB 8
758 #define A2W_PLLH_PIX_DIV_BITS 7:0
759 #define A2W_PLLH_PIX_DIV_SET 0x000000ff
760 #define A2W_PLLH_PIX_DIV_CLR 0xffffff00
761 #define A2W_PLLH_PIX_DIV_MSB 7
762 #define A2W_PLLH_PIX_DIV_LSB 0
763 #define A2W_SMPS_A_MODE HW_REGISTER_RW( 0x7e1021a0 )
764 #define A2W_SMPS_A_MODE_MASK 0x00000001
765 #define A2W_SMPS_A_MODE_WIDTH 1
766 #define A2W_SMPS_A_MODE_RESET 0000000000
767 #define A2W_SMPS_A_MODE_BSTPWMB_BITS 0:0
768 #define A2W_SMPS_A_MODE_BSTPWMB_SET 0x00000001
769 #define A2W_SMPS_A_MODE_BSTPWMB_CLR 0xfffffffe
770 #define A2W_SMPS_A_MODE_BSTPWMB_MSB 0
771 #define A2W_SMPS_A_MODE_BSTPWMB_LSB 0
772 #define A2W_SMPS_A_VOLTS HW_REGISTER_RW( 0x7e1022a0 )
773 #define A2W_SMPS_A_VOLTS_MASK 0x0000001f
774 #define A2W_SMPS_A_VOLTS_WIDTH 5
775 #define A2W_SMPS_A_VOLTS_RESET 0000000000
776 #define A2W_SMPS_A_VOLTS_VOLTS_BITS 4:0
777 #define A2W_SMPS_A_VOLTS_VOLTS_SET 0x0000001f
778 #define A2W_SMPS_A_VOLTS_VOLTS_CLR 0xffffffe0
779 #define A2W_SMPS_A_VOLTS_VOLTS_MSB 4
780 #define A2W_SMPS_A_VOLTS_VOLTS_LSB 0
781 #define A2W_SMPS_A_GAIN HW_REGISTER_RW( 0x7e1023a0 )
782 #define A2W_SMPS_A_GAIN_MASK 0x00000007
783 #define A2W_SMPS_A_GAIN_WIDTH 3
784 #define A2W_SMPS_A_GAIN_RESET 0000000000
785 #define A2W_SMPS_A_GAIN_DIGGAIN_BITS 2:0
786 #define A2W_SMPS_A_GAIN_DIGGAIN_SET 0x00000007
787 #define A2W_SMPS_A_GAIN_DIGGAIN_CLR 0xfffffff8
788 #define A2W_SMPS_A_GAIN_DIGGAIN_MSB 2
789 #define A2W_SMPS_A_GAIN_DIGGAIN_LSB 0
790 #define A2W_SMPS_B_STAT HW_REGISTER_RW( 0x7e1021b0 )
791 #define A2W_SMPS_B_STAT_MASK 0x0000111f
792 #define A2W_SMPS_B_STAT_WIDTH 13
793 #define A2W_SMPS_B_STAT_RESET 0000000000
794 #define A2W_SMPS_B_STAT_POK_BITS 12:12
795 #define A2W_SMPS_B_STAT_POK_SET 0x00001000
796 #define A2W_SMPS_B_STAT_POK_CLR 0xffffefff
797 #define A2W_SMPS_B_STAT_POK_MSB 12
798 #define A2W_SMPS_B_STAT_POK_LSB 12
799 #define A2W_SMPS_B_STAT_BSTPWMB_BITS 8:8
800 #define A2W_SMPS_B_STAT_BSTPWMB_SET 0x00000100
801 #define A2W_SMPS_B_STAT_BSTPWMB_CLR 0xfffffeff
802 #define A2W_SMPS_B_STAT_BSTPWMB_MSB 8
803 #define A2W_SMPS_B_STAT_BSTPWMB_LSB 8
804 #define A2W_SMPS_B_STAT_VOLTS_BITS 4:0
805 #define A2W_SMPS_B_STAT_VOLTS_SET 0x0000001f
806 #define A2W_SMPS_B_STAT_VOLTS_CLR 0xffffffe0
807 #define A2W_SMPS_B_STAT_VOLTS_MSB 4
808 #define A2W_SMPS_B_STAT_VOLTS_LSB 0
809 #define A2W_SMPS_C_CLK HW_REGISTER_RW( 0x7e1021c0 )
810 #define A2W_SMPS_C_CLK_MASK 0x0000000f
811 #define A2W_SMPS_C_CLK_WIDTH 4
812 #define A2W_SMPS_C_CLK_RESET 0000000000
813 #define A2W_SMPS_C_CLK_TDEN_BITS 3:3
814 #define A2W_SMPS_C_CLK_TDEN_SET 0x00000008
815 #define A2W_SMPS_C_CLK_TDEN_CLR 0xfffffff7
816 #define A2W_SMPS_C_CLK_TDEN_MSB 3
817 #define A2W_SMPS_C_CLK_TDEN_LSB 3
818 #define A2W_SMPS_C_CLK_USEOSC_BITS 2:2
819 #define A2W_SMPS_C_CLK_USEOSC_SET 0x00000004
820 #define A2W_SMPS_C_CLK_USEOSC_CLR 0xfffffffb
821 #define A2W_SMPS_C_CLK_USEOSC_MSB 2
822 #define A2W_SMPS_C_CLK_USEOSC_LSB 2
823 #define A2W_SMPS_C_CLK_OSCDIV_BITS 1:0
824 #define A2W_SMPS_C_CLK_OSCDIV_SET 0x00000003
825 #define A2W_SMPS_C_CLK_OSCDIV_CLR 0xfffffffc
826 #define A2W_SMPS_C_CLK_OSCDIV_MSB 1
827 #define A2W_SMPS_C_CLK_OSCDIV_LSB 0
828 #define A2W_SMPS_C_CTL HW_REGISTER_RW( 0x7e1022c0 )
829 #define A2W_SMPS_C_CTL_MASK 0x00000003
830 #define A2W_SMPS_C_CTL_WIDTH 2
831 #define A2W_SMPS_C_CTL_RESET 0000000000
832 #define A2W_SMPS_C_CTL_UPEN_BITS 1:1
833 #define A2W_SMPS_C_CTL_UPEN_SET 0x00000002
834 #define A2W_SMPS_C_CTL_UPEN_CLR 0xfffffffd
835 #define A2W_SMPS_C_CTL_UPEN_MSB 1
836 #define A2W_SMPS_C_CTL_UPEN_LSB 1
837 #define A2W_SMPS_C_CTL_CTRLEN_BITS 0:0
838 #define A2W_SMPS_C_CTL_CTRLEN_SET 0x00000001
839 #define A2W_SMPS_C_CTL_CTRLEN_CLR 0xfffffffe
840 #define A2W_SMPS_C_CTL_CTRLEN_MSB 0
841 #define A2W_SMPS_C_CTL_CTRLEN_LSB 0
842 #define A2W_SMPS_L_SPV HW_REGISTER_RW( 0x7e1021d0 )
843 #define A2W_SMPS_L_SPV_MASK 0x0000001f
844 #define A2W_SMPS_L_SPV_WIDTH 5
845 #define A2W_SMPS_L_SPV_RESET 0000000000
846 #define A2W_SMPS_L_SPV_VOLTS_BITS 4:0
847 #define A2W_SMPS_L_SPV_VOLTS_SET 0x0000001f
848 #define A2W_SMPS_L_SPV_VOLTS_CLR 0xffffffe0
849 #define A2W_SMPS_L_SPV_VOLTS_MSB 4
850 #define A2W_SMPS_L_SPV_VOLTS_LSB 0
851 #define A2W_SMPS_L_SPA HW_REGISTER_RW( 0x7e1022d0 )
852 #define A2W_SMPS_L_SPA_MASK 0x000003ff
853 #define A2W_SMPS_L_SPA_WIDTH 10
854 #define A2W_SMPS_L_SPA_RESET 0000000000
855 #define A2W_SMPS_L_SPA_ANA_BITS 9:0
856 #define A2W_SMPS_L_SPA_ANA_SET 0x000003ff
857 #define A2W_SMPS_L_SPA_ANA_CLR 0xfffffc00
858 #define A2W_SMPS_L_SPA_ANA_MSB 9
859 #define A2W_SMPS_L_SPA_ANA_LSB 0
860 #define A2W_SMPS_L_SCV HW_REGISTER_RW( 0x7e1023d0 )
861 #define A2W_SMPS_L_SCV_MASK 0x0000001f
862 #define A2W_SMPS_L_SCV_WIDTH 5
863 #define A2W_SMPS_L_SCV_RESET 0000000000
864 #define A2W_SMPS_L_SCV_VOLTS_BITS 4:0
865 #define A2W_SMPS_L_SCV_VOLTS_SET 0x0000001f
866 #define A2W_SMPS_L_SCV_VOLTS_CLR 0xffffffe0
867 #define A2W_SMPS_L_SCV_VOLTS_MSB 4
868 #define A2W_SMPS_L_SCV_VOLTS_LSB 0
869 #define A2W_SMPS_L_SCA HW_REGISTER_RW( 0x7e1024d0 )
870 #define A2W_SMPS_L_SCA_MASK 0x00000fff
871 #define A2W_SMPS_L_SCA_WIDTH 12
872 #define A2W_SMPS_L_SCA_RESET 0000000000
873 #define A2W_SMPS_L_SCA_ANA_BITS 11:0
874 #define A2W_SMPS_L_SCA_ANA_SET 0x00000fff
875 #define A2W_SMPS_L_SCA_ANA_CLR 0xfffff000
876 #define A2W_SMPS_L_SCA_ANA_MSB 11
877 #define A2W_SMPS_L_SCA_ANA_LSB 0
878 #define A2W_SMPS_L_SIV HW_REGISTER_RW( 0x7e1025d0 )
879 #define A2W_SMPS_L_SIV_MASK 0x0000001f
880 #define A2W_SMPS_L_SIV_WIDTH 5
881 #define A2W_SMPS_L_SIV_RESET 0000000000
882 #define A2W_SMPS_L_SIV_VOLTS_BITS 4:0
883 #define A2W_SMPS_L_SIV_VOLTS_SET 0x0000001f
884 #define A2W_SMPS_L_SIV_VOLTS_CLR 0xffffffe0
885 #define A2W_SMPS_L_SIV_VOLTS_MSB 4
886 #define A2W_SMPS_L_SIV_VOLTS_LSB 0
887 #define A2W_SMPS_L_SIA HW_REGISTER_RW( 0x7e1026d0 )
888 #define A2W_SMPS_L_SIA_MASK 0x000003ff
889 #define A2W_SMPS_L_SIA_WIDTH 10
890 #define A2W_SMPS_L_SIA_RESET 0000000000
891 #define A2W_SMPS_L_SIA_ANA_BITS 9:0
892 #define A2W_SMPS_L_SIA_ANA_SET 0x000003ff
893 #define A2W_SMPS_L_SIA_ANA_CLR 0xfffffc00
894 #define A2W_SMPS_L_SIA_ANA_MSB 9
895 #define A2W_SMPS_L_SIA_ANA_LSB 0
896 #define A2W_XOSC_CTRL HW_REGISTER_RW( 0x7e102190 )
897 #define A2W_XOSC_CTRL_MASK 0x000ff0ff
898 #define A2W_XOSC_CTRL_WIDTH 20
899 #define A2W_XOSC_CTRL_RESET 0000000000
900 #define A2W_XOSC_CTRL_PLLBOK_BITS 19:19
901 #define A2W_XOSC_CTRL_PLLBOK_SET 0x00080000
902 #define A2W_XOSC_CTRL_PLLBOK_CLR 0xfff7ffff
903 #define A2W_XOSC_CTRL_PLLBOK_MSB 19
904 #define A2W_XOSC_CTRL_PLLBOK_LSB 19
905 #define A2W_XOSC_CTRL_PLLAOK_BITS 18:18
906 #define A2W_XOSC_CTRL_PLLAOK_SET 0x00040000
907 #define A2W_XOSC_CTRL_PLLAOK_CLR 0xfffbffff
908 #define A2W_XOSC_CTRL_PLLAOK_MSB 18
909 #define A2W_XOSC_CTRL_PLLAOK_LSB 18
910 #define A2W_XOSC_CTRL_PLLDOK_BITS 17:17
911 #define A2W_XOSC_CTRL_PLLDOK_SET 0x00020000
912 #define A2W_XOSC_CTRL_PLLDOK_CLR 0xfffdffff
913 #define A2W_XOSC_CTRL_PLLDOK_MSB 17
914 #define A2W_XOSC_CTRL_PLLDOK_LSB 17
915 #define A2W_XOSC_CTRL_DDROK_BITS 16:16
916 #define A2W_XOSC_CTRL_DDROK_SET 0x00010000
917 #define A2W_XOSC_CTRL_DDROK_CLR 0xfffeffff
918 #define A2W_XOSC_CTRL_DDROK_MSB 16
919 #define A2W_XOSC_CTRL_DDROK_LSB 16
920 #define A2W_XOSC_CTRL_SMPSOK_BITS 15:15
921 #define A2W_XOSC_CTRL_SMPSOK_SET 0x00008000
922 #define A2W_XOSC_CTRL_SMPSOK_CLR 0xffff7fff
923 #define A2W_XOSC_CTRL_SMPSOK_MSB 15
924 #define A2W_XOSC_CTRL_SMPSOK_LSB 15
925 #define A2W_XOSC_CTRL_USBOK_BITS 14:14
926 #define A2W_XOSC_CTRL_USBOK_SET 0x00004000
927 #define A2W_XOSC_CTRL_USBOK_CLR 0xffffbfff
928 #define A2W_XOSC_CTRL_USBOK_MSB 14
929 #define A2W_XOSC_CTRL_USBOK_LSB 14
930 #define A2W_XOSC_CTRL_HDMIOK_BITS 13:13
931 #define A2W_XOSC_CTRL_HDMIOK_SET 0x00002000
932 #define A2W_XOSC_CTRL_HDMIOK_CLR 0xffffdfff
933 #define A2W_XOSC_CTRL_HDMIOK_MSB 13
934 #define A2W_XOSC_CTRL_HDMIOK_LSB 13
935 #define A2W_XOSC_CTRL_PLLCOK_BITS 12:12
936 #define A2W_XOSC_CTRL_PLLCOK_SET 0x00001000
937 #define A2W_XOSC_CTRL_PLLCOK_CLR 0xffffefff
938 #define A2W_XOSC_CTRL_PLLCOK_MSB 12
939 #define A2W_XOSC_CTRL_PLLCOK_LSB 12
940 #define A2W_XOSC_CTRL_PLLBEN_BITS 7:7
941 #define A2W_XOSC_CTRL_PLLBEN_SET 0x00000080
942 #define A2W_XOSC_CTRL_PLLBEN_CLR 0xffffff7f
943 #define A2W_XOSC_CTRL_PLLBEN_MSB 7
944 #define A2W_XOSC_CTRL_PLLBEN_LSB 7
945 #define A2W_XOSC_CTRL_PLLAEN_BITS 6:6
946 #define A2W_XOSC_CTRL_PLLAEN_SET 0x00000040
947 #define A2W_XOSC_CTRL_PLLAEN_CLR 0xffffffbf
948 #define A2W_XOSC_CTRL_PLLAEN_MSB 6
949 #define A2W_XOSC_CTRL_PLLAEN_LSB 6
950 #define A2W_XOSC_CTRL_PLLDEN_BITS 5:5
951 #define A2W_XOSC_CTRL_PLLDEN_SET 0x00000020
952 #define A2W_XOSC_CTRL_PLLDEN_CLR 0xffffffdf
953 #define A2W_XOSC_CTRL_PLLDEN_MSB 5
954 #define A2W_XOSC_CTRL_PLLDEN_LSB 5
955 #define A2W_XOSC_CTRL_DDREN_BITS 4:4
956 #define A2W_XOSC_CTRL_DDREN_SET 0x00000010
957 #define A2W_XOSC_CTRL_DDREN_CLR 0xffffffef
958 #define A2W_XOSC_CTRL_DDREN_MSB 4
959 #define A2W_XOSC_CTRL_DDREN_LSB 4
960 #define A2W_XOSC_CTRL_SMPSEN_BITS 3:3
961 #define A2W_XOSC_CTRL_SMPSEN_SET 0x00000008
962 #define A2W_XOSC_CTRL_SMPSEN_CLR 0xfffffff7
963 #define A2W_XOSC_CTRL_SMPSEN_MSB 3
964 #define A2W_XOSC_CTRL_SMPSEN_LSB 3
965 #define A2W_XOSC_CTRL_USBEN_BITS 2:2
966 #define A2W_XOSC_CTRL_USBEN_SET 0x00000004
967 #define A2W_XOSC_CTRL_USBEN_CLR 0xfffffffb
968 #define A2W_XOSC_CTRL_USBEN_MSB 2
969 #define A2W_XOSC_CTRL_USBEN_LSB 2
970 #define A2W_XOSC_CTRL_HDMIEN_BITS 1:1
971 #define A2W_XOSC_CTRL_HDMIEN_SET 0x00000002
972 #define A2W_XOSC_CTRL_HDMIEN_CLR 0xfffffffd
973 #define A2W_XOSC_CTRL_HDMIEN_MSB 1
974 #define A2W_XOSC_CTRL_HDMIEN_LSB 1
975 #define A2W_XOSC_CTRL_PLLCEN_BITS 0:0
976 #define A2W_XOSC_CTRL_PLLCEN_SET 0x00000001
977 #define A2W_XOSC_CTRL_PLLCEN_CLR 0xfffffffe
978 #define A2W_XOSC_CTRL_PLLCEN_MSB 0
979 #define A2W_XOSC_CTRL_PLLCEN_LSB 0
980 #define A2W_XOSC_CPR HW_REGISTER_RW( 0x7e102290 )
981 #define A2W_XOSC_CPR_MASK 0x00000013
982 #define A2W_XOSC_CPR_WIDTH 5
983 #define A2W_XOSC_CPR_RESET 0000000000
984 #define A2W_XOSC_CPR_CPR1_BITS 4:4
985 #define A2W_XOSC_CPR_CPR1_SET 0x00000010
986 #define A2W_XOSC_CPR_CPR1_CLR 0xffffffef
987 #define A2W_XOSC_CPR_CPR1_MSB 4
988 #define A2W_XOSC_CPR_CPR1_LSB 4
989 #define A2W_XOSC_CPR_DIV_BITS 1:0
990 #define A2W_XOSC_CPR_DIV_SET 0x00000003
991 #define A2W_XOSC_CPR_DIV_CLR 0xfffffffc
992 #define A2W_XOSC_CPR_DIV_MSB 1
993 #define A2W_XOSC_CPR_DIV_LSB 0
994 #define A2W_XOSC_BIAS HW_REGISTER_RW( 0x7e102390 )
995 #define A2W_XOSC_BIAS_MASK 0x0000001f
996 #define A2W_XOSC_BIAS_WIDTH 5
997 #define A2W_XOSC_BIAS_RESET 0x00000018
998 #define A2W_XOSC_BIAS_HIGHP_BITS 4:4
999 #define A2W_XOSC_BIAS_HIGHP_SET 0x00000010
1000 #define A2W_XOSC_BIAS_HIGHP_CLR 0xffffffef
1001 #define A2W_XOSC_BIAS_HIGHP_MSB 4
1002 #define A2W_XOSC_BIAS_HIGHP_LSB 4
1003 #define A2W_XOSC_BIAS_BIAS_BITS 3:0
1004 #define A2W_XOSC_BIAS_BIAS_SET 0x0000000f
1005 #define A2W_XOSC_BIAS_BIAS_CLR 0xfffffff0
1006 #define A2W_XOSC_BIAS_BIAS_MSB 3
1007 #define A2W_XOSC_BIAS_BIAS_LSB 0
1008 #define A2W_XOSC_PWR HW_REGISTER_RW( 0x7e102490 )
1009 #define A2W_XOSC_PWR_MASK 0x00000007
1010 #define A2W_XOSC_PWR_WIDTH 3
1011 #define A2W_XOSC_PWR_RESET 0x00000004
1012 #define A2W_XOSC_PWR_RSTB_BITS 2:2
1013 #define A2W_XOSC_PWR_RSTB_SET 0x00000004
1014 #define A2W_XOSC_PWR_RSTB_CLR 0xfffffffb
1015 #define A2W_XOSC_PWR_RSTB_MSB 2
1016 #define A2W_XOSC_PWR_RSTB_LSB 2
1017 #define A2W_XOSC_PWR_PWRDN_BITS 1:1
1018 #define A2W_XOSC_PWR_PWRDN_SET 0x00000002
1019 #define A2W_XOSC_PWR_PWRDN_CLR 0xfffffffd
1020 #define A2W_XOSC_PWR_PWRDN_MSB 1
1021 #define A2W_XOSC_PWR_PWRDN_LSB 1
1022 #define A2W_XOSC_PWR_BYPASS_BITS 0:0
1023 #define A2W_XOSC_PWR_BYPASS_SET 0x00000001
1024 #define A2W_XOSC_PWR_BYPASS_CLR 0xfffffffe
1025 #define A2W_XOSC_PWR_BYPASS_MSB 0
1026 #define A2W_XOSC_PWR_BYPASS_LSB 0
1027 #define A2W_PLLA_ANA_SSCS HW_REGISTER_RW( 0x7e102110 )
1028 #define A2W_PLLA_ANA_SSCS_MASK 0x0001ffff
1029 #define A2W_PLLA_ANA_SSCS_WIDTH 17
1030 #define A2W_PLLA_ANA_SSCS_RESET 0000000000
1031 #define A2W_PLLA_ANA_SSCS_MODE_BITS 16:16
1032 #define A2W_PLLA_ANA_SSCS_MODE_SET 0x00010000
1033 #define A2W_PLLA_ANA_SSCS_MODE_CLR 0xfffeffff
1034 #define A2W_PLLA_ANA_SSCS_MODE_MSB 16
1035 #define A2W_PLLA_ANA_SSCS_MODE_LSB 16
1036 #define A2W_PLLA_ANA_SSCS_STEP_BITS 15:0
1037 #define A2W_PLLA_ANA_SSCS_STEP_SET 0x0000ffff
1038 #define A2W_PLLA_ANA_SSCS_STEP_CLR 0xffff0000
1039 #define A2W_PLLA_ANA_SSCS_STEP_MSB 15
1040 #define A2W_PLLA_ANA_SSCS_STEP_LSB 0
1041 #define A2W_PLLA_ANA_SSCL HW_REGISTER_RW( 0x7e102210 )
1042 #define A2W_PLLA_ANA_SSCL_MASK 0x003fffff
1043 #define A2W_PLLA_ANA_SSCL_WIDTH 22
1044 #define A2W_PLLA_ANA_SSCL_RESET 0000000000
1045 #define A2W_PLLA_ANA_SSCL_LIMIT_BITS 21:0
1046 #define A2W_PLLA_ANA_SSCL_LIMIT_SET 0x003fffff
1047 #define A2W_PLLA_ANA_SSCL_LIMIT_CLR 0xffc00000
1048 #define A2W_PLLA_ANA_SSCL_LIMIT_MSB 21
1049 #define A2W_PLLA_ANA_SSCL_LIMIT_LSB 0
1050 #define A2W_PLLA_ANA_KAIP HW_REGISTER_RW( 0x7e102310 )
1051 #define A2W_PLLA_ANA_KAIP_MASK 0x0000077f
1052 #define A2W_PLLA_ANA_KAIP_WIDTH 11
1053 #define A2W_PLLA_ANA_KAIP_RESET 0x0000033a
1054 #define A2W_PLLA_ANA_KAIP_KA_BITS 10:8
1055 #define A2W_PLLA_ANA_KAIP_KA_SET 0x00000700
1056 #define A2W_PLLA_ANA_KAIP_KA_CLR 0xfffff8ff
1057 #define A2W_PLLA_ANA_KAIP_KA_MSB 10
1058 #define A2W_PLLA_ANA_KAIP_KA_LSB 8
1059 #define A2W_PLLA_ANA_KAIP_KI_BITS 6:4
1060 #define A2W_PLLA_ANA_KAIP_KI_SET 0x00000070
1061 #define A2W_PLLA_ANA_KAIP_KI_CLR 0xffffff8f
1062 #define A2W_PLLA_ANA_KAIP_KI_MSB 6
1063 #define A2W_PLLA_ANA_KAIP_KI_LSB 4
1064 #define A2W_PLLA_ANA_KAIP_KP_BITS 3:0
1065 #define A2W_PLLA_ANA_KAIP_KP_SET 0x0000000f
1066 #define A2W_PLLA_ANA_KAIP_KP_CLR 0xfffffff0
1067 #define A2W_PLLA_ANA_KAIP_KP_MSB 3
1068 #define A2W_PLLA_ANA_KAIP_KP_LSB 0
1069 #define A2W_PLLA_ANA_STAT HW_REGISTER_RW( 0x7e102410 )
1070 #define A2W_PLLA_ANA_STAT_MASK 0x00000fff
1071 #define A2W_PLLA_ANA_STAT_WIDTH 12
1072 #define A2W_PLLA_ANA_STAT_RESET 0000000000
1073 #define A2W_PLLA_ANA_STAT_DATA_BITS 11:0
1074 #define A2W_PLLA_ANA_STAT_DATA_SET 0x00000fff
1075 #define A2W_PLLA_ANA_STAT_DATA_CLR 0xfffff000
1076 #define A2W_PLLA_ANA_STAT_DATA_MSB 11
1077 #define A2W_PLLA_ANA_STAT_DATA_LSB 0
1078 #define A2W_PLLA_ANA_SCTL HW_REGISTER_RW( 0x7e102510 )
1079 #define A2W_PLLA_ANA_SCTL_MASK 0x0000001f
1080 #define A2W_PLLA_ANA_SCTL_WIDTH 5
1081 #define A2W_PLLA_ANA_SCTL_RESET 0000000000
1082 #define A2W_PLLA_ANA_SCTL_RESET_BITS 4:4
1083 #define A2W_PLLA_ANA_SCTL_RESET_SET 0x00000010
1084 #define A2W_PLLA_ANA_SCTL_RESET_CLR 0xffffffef
1085 #define A2W_PLLA_ANA_SCTL_RESET_MSB 4
1086 #define A2W_PLLA_ANA_SCTL_RESET_LSB 4
1087 #define A2W_PLLA_ANA_SCTL_UPDATE_BITS 3:3
1088 #define A2W_PLLA_ANA_SCTL_UPDATE_SET 0x00000008
1089 #define A2W_PLLA_ANA_SCTL_UPDATE_CLR 0xfffffff7
1090 #define A2W_PLLA_ANA_SCTL_UPDATE_MSB 3
1091 #define A2W_PLLA_ANA_SCTL_UPDATE_LSB 3
1092 #define A2W_PLLA_ANA_SCTL_SEL_BITS 2:0
1093 #define A2W_PLLA_ANA_SCTL_SEL_SET 0x00000007
1094 #define A2W_PLLA_ANA_SCTL_SEL_CLR 0xfffffff8
1095 #define A2W_PLLA_ANA_SCTL_SEL_MSB 2
1096 #define A2W_PLLA_ANA_SCTL_SEL_LSB 0
1097 #define A2W_PLLA_ANA_VCO HW_REGISTER_RW( 0x7e102610 )
1098 #define A2W_PLLA_ANA_VCO_MASK 0x00000001
1099 #define A2W_PLLA_ANA_VCO_WIDTH 1
1100 #define A2W_PLLA_ANA_VCO_RESET 0000000000
1101 #define A2W_PLLA_ANA_VCO_RANGE_BITS 0:0
1102 #define A2W_PLLA_ANA_VCO_RANGE_SET 0x00000001
1103 #define A2W_PLLA_ANA_VCO_RANGE_CLR 0xfffffffe
1104 #define A2W_PLLA_ANA_VCO_RANGE_MSB 0
1105 #define A2W_PLLA_ANA_VCO_RANGE_LSB 0
1106 #define A2W_PLLB_ANA_SSCS HW_REGISTER_RW( 0x7e1021f0 )
1107 #define A2W_PLLB_ANA_SSCS_MASK 0x0001ffff
1108 #define A2W_PLLB_ANA_SSCS_WIDTH 17
1109 #define A2W_PLLB_ANA_SSCS_RESET 0000000000
1110 #define A2W_PLLB_ANA_SSCS_MODE_BITS 16:16
1111 #define A2W_PLLB_ANA_SSCS_MODE_SET 0x00010000
1112 #define A2W_PLLB_ANA_SSCS_MODE_CLR 0xfffeffff
1113 #define A2W_PLLB_ANA_SSCS_MODE_MSB 16
1114 #define A2W_PLLB_ANA_SSCS_MODE_LSB 16
1115 #define A2W_PLLB_ANA_SSCS_STEP_BITS 15:0
1116 #define A2W_PLLB_ANA_SSCS_STEP_SET 0x0000ffff
1117 #define A2W_PLLB_ANA_SSCS_STEP_CLR 0xffff0000
1118 #define A2W_PLLB_ANA_SSCS_STEP_MSB 15
1119 #define A2W_PLLB_ANA_SSCS_STEP_LSB 0
1120 #define A2W_PLLB_ANA_SSCL HW_REGISTER_RW( 0x7e1022f0 )
1121 #define A2W_PLLB_ANA_SSCL_MASK 0x003fffff
1122 #define A2W_PLLB_ANA_SSCL_WIDTH 22
1123 #define A2W_PLLB_ANA_SSCL_RESET 0000000000
1124 #define A2W_PLLB_ANA_SSCL_LIMIT_BITS 21:0
1125 #define A2W_PLLB_ANA_SSCL_LIMIT_SET 0x003fffff
1126 #define A2W_PLLB_ANA_SSCL_LIMIT_CLR 0xffc00000
1127 #define A2W_PLLB_ANA_SSCL_LIMIT_MSB 21
1128 #define A2W_PLLB_ANA_SSCL_LIMIT_LSB 0
1129 #define A2W_PLLB_ANA_KAIP HW_REGISTER_RW( 0x7e1023f0 )
1130 #define A2W_PLLB_ANA_KAIP_MASK 0x0000077f
1131 #define A2W_PLLB_ANA_KAIP_WIDTH 11
1132 #define A2W_PLLB_ANA_KAIP_RESET 0x0000033a
1133 #define A2W_PLLB_ANA_KAIP_KA_BITS 10:8
1134 #define A2W_PLLB_ANA_KAIP_KA_SET 0x00000700
1135 #define A2W_PLLB_ANA_KAIP_KA_CLR 0xfffff8ff
1136 #define A2W_PLLB_ANA_KAIP_KA_MSB 10
1137 #define A2W_PLLB_ANA_KAIP_KA_LSB 8
1138 #define A2W_PLLB_ANA_KAIP_KI_BITS 6:4
1139 #define A2W_PLLB_ANA_KAIP_KI_SET 0x00000070
1140 #define A2W_PLLB_ANA_KAIP_KI_CLR 0xffffff8f
1141 #define A2W_PLLB_ANA_KAIP_KI_MSB 6
1142 #define A2W_PLLB_ANA_KAIP_KI_LSB 4
1143 #define A2W_PLLB_ANA_KAIP_KP_BITS 3:0
1144 #define A2W_PLLB_ANA_KAIP_KP_SET 0x0000000f
1145 #define A2W_PLLB_ANA_KAIP_KP_CLR 0xfffffff0
1146 #define A2W_PLLB_ANA_KAIP_KP_MSB 3
1147 #define A2W_PLLB_ANA_KAIP_KP_LSB 0
1148 #define A2W_PLLB_ANA_STAT HW_REGISTER_RW( 0x7e1024f0 )
1149 #define A2W_PLLB_ANA_STAT_MASK 0x00000fff
1150 #define A2W_PLLB_ANA_STAT_WIDTH 12
1151 #define A2W_PLLB_ANA_STAT_RESET 0000000000
1152 #define A2W_PLLB_ANA_STAT_DATA_BITS 11:0
1153 #define A2W_PLLB_ANA_STAT_DATA_SET 0x00000fff
1154 #define A2W_PLLB_ANA_STAT_DATA_CLR 0xfffff000
1155 #define A2W_PLLB_ANA_STAT_DATA_MSB 11
1156 #define A2W_PLLB_ANA_STAT_DATA_LSB 0
1157 #define A2W_PLLB_ANA_SCTL HW_REGISTER_RW( 0x7e1025f0 )
1158 #define A2W_PLLB_ANA_SCTL_MASK 0x0000001f
1159 #define A2W_PLLB_ANA_SCTL_WIDTH 5
1160 #define A2W_PLLB_ANA_SCTL_RESET 0000000000
1161 #define A2W_PLLB_ANA_SCTL_RESET_BITS 4:4
1162 #define A2W_PLLB_ANA_SCTL_RESET_SET 0x00000010
1163 #define A2W_PLLB_ANA_SCTL_RESET_CLR 0xffffffef
1164 #define A2W_PLLB_ANA_SCTL_RESET_MSB 4
1165 #define A2W_PLLB_ANA_SCTL_RESET_LSB 4
1166 #define A2W_PLLB_ANA_SCTL_UPDATE_BITS 3:3
1167 #define A2W_PLLB_ANA_SCTL_UPDATE_SET 0x00000008
1168 #define A2W_PLLB_ANA_SCTL_UPDATE_CLR 0xfffffff7
1169 #define A2W_PLLB_ANA_SCTL_UPDATE_MSB 3
1170 #define A2W_PLLB_ANA_SCTL_UPDATE_LSB 3
1171 #define A2W_PLLB_ANA_SCTL_SEL_BITS 2:0
1172 #define A2W_PLLB_ANA_SCTL_SEL_SET 0x00000007
1173 #define A2W_PLLB_ANA_SCTL_SEL_CLR 0xfffffff8
1174 #define A2W_PLLB_ANA_SCTL_SEL_MSB 2
1175 #define A2W_PLLB_ANA_SCTL_SEL_LSB 0
1176 #define A2W_PLLB_ANA_VCO HW_REGISTER_RW( 0x7e1026f0 )
1177 #define A2W_PLLB_ANA_VCO_MASK 0x00000001
1178 #define A2W_PLLB_ANA_VCO_WIDTH 1
1179 #define A2W_PLLB_ANA_VCO_RESET 0000000000
1180 #define A2W_PLLB_ANA_VCO_RANGE_BITS 0:0
1181 #define A2W_PLLB_ANA_VCO_RANGE_SET 0x00000001
1182 #define A2W_PLLB_ANA_VCO_RANGE_CLR 0xfffffffe
1183 #define A2W_PLLB_ANA_VCO_RANGE_MSB 0
1184 #define A2W_PLLB_ANA_VCO_RANGE_LSB 0
1185 #define A2W_PLLC_ANA_SSCS HW_REGISTER_RW( 0x7e102130 )
1186 #define A2W_PLLC_ANA_SSCS_MASK 0x0001ffff
1187 #define A2W_PLLC_ANA_SSCS_WIDTH 17
1188 #define A2W_PLLC_ANA_SSCS_RESET 0000000000
1189 #define A2W_PLLC_ANA_SSCS_MODE_BITS 16:16
1190 #define A2W_PLLC_ANA_SSCS_MODE_SET 0x00010000
1191 #define A2W_PLLC_ANA_SSCS_MODE_CLR 0xfffeffff
1192 #define A2W_PLLC_ANA_SSCS_MODE_MSB 16
1193 #define A2W_PLLC_ANA_SSCS_MODE_LSB 16
1194 #define A2W_PLLC_ANA_SSCS_STEP_BITS 15:0
1195 #define A2W_PLLC_ANA_SSCS_STEP_SET 0x0000ffff
1196 #define A2W_PLLC_ANA_SSCS_STEP_CLR 0xffff0000
1197 #define A2W_PLLC_ANA_SSCS_STEP_MSB 15
1198 #define A2W_PLLC_ANA_SSCS_STEP_LSB 0
1199 #define A2W_PLLC_ANA_SSCL HW_REGISTER_RW( 0x7e102230 )
1200 #define A2W_PLLC_ANA_SSCL_MASK 0x003fffff
1201 #define A2W_PLLC_ANA_SSCL_WIDTH 22
1202 #define A2W_PLLC_ANA_SSCL_RESET 0000000000
1203 #define A2W_PLLC_ANA_KAIP HW_REGISTER_RW( 0x7e102330 )
1204 #define A2W_PLLC_ANA_KAIP_MASK 0x0000077f
1205 #define A2W_PLLC_ANA_KAIP_WIDTH 11
1206 #define A2W_PLLC_ANA_KAIP_RESET 0x0000033a
1207 #define A2W_PLLC_ANA_KAIP_KA_BITS 10:8
1208 #define A2W_PLLC_ANA_KAIP_KA_SET 0x00000700
1209 #define A2W_PLLC_ANA_KAIP_KA_CLR 0xfffff8ff
1210 #define A2W_PLLC_ANA_KAIP_KA_MSB 10
1211 #define A2W_PLLC_ANA_KAIP_KA_LSB 8
1212 #define A2W_PLLC_ANA_KAIP_KI_BITS 6:4
1213 #define A2W_PLLC_ANA_KAIP_KI_SET 0x00000070
1214 #define A2W_PLLC_ANA_KAIP_KI_CLR 0xffffff8f
1215 #define A2W_PLLC_ANA_KAIP_KI_MSB 6
1216 #define A2W_PLLC_ANA_KAIP_KI_LSB 4
1217 #define A2W_PLLC_ANA_KAIP_KP_BITS 3:0
1218 #define A2W_PLLC_ANA_KAIP_KP_SET 0x0000000f
1219 #define A2W_PLLC_ANA_KAIP_KP_CLR 0xfffffff0
1220 #define A2W_PLLC_ANA_KAIP_KP_MSB 3
1221 #define A2W_PLLC_ANA_KAIP_KP_LSB 0
1222 #define A2W_PLLC_ANA_STAT HW_REGISTER_RW( 0x7e102430 )
1223 #define A2W_PLLC_ANA_STAT_MASK 0x00000fff
1224 #define A2W_PLLC_ANA_STAT_WIDTH 12
1225 #define A2W_PLLC_ANA_STAT_RESET 0000000000
1226 #define A2W_PLLC_ANA_STAT_DATA_BITS 11:0
1227 #define A2W_PLLC_ANA_STAT_DATA_SET 0x00000fff
1228 #define A2W_PLLC_ANA_STAT_DATA_CLR 0xfffff000
1229 #define A2W_PLLC_ANA_STAT_DATA_MSB 11
1230 #define A2W_PLLC_ANA_STAT_DATA_LSB 0
1231 #define A2W_PLLC_ANA_SCTL HW_REGISTER_RW( 0x7e102530 )
1232 #define A2W_PLLC_ANA_SCTL_MASK 0x0000001f
1233 #define A2W_PLLC_ANA_SCTL_WIDTH 5
1234 #define A2W_PLLC_ANA_SCTL_RESET 0000000000
1235 #define A2W_PLLC_ANA_SCTL_RESET_BITS 4:4
1236 #define A2W_PLLC_ANA_SCTL_RESET_SET 0x00000010
1237 #define A2W_PLLC_ANA_SCTL_RESET_CLR 0xffffffef
1238 #define A2W_PLLC_ANA_SCTL_RESET_MSB 4
1239 #define A2W_PLLC_ANA_SCTL_RESET_LSB 4
1240 #define A2W_PLLC_ANA_SCTL_UPDATE_BITS 3:3
1241 #define A2W_PLLC_ANA_SCTL_UPDATE_SET 0x00000008
1242 #define A2W_PLLC_ANA_SCTL_UPDATE_CLR 0xfffffff7
1243 #define A2W_PLLC_ANA_SCTL_UPDATE_MSB 3
1244 #define A2W_PLLC_ANA_SCTL_UPDATE_LSB 3
1245 #define A2W_PLLC_ANA_SCTL_SEL_BITS 2:0
1246 #define A2W_PLLC_ANA_SCTL_SEL_SET 0x00000007
1247 #define A2W_PLLC_ANA_SCTL_SEL_CLR 0xfffffff8
1248 #define A2W_PLLC_ANA_SCTL_SEL_MSB 2
1249 #define A2W_PLLC_ANA_SCTL_SEL_LSB 0
1250 #define A2W_PLLC_ANA_VCO HW_REGISTER_RW( 0x7e102630 )
1251 #define A2W_PLLC_ANA_VCO_MASK 0x00000001
1252 #define A2W_PLLC_ANA_VCO_WIDTH 1
1253 #define A2W_PLLC_ANA_VCO_RESET 0000000000
1254 #define A2W_PLLC_ANA_VCO_RANGE_BITS 0:0
1255 #define A2W_PLLC_ANA_VCO_RANGE_SET 0x00000001
1256 #define A2W_PLLC_ANA_VCO_RANGE_CLR 0xfffffffe
1257 #define A2W_PLLC_ANA_VCO_RANGE_MSB 0
1258 #define A2W_PLLC_ANA_VCO_RANGE_LSB 0
1259 #define A2W_PLLD_ANA_SSCS HW_REGISTER_RW( 0x7e102150 )
1260 #define A2W_PLLD_ANA_SSCS_MASK 0x0001ffff
1261 #define A2W_PLLD_ANA_SSCS_WIDTH 17
1262 #define A2W_PLLD_ANA_SSCS_RESET 0000000000
1263 #define A2W_PLLD_ANA_SSCS_MODE_BITS 16:16
1264 #define A2W_PLLD_ANA_SSCS_MODE_SET 0x00010000
1265 #define A2W_PLLD_ANA_SSCS_MODE_CLR 0xfffeffff
1266 #define A2W_PLLD_ANA_SSCS_MODE_MSB 16
1267 #define A2W_PLLD_ANA_SSCS_MODE_LSB 16
1268 #define A2W_PLLD_ANA_SSCS_STEP_BITS 15:0
1269 #define A2W_PLLD_ANA_SSCS_STEP_SET 0x0000ffff
1270 #define A2W_PLLD_ANA_SSCS_STEP_CLR 0xffff0000
1271 #define A2W_PLLD_ANA_SSCS_STEP_MSB 15
1272 #define A2W_PLLD_ANA_SSCS_STEP_LSB 0
1273 #define A2W_PLLD_ANA_SSCL HW_REGISTER_RW( 0x7e102250 )
1274 #define A2W_PLLD_ANA_SSCL_MASK 0x003fffff
1275 #define A2W_PLLD_ANA_SSCL_WIDTH 22
1276 #define A2W_PLLD_ANA_SSCL_RESET 0000000000
1277 #define A2W_PLLD_ANA_KAIP HW_REGISTER_RW( 0x7e102350 )
1278 #define A2W_PLLD_ANA_KAIP_MASK 0x0000077f
1279 #define A2W_PLLD_ANA_KAIP_WIDTH 11
1280 #define A2W_PLLD_ANA_KAIP_RESET 0x0000033a
1281 #define A2W_PLLD_ANA_KAIP_KA_BITS 10:8
1282 #define A2W_PLLD_ANA_KAIP_KA_SET 0x00000700
1283 #define A2W_PLLD_ANA_KAIP_KA_CLR 0xfffff8ff
1284 #define A2W_PLLD_ANA_KAIP_KA_MSB 10
1285 #define A2W_PLLD_ANA_KAIP_KA_LSB 8
1286 #define A2W_PLLD_ANA_KAIP_KI_BITS 6:4
1287 #define A2W_PLLD_ANA_KAIP_KI_SET 0x00000070
1288 #define A2W_PLLD_ANA_KAIP_KI_CLR 0xffffff8f
1289 #define A2W_PLLD_ANA_KAIP_KI_MSB 6
1290 #define A2W_PLLD_ANA_KAIP_KI_LSB 4
1291 #define A2W_PLLD_ANA_KAIP_KP_BITS 3:0
1292 #define A2W_PLLD_ANA_KAIP_KP_SET 0x0000000f
1293 #define A2W_PLLD_ANA_KAIP_KP_CLR 0xfffffff0
1294 #define A2W_PLLD_ANA_KAIP_KP_MSB 3
1295 #define A2W_PLLD_ANA_KAIP_KP_LSB 0
1296 #define A2W_PLLD_ANA_STAT HW_REGISTER_RW( 0x7e102450 )
1297 #define A2W_PLLD_ANA_STAT_MASK 0x00000fff
1298 #define A2W_PLLD_ANA_STAT_WIDTH 12
1299 #define A2W_PLLD_ANA_STAT_RESET 0000000000
1300 #define A2W_PLLD_ANA_STAT_DATA_BITS 11:0
1301 #define A2W_PLLD_ANA_STAT_DATA_SET 0x00000fff
1302 #define A2W_PLLD_ANA_STAT_DATA_CLR 0xfffff000
1303 #define A2W_PLLD_ANA_STAT_DATA_MSB 11
1304 #define A2W_PLLD_ANA_STAT_DATA_LSB 0
1305 #define A2W_PLLD_ANA_SCTL HW_REGISTER_RW( 0x7e102550 )
1306 #define A2W_PLLD_ANA_SCTL_MASK 0x0000001f
1307 #define A2W_PLLD_ANA_SCTL_WIDTH 5
1308 #define A2W_PLLD_ANA_SCTL_RESET 0000000000
1309 #define A2W_PLLD_ANA_SCTL_RESET_BITS 4:4
1310 #define A2W_PLLD_ANA_SCTL_RESET_SET 0x00000010
1311 #define A2W_PLLD_ANA_SCTL_RESET_CLR 0xffffffef
1312 #define A2W_PLLD_ANA_SCTL_RESET_MSB 4
1313 #define A2W_PLLD_ANA_SCTL_RESET_LSB 4
1314 #define A2W_PLLD_ANA_SCTL_UPDATE_BITS 3:3
1315 #define A2W_PLLD_ANA_SCTL_UPDATE_SET 0x00000008
1316 #define A2W_PLLD_ANA_SCTL_UPDATE_CLR 0xfffffff7
1317 #define A2W_PLLD_ANA_SCTL_UPDATE_MSB 3
1318 #define A2W_PLLD_ANA_SCTL_UPDATE_LSB 3
1319 #define A2W_PLLD_ANA_SCTL_SEL_BITS 2:0
1320 #define A2W_PLLD_ANA_SCTL_SEL_SET 0x00000007
1321 #define A2W_PLLD_ANA_SCTL_SEL_CLR 0xfffffff8
1322 #define A2W_PLLD_ANA_SCTL_SEL_MSB 2
1323 #define A2W_PLLD_ANA_SCTL_SEL_LSB 0
1324 #define A2W_PLLD_ANA_VCO HW_REGISTER_RW( 0x7e102650 )
1325 #define A2W_PLLD_ANA_VCO_MASK 0x00000001
1326 #define A2W_PLLD_ANA_VCO_WIDTH 1
1327 #define A2W_PLLD_ANA_VCO_RESET 0000000000
1328 #define A2W_PLLD_ANA_VCO_RANGE_BITS 0:0
1329 #define A2W_PLLD_ANA_VCO_RANGE_SET 0x00000001
1330 #define A2W_PLLD_ANA_VCO_RANGE_CLR 0xfffffffe
1331 #define A2W_PLLD_ANA_VCO_RANGE_MSB 0
1332 #define A2W_PLLD_ANA_VCO_RANGE_LSB 0
1333 #define A2W_PLLH_ANA_KAIP HW_REGISTER_RW( 0x7e102370 )
1334 #define A2W_PLLH_ANA_KAIP_MASK 0x0000077f
1335 #define A2W_PLLH_ANA_KAIP_WIDTH 11
1336 #define A2W_PLLH_ANA_KAIP_RESET 0x0000033a
1337 #define A2W_PLLH_ANA_KAIP_KA_BITS 10:8
1338 #define A2W_PLLH_ANA_KAIP_KA_SET 0x00000700
1339 #define A2W_PLLH_ANA_KAIP_KA_CLR 0xfffff8ff
1340 #define A2W_PLLH_ANA_KAIP_KA_MSB 10
1341 #define A2W_PLLH_ANA_KAIP_KA_LSB 8
1342 #define A2W_PLLH_ANA_KAIP_KI_BITS 6:4
1343 #define A2W_PLLH_ANA_KAIP_KI_SET 0x00000070
1344 #define A2W_PLLH_ANA_KAIP_KI_CLR 0xffffff8f
1345 #define A2W_PLLH_ANA_KAIP_KI_MSB 6
1346 #define A2W_PLLH_ANA_KAIP_KI_LSB 4
1347 #define A2W_PLLH_ANA_KAIP_KP_BITS 3:0
1348 #define A2W_PLLH_ANA_KAIP_KP_SET 0x0000000f
1349 #define A2W_PLLH_ANA_KAIP_KP_CLR 0xfffffff0
1350 #define A2W_PLLH_ANA_KAIP_KP_MSB 3
1351 #define A2W_PLLH_ANA_KAIP_KP_LSB 0
1352 #define A2W_PLLH_ANA_STAT HW_REGISTER_RW( 0x7e102660 )
1353 #define A2W_PLLH_ANA_STAT_MASK 0x001f1fff
1354 #define A2W_PLLH_ANA_STAT_WIDTH 21
1355 #define A2W_PLLH_ANA_STAT_RESET 0000000000
1356 #define A2W_PLLH_ANA_STAT_CNTLENB_BITS 20:20
1357 #define A2W_PLLH_ANA_STAT_CNTLENB_SET 0x00100000
1358 #define A2W_PLLH_ANA_STAT_CNTLENB_CLR 0xffefffff
1359 #define A2W_PLLH_ANA_STAT_CNTLENB_MSB 20
1360 #define A2W_PLLH_ANA_STAT_CNTLENB_LSB 20
1361 #define A2W_PLLH_ANA_STAT_RCALCODE_BITS 19:16
1362 #define A2W_PLLH_ANA_STAT_RCALCODE_SET 0x000f0000
1363 #define A2W_PLLH_ANA_STAT_RCALCODE_CLR 0xfff0ffff
1364 #define A2W_PLLH_ANA_STAT_RCALCODE_MSB 19
1365 #define A2W_PLLH_ANA_STAT_RCALCODE_LSB 16
1366 #define A2W_PLLH_ANA_STAT_RCALDONE_BITS 12:12
1367 #define A2W_PLLH_ANA_STAT_RCALDONE_SET 0x00001000
1368 #define A2W_PLLH_ANA_STAT_RCALDONE_CLR 0xffffefff
1369 #define A2W_PLLH_ANA_STAT_RCALDONE_MSB 12
1370 #define A2W_PLLH_ANA_STAT_RCALDONE_LSB 12
1371 #define A2W_PLLH_ANA_STAT_DATA_BITS 11:0
1372 #define A2W_PLLH_ANA_STAT_DATA_SET 0x00000fff
1373 #define A2W_PLLH_ANA_STAT_DATA_CLR 0xfffff000
1374 #define A2W_PLLH_ANA_STAT_DATA_MSB 11
1375 #define A2W_PLLH_ANA_STAT_DATA_LSB 0
1376 #define A2W_PLLH_ANA_SCTL HW_REGISTER_RW( 0x7e102570 )
1377 #define A2W_PLLH_ANA_SCTL_MASK 0x0000001f
1378 #define A2W_PLLH_ANA_SCTL_WIDTH 5
1379 #define A2W_PLLH_ANA_SCTL_RESET 0000000000
1380 #define A2W_PLLH_ANA_SCTL_RESET_BITS 4:4
1381 #define A2W_PLLH_ANA_SCTL_RESET_SET 0x00000010
1382 #define A2W_PLLH_ANA_SCTL_RESET_CLR 0xffffffef
1383 #define A2W_PLLH_ANA_SCTL_RESET_MSB 4
1384 #define A2W_PLLH_ANA_SCTL_RESET_LSB 4
1385 #define A2W_PLLH_ANA_SCTL_UPDATE_BITS 3:3
1386 #define A2W_PLLH_ANA_SCTL_UPDATE_SET 0x00000008
1387 #define A2W_PLLH_ANA_SCTL_UPDATE_CLR 0xfffffff7
1388 #define A2W_PLLH_ANA_SCTL_UPDATE_MSB 3
1389 #define A2W_PLLH_ANA_SCTL_UPDATE_LSB 3
1390 #define A2W_PLLH_ANA_SCTL_SEL_BITS 2:0
1391 #define A2W_PLLH_ANA_SCTL_SEL_SET 0x00000007
1392 #define A2W_PLLH_ANA_SCTL_SEL_CLR 0xfffffff8
1393 #define A2W_PLLH_ANA_SCTL_SEL_MSB 2
1394 #define A2W_PLLH_ANA_SCTL_SEL_LSB 0
1395 #define A2W_PLLH_ANA_VCO HW_REGISTER_RW( 0x7e102670 )
1396 #define A2W_PLLH_ANA_VCO_MASK 0x00000001
1397 #define A2W_PLLH_ANA_VCO_WIDTH 1
1398 #define A2W_PLLH_ANA_VCO_RESET 0000000000
1399 #define A2W_PLLH_ANA_VCO_RANGE_BITS 0:0
1400 #define A2W_PLLH_ANA_VCO_RANGE_SET 0x00000001
1401 #define A2W_PLLH_ANA_VCO_RANGE_CLR 0xfffffffe
1402 #define A2W_PLLH_ANA_VCO_RANGE_MSB 0
1403 #define A2W_PLLH_ANA_VCO_RANGE_LSB 0
1404 #define A2W_HDMI_CTL_RCAL HW_REGISTER_RW( 0x7e102180 )
1405 #define A2W_HDMI_CTL_RCAL_MASK 0x00011f33
1406 #define A2W_HDMI_CTL_RCAL_WIDTH 17
1407 #define A2W_HDMI_CTL_RCAL_RESET 0x00010000
1408 #define A2W_HDMI_CTL_RCAL_RSTB_BITS 16:16
1409 #define A2W_HDMI_CTL_RCAL_RSTB_SET 0x00010000
1410 #define A2W_HDMI_CTL_RCAL_RSTB_CLR 0xfffeffff
1411 #define A2W_HDMI_CTL_RCAL_RSTB_MSB 16
1412 #define A2W_HDMI_CTL_RCAL_RSTB_LSB 16
1413 #define A2W_HDMI_CTL_RCAL_MANREN_BITS 12:12
1414 #define A2W_HDMI_CTL_RCAL_MANREN_SET 0x00001000
1415 #define A2W_HDMI_CTL_RCAL_MANREN_CLR 0xffffefff
1416 #define A2W_HDMI_CTL_RCAL_MANREN_MSB 12
1417 #define A2W_HDMI_CTL_RCAL_MANREN_LSB 12
1418 #define A2W_HDMI_CTL_RCAL_MANR_BITS 11:8
1419 #define A2W_HDMI_CTL_RCAL_MANR_SET 0x00000f00
1420 #define A2W_HDMI_CTL_RCAL_MANR_CLR 0xfffff0ff
1421 #define A2W_HDMI_CTL_RCAL_MANR_MSB 11
1422 #define A2W_HDMI_CTL_RCAL_MANR_LSB 8
1423 #define A2W_HDMI_CTL_RCAL_SELDIV_BITS 5:4
1424 #define A2W_HDMI_CTL_RCAL_SELDIV_SET 0x00000030
1425 #define A2W_HDMI_CTL_RCAL_SELDIV_CLR 0xffffffcf
1426 #define A2W_HDMI_CTL_RCAL_SELDIV_MSB 5
1427 #define A2W_HDMI_CTL_RCAL_SELDIV_LSB 4
1428 #define A2W_HDMI_CTL_RCAL_SELAVG_BITS 1:0
1429 #define A2W_HDMI_CTL_RCAL_SELAVG_SET 0x00000003
1430 #define A2W_HDMI_CTL_RCAL_SELAVG_CLR 0xfffffffc
1431 #define A2W_HDMI_CTL_RCAL_SELAVG_MSB 1
1432 #define A2W_HDMI_CTL_RCAL_SELAVG_LSB 0
1433 #define A2W_HDMI_CTL_HFEN HW_REGISTER_RW( 0x7e102280 )
1434 #define A2W_HDMI_CTL_HFEN_MASK 0x00000001
1435 #define A2W_HDMI_CTL_HFEN_WIDTH 1
1436 #define A2W_HDMI_CTL_HFEN_RESET 0000000000
1437 #define A2W_HDMI_CTL_HFEN_HFEN_BITS 0:0
1438 #define A2W_HDMI_CTL_HFEN_HFEN_SET 0x00000001
1439 #define A2W_HDMI_CTL_HFEN_HFEN_CLR 0xfffffffe
1440 #define A2W_HDMI_CTL_HFEN_HFEN_MSB 0
1441 #define A2W_HDMI_CTL_HFEN_HFEN_LSB 0
1442 #define A2W_PLLA_DIG0R HW_REGISTER_RW( 0x7e102800 )
1443 #define A2W_PLLA_DIG0R_MASK 0x00ffffff
1444 #define A2W_PLLA_DIG0R_WIDTH 24
1445 #define A2W_PLLA_DIG0R_RESET 0000000000
1446 #define A2W_PLLA_DIG1R HW_REGISTER_RW( 0x7e102804 )
1447 #define A2W_PLLA_DIG1R_MASK 0x00ffffff
1448 #define A2W_PLLA_DIG1R_WIDTH 24
1449 #define A2W_PLLA_DIG1R_RESET 0x00004000
1450 #define A2W_PLLA_DIG2R HW_REGISTER_RW( 0x7e102808 )
1451 #define A2W_PLLA_DIG2R_MASK 0x00ffffff
1452 #define A2W_PLLA_DIG2R_WIDTH 24
1453 #define A2W_PLLA_DIG2R_RESET 0x00100401
1454 #define A2W_PLLA_DIG3R HW_REGISTER_RW( 0x7e10280c )
1455 #define A2W_PLLA_DIG3R_MASK 0x00ffffff
1456 #define A2W_PLLA_DIG3R_WIDTH 24
1457 #define A2W_PLLA_DIG3R_RESET 0x00000004
1458 #define A2W_PLLA_ANA0R HW_REGISTER_RW( 0x7e102810 )
1459 #define A2W_PLLA_ANA0R_MASK 0x00ffffff
1460 #define A2W_PLLA_ANA0R_WIDTH 24
1461 #define A2W_PLLA_ANA0R_RESET 0000000000
1462 #define A2W_PLLA_ANA1R HW_REGISTER_RW( 0x7e102814 )
1463 #define A2W_PLLA_ANA1R_MASK 0x00ffffff
1464 #define A2W_PLLA_ANA1R_WIDTH 24
1465 #define A2W_PLLA_ANA1R_RESET 0x001d0000
1466 #define A2W_PLLA_ANA2R HW_REGISTER_RW( 0x7e102818 )
1467 #define A2W_PLLA_ANA2R_MASK 0x00ffffff
1468 #define A2W_PLLA_ANA2R_WIDTH 24
1469 #define A2W_PLLA_ANA2R_RESET 0000000000
1470 #define A2W_PLLA_ANA3R HW_REGISTER_RW( 0x7e10281c )
1471 #define A2W_PLLA_ANA3R_MASK 0x00ffffff
1472 #define A2W_PLLA_ANA3R_WIDTH 24
1473 #define A2W_PLLA_ANA3R_RESET 0x00000180
1474 #define A2W_PLLB_DIG0R HW_REGISTER_RW( 0x7e1028e0 )
1475 #define A2W_PLLB_DIG0R_MASK 0x00ffffff
1476 #define A2W_PLLB_DIG0R_WIDTH 24
1477 #define A2W_PLLB_DIG0R_RESET 0000000000
1478 #define A2W_PLLB_DIG1R HW_REGISTER_RW( 0x7e1028e4 )
1479 #define A2W_PLLB_DIG1R_MASK 0x00ffffff
1480 #define A2W_PLLB_DIG1R_WIDTH 24
1481 #define A2W_PLLB_DIG1R_RESET 0x00004000
1482 #define A2W_PLLB_DIG2R HW_REGISTER_RW( 0x7e1028e8 )
1483 #define A2W_PLLB_DIG2R_MASK 0x00ffffff
1484 #define A2W_PLLB_DIG2R_WIDTH 24
1485 #define A2W_PLLB_DIG2R_RESET 0x00100401
1486 #define A2W_PLLB_DIG3R HW_REGISTER_RW( 0x7e1028ec )
1487 #define A2W_PLLB_DIG3R_MASK 0x00ffffff
1488 #define A2W_PLLB_DIG3R_WIDTH 24
1489 #define A2W_PLLB_DIG3R_RESET 0x00000004
1490 #define A2W_PLLB_ANA0R HW_REGISTER_RW( 0x7e1028f0 )
1491 #define A2W_PLLB_ANA0R_MASK 0x00ffffff
1492 #define A2W_PLLB_ANA0R_WIDTH 24
1493 #define A2W_PLLB_ANA0R_RESET 0000000000
1494 #define A2W_PLLB_ANA1R HW_REGISTER_RW( 0x7e1028f4 )
1495 #define A2W_PLLB_ANA1R_MASK 0x00ffffff
1496 #define A2W_PLLB_ANA1R_WIDTH 24
1497 #define A2W_PLLB_ANA1R_RESET 0x001d0000
1498 #define A2W_PLLB_ANA2R HW_REGISTER_RW( 0x7e1028f8 )
1499 #define A2W_PLLB_ANA2R_MASK 0x00ffffff
1500 #define A2W_PLLB_ANA2R_WIDTH 24
1501 #define A2W_PLLB_ANA2R_RESET 0000000000
1502 #define A2W_PLLB_ANA3R HW_REGISTER_RW( 0x7e1028fc )
1503 #define A2W_PLLB_ANA3R_MASK 0x00ffffff
1504 #define A2W_PLLB_ANA3R_WIDTH 24
1505 #define A2W_PLLB_ANA3R_RESET 0x00000180
1506 #define A2W_PLLC_DIG0R HW_REGISTER_RW( 0x7e102820 )
1507 #define A2W_PLLC_DIG0R_MASK 0x00ffffff
1508 #define A2W_PLLC_DIG0R_WIDTH 24
1509 #define A2W_PLLC_DIG0R_RESET 0000000000
1510 #define A2W_PLLC_DIG1R HW_REGISTER_RW( 0x7e102824 )
1511 #define A2W_PLLC_DIG1R_MASK 0x00ffffff
1512 #define A2W_PLLC_DIG1R_WIDTH 24
1513 #define A2W_PLLC_DIG1R_RESET 0x00004000
1514 #define A2W_PLLC_DIG2R HW_REGISTER_RW( 0x7e102828 )
1515 #define A2W_PLLC_DIG2R_MASK 0x00ffffff
1516 #define A2W_PLLC_DIG2R_WIDTH 24
1517 #define A2W_PLLC_DIG2R_RESET 0x00100401
1518 #define A2W_PLLC_DIG3R HW_REGISTER_RW( 0x7e10282c )
1519 #define A2W_PLLC_DIG3R_MASK 0x00ffffff
1520 #define A2W_PLLC_DIG3R_WIDTH 24
1521 #define A2W_PLLC_DIG3R_RESET 0x00000004
1522 #define A2W_PLLC_ANA0R HW_REGISTER_RW( 0x7e102830 )
1523 #define A2W_PLLC_ANA0R_MASK 0x00ffffff
1524 #define A2W_PLLC_ANA0R_WIDTH 24
1525 #define A2W_PLLC_ANA0R_RESET 0000000000
1526 #define A2W_PLLC_ANA1R HW_REGISTER_RW( 0x7e102834 )
1527 #define A2W_PLLC_ANA1R_MASK 0x00ffffff
1528 #define A2W_PLLC_ANA1R_WIDTH 24
1529 #define A2W_PLLC_ANA1R_RESET 0x001d0000
1530 #define A2W_PLLC_ANA2R HW_REGISTER_RW( 0x7e102838 )
1531 #define A2W_PLLC_ANA2R_MASK 0x00ffffff
1532 #define A2W_PLLC_ANA2R_WIDTH 24
1533 #define A2W_PLLC_ANA2R_RESET 0000000000
1534 #define A2W_PLLC_ANA3R HW_REGISTER_RW( 0x7e10283c )
1535 #define A2W_PLLC_ANA3R_MASK 0x00ffffff
1536 #define A2W_PLLC_ANA3R_WIDTH 24
1537 #define A2W_PLLC_ANA3R_RESET 0x00000180
1538 #define A2W_PLLD_DIG0R HW_REGISTER_RW( 0x7e102840 )
1539 #define A2W_PLLD_DIG0R_MASK 0x00ffffff
1540 #define A2W_PLLD_DIG0R_WIDTH 24
1541 #define A2W_PLLD_DIG0R_RESET 0000000000
1542 #define A2W_PLLD_DIG1R HW_REGISTER_RW( 0x7e102844 )
1543 #define A2W_PLLD_DIG1R_MASK 0x00ffffff
1544 #define A2W_PLLD_DIG1R_WIDTH 24
1545 #define A2W_PLLD_DIG1R_RESET 0x00004000
1546 #define A2W_PLLD_DIG2R HW_REGISTER_RW( 0x7e102848 )
1547 #define A2W_PLLD_DIG2R_MASK 0x00ffffff
1548 #define A2W_PLLD_DIG2R_WIDTH 24
1549 #define A2W_PLLD_DIG2R_RESET 0x00100401
1550 #define A2W_PLLD_DIG3R HW_REGISTER_RW( 0x7e10284c )
1551 #define A2W_PLLD_DIG3R_MASK 0x00ffffff
1552 #define A2W_PLLD_DIG3R_WIDTH 24
1553 #define A2W_PLLD_DIG3R_RESET 0x00000004
1554 #define A2W_PLLD_ANA0R HW_REGISTER_RW( 0x7e102850 )
1555 #define A2W_PLLD_ANA0R_MASK 0x00ffffff
1556 #define A2W_PLLD_ANA0R_WIDTH 24
1557 #define A2W_PLLD_ANA0R_RESET 0000000000
1558 #define A2W_PLLD_ANA1R HW_REGISTER_RW( 0x7e102854 )
1559 #define A2W_PLLD_ANA1R_MASK 0x00ffffff
1560 #define A2W_PLLD_ANA1R_WIDTH 24
1561 #define A2W_PLLD_ANA1R_RESET 0x001d0000
1562 #define A2W_PLLD_ANA2R HW_REGISTER_RW( 0x7e102858 )
1563 #define A2W_PLLD_ANA2R_MASK 0x00ffffff
1564 #define A2W_PLLD_ANA2R_WIDTH 24
1565 #define A2W_PLLD_ANA2R_RESET 0000000000
1566 #define A2W_PLLD_ANA3R HW_REGISTER_RW( 0x7e10285c )
1567 #define A2W_PLLD_ANA3R_MASK 0x00ffffff
1568 #define A2W_PLLD_ANA3R_WIDTH 24
1569 #define A2W_PLLD_ANA3R_RESET 0x00000180
1570 #define A2W_PLLH_DIG0R HW_REGISTER_RW( 0x7e102860 )
1571 #define A2W_PLLH_DIG0R_MASK 0x00ffffff
1572 #define A2W_PLLH_DIG0R_WIDTH 24
1573 #define A2W_PLLH_DIG0R_RESET 0000000000
1574 #define A2W_PLLH_DIG1R HW_REGISTER_RW( 0x7e102864 )
1575 #define A2W_PLLH_DIG1R_MASK 0x00ffffff
1576 #define A2W_PLLH_DIG1R_WIDTH 24
1577 #define A2W_PLLH_DIG1R_RESET 0000000000
1578 #define A2W_PLLH_DIG2R HW_REGISTER_RW( 0x7e102868 )
1579 #define A2W_PLLH_DIG2R_MASK 0x00ffffff
1580 #define A2W_PLLH_DIG2R_WIDTH 24
1581 #define A2W_PLLH_DIG2R_RESET 0x000000aa
1582 #define A2W_PLLH_DIG3R HW_REGISTER_RW( 0x7e10286c )
1583 #define A2W_PLLH_DIG3R_MASK 0x00ffffff
1584 #define A2W_PLLH_DIG3R_WIDTH 24
1585 #define A2W_PLLH_DIG3R_RESET 0000000000
1586 #define A2W_PLLH_ANA0R HW_REGISTER_RW( 0x7e102870 )
1587 #define A2W_PLLH_ANA0R_MASK 0x00ffffff
1588 #define A2W_PLLH_ANA0R_WIDTH 24
1589 #define A2W_PLLH_ANA0R_RESET 0x00d80000
1590 #define A2W_PLLH_ANA1R HW_REGISTER_RW( 0x7e102874 )
1591 #define A2W_PLLH_ANA1R_MASK 0x00ffffff
1592 #define A2W_PLLH_ANA1R_WIDTH 24
1593 #define A2W_PLLH_ANA1R_RESET 0x00000014
1594 #define A2W_PLLH_ANA2R HW_REGISTER_RW( 0x7e102878 )
1595 #define A2W_PLLH_ANA2R_MASK 0x00ffffff
1596 #define A2W_PLLH_ANA2R_WIDTH 24
1597 #define A2W_PLLH_ANA2R_RESET 0000000000
1598 #define A2W_PLLH_ANA3R HW_REGISTER_RW( 0x7e10287c )
1599 #define A2W_PLLH_ANA3R_MASK 0x00ffffff
1600 #define A2W_PLLH_ANA3R_WIDTH 24
1601 #define A2W_PLLH_ANA3R_RESET 0000000000
1602 #define A2W_HDMI_CTL0R HW_REGISTER_RW( 0x7e102880 )
1603 #define A2W_HDMI_CTL0R_MASK 0x00ffffff
1604 #define A2W_HDMI_CTL0R_WIDTH 24
1605 #define A2W_HDMI_CTL0R_RESET 0x00470238
1606 #define A2W_HDMI_CTL1R HW_REGISTER_RW( 0x7e102884 )
1607 #define A2W_HDMI_CTL1R_MASK 0x00ffffff
1608 #define A2W_HDMI_CTL1R_WIDTH 24
1609 #define A2W_HDMI_CTL1R_RESET 0x00011c00
1610 #define A2W_HDMI_CTL2R HW_REGISTER_RW( 0x7e102888 )
1611 #define A2W_HDMI_CTL2R_MASK 0x00ffffff
1612 #define A2W_HDMI_CTL2R_WIDTH 24
1613 #define A2W_HDMI_CTL2R_RESET 0x0018048e
1614 #define A2W_HDMI_CTL3R HW_REGISTER_RW( 0x7e10288c )
1615 #define A2W_HDMI_CTL3R_MASK 0x00ffffff
1616 #define A2W_HDMI_CTL3R_WIDTH 24
1617 #define A2W_HDMI_CTL3R_RESET 0x00000040
1618 #define A2W_XOSC0R HW_REGISTER_RW( 0x7e102890 )
1619 #define A2W_XOSC0R_MASK 0x00ffffff
1620 #define A2W_XOSC0R_WIDTH 24
1621 #define A2W_XOSC0R_RESET 0x00820080
1622 #define A2W_XOSC1R HW_REGISTER_RW( 0x7e102894 )
1623 #define A2W_XOSC1R_MASK 0x00ffffff
1624 #define A2W_XOSC1R_WIDTH 24
1625 #define A2W_XOSC1R_RESET 0x00000006
1626 #define A2W_SMPS_CTLA0R HW_REGISTER_RW( 0x7e1028a0 )
1627 #define A2W_SMPS_CTLA0R_MASK 0x00ffffff
1628 #define A2W_SMPS_CTLA0R_WIDTH 24
1629 #define A2W_SMPS_CTLA0R_RESET 0000000000
1630 #define A2W_SMPS_CTLA1R HW_REGISTER_RW( 0x7e1028a4 )
1631 #define A2W_SMPS_CTLA1R_MASK 0x00ffffff
1632 #define A2W_SMPS_CTLA1R_WIDTH 24
1633 #define A2W_SMPS_CTLA1R_RESET 0000000000
1634 #define A2W_SMPS_CTLA2R HW_REGISTER_RW( 0x7e1028a8 )
1635 #define A2W_SMPS_CTLA2R_MASK 0x00ffffff
1636 #define A2W_SMPS_CTLA2R_WIDTH 24
1637 #define A2W_SMPS_CTLA2R_RESET 0000000000
1638 #define A2W_SMPS_CTLB0R HW_REGISTER_RW( 0x7e1028b0 )
1639 #define A2W_SMPS_CTLB0R_MASK 0x00ffffff
1640 #define A2W_SMPS_CTLB0R_WIDTH 24
1641 #define A2W_SMPS_CTLB0R_RESET 0000000000
1642 #define A2W_SMPS_CTLB1R HW_REGISTER_RW( 0x7e1028b4 )
1643 #define A2W_SMPS_CTLB1R_MASK 0x00ffffff
1644 #define A2W_SMPS_CTLB1R_WIDTH 24
1645 #define A2W_SMPS_CTLB1R_RESET 0000000000
1646 #define A2W_SMPS_CTLB2R HW_REGISTER_RW( 0x7e1028b8 )
1647 #define A2W_SMPS_CTLB2R_MASK 0x00ffffff
1648 #define A2W_SMPS_CTLB2R_WIDTH 24
1649 #define A2W_SMPS_CTLB2R_RESET 0000000000
1650 #define A2W_SMPS_CTLC0R HW_REGISTER_RW( 0x7e1028c0 )
1651 #define A2W_SMPS_CTLC0R_MASK 0x00ffffff
1652 #define A2W_SMPS_CTLC0R_WIDTH 24
1653 #define A2W_SMPS_CTLC0R_RESET 0000000000
1654 #define A2W_SMPS_CTLC1R HW_REGISTER_RW( 0x7e1028c4 )
1655 #define A2W_SMPS_CTLC1R_MASK 0x00ffffff
1656 #define A2W_SMPS_CTLC1R_WIDTH 24
1657 #define A2W_SMPS_CTLC1R_RESET 0000000000
1658 #define A2W_SMPS_CTLC2R HW_REGISTER_RW( 0x7e1028c8 )
1659 #define A2W_SMPS_CTLC2R_MASK 0x00ffffff
1660 #define A2W_SMPS_CTLC2R_WIDTH 24
1661 #define A2W_SMPS_CTLC2R_RESET 0000000000
1662 #define A2W_SMPS_CTLC3R HW_REGISTER_RW( 0x7e1028cc )
1663 #define A2W_SMPS_CTLC3R_MASK 0x00ffffff
1664 #define A2W_SMPS_CTLC3R_WIDTH 24
1665 #define A2W_SMPS_CTLC3R_RESET 0000000000
1666 #define A2W_SMPS_LDO0R HW_REGISTER_RW( 0x7e1028d0 )
1667 #define A2W_SMPS_LDO0R_MASK 0x00ffffff
1668 #define A2W_SMPS_LDO0R_WIDTH 24
1669 #define A2W_SMPS_LDO0R_RESET 0000000000
1670 #define A2W_SMPS_LDO1R HW_REGISTER_RW( 0x7e1028d4 )
1671 #define A2W_SMPS_LDO1R_MASK 0x00ffffff
1672 #define A2W_SMPS_LDO1R_WIDTH 24
1673 #define A2W_SMPS_LDO1R_RESET 0000000000
1674 #define A2W_PLLA_CTRLR HW_REGISTER_RW( 0x7e102900 )
1675 #define A2W_PLLA_CTRLR_MASK 0x000373ff
1676 #define A2W_PLLA_CTRLR_WIDTH 18
1677 #define A2W_PLLA_CTRLR_RESET 0x00010000
1678 #define A2W_PLLA_FRACR HW_REGISTER_RW( 0x7e102a00 )
1679 #define A2W_PLLA_FRACR_MASK 0x000fffff
1680 #define A2W_PLLA_FRACR_WIDTH 20
1681 #define A2W_PLLA_FRACR_RESET 0000000000
1682 #define A2W_PLLA_DSI0R HW_REGISTER_RW( 0x7e102b00 )
1683 #define A2W_PLLA_DSI0R_MASK 0x000003ff
1684 #define A2W_PLLA_DSI0R_WIDTH 10
1685 #define A2W_PLLA_DSI0R_RESET 0x00000100
1686 #define A2W_PLLA_CORER HW_REGISTER_RW( 0x7e102c00 )
1687 #define A2W_PLLA_CORER_MASK 0x000003ff
1688 #define A2W_PLLA_CORER_WIDTH 10
1689 #define A2W_PLLA_CORER_RESET 0x00000100
1690 #define A2W_PLLA_PERR HW_REGISTER_RW( 0x7e102d00 )
1691 #define A2W_PLLA_PERR_MASK 0x000003ff
1692 #define A2W_PLLA_PERR_WIDTH 10
1693 #define A2W_PLLA_PERR_RESET 0x00000100
1694 #define A2W_PLLA_CCP2R HW_REGISTER_RW( 0x7e102e00 )
1695 #define A2W_PLLA_CCP2R_MASK 0x000003ff
1696 #define A2W_PLLA_CCP2R_WIDTH 10
1697 #define A2W_PLLA_CCP2R_RESET 0x00000100
1698 #define A2W_PLLA_MULTI HW_REGISTER_RW( 0x7e102f00 )
1699 #define A2W_PLLA_MULTI_MASK 0000000000
1700 #define A2W_PLLA_MULTI_WIDTH 0
1701 #define A2W_PLLA_MULTI_RESET 0000000000
1702 #define A2W_PLLB_CTRLR HW_REGISTER_RW( 0x7e1029e0 )
1703 #define A2W_PLLB_CTRLR_MASK 0x000373ff
1704 #define A2W_PLLB_CTRLR_WIDTH 18
1705 #define A2W_PLLB_CTRLR_RESET 0x00010000
1706 #define A2W_PLLB_FRACR HW_REGISTER_RW( 0x7e102ae0 )
1707 #define A2W_PLLB_FRACR_MASK 0x000fffff
1708 #define A2W_PLLB_FRACR_WIDTH 20
1709 #define A2W_PLLB_FRACR_RESET 0000000000
1710 #define A2W_PLLB_ARMR HW_REGISTER_RW( 0x7e102be0 )
1711 #define A2W_PLLB_ARMR_MASK 0x000003ff
1712 #define A2W_PLLB_ARMR_WIDTH 10
1713 #define A2W_PLLB_ARMR_RESET 0x00000100
1714 #define A2W_PLLB_SP0R HW_REGISTER_RW( 0x7e102ce0 )
1715 #define A2W_PLLB_SP0R_MASK 0x000003ff
1716 #define A2W_PLLB_SP0R_WIDTH 10
1717 #define A2W_PLLB_SP0R_RESET 0x00000100
1718 #define A2W_PLLB_SP1R HW_REGISTER_RW( 0x7e102de0 )
1719 #define A2W_PLLB_SP1R_MASK 0x000003ff
1720 #define A2W_PLLB_SP1R_WIDTH 10
1721 #define A2W_PLLB_SP1R_RESET 0x00000100
1722 #define A2W_PLLB_SP2R HW_REGISTER_RW( 0x7e102ee0 )
1723 #define A2W_PLLB_SP2R_MASK 0x000003ff
1724 #define A2W_PLLB_SP2R_WIDTH 10
1725 #define A2W_PLLB_SP2R_RESET 0x00000100
1726 #define A2W_PLLB_MULTI HW_REGISTER_RW( 0x7e102fe0 )
1727 #define A2W_PLLB_MULTI_MASK 0000000000
1728 #define A2W_PLLB_MULTI_WIDTH 0
1729 #define A2W_PLLB_MULTI_RESET 0000000000
1730 #define A2W_PLLC_CTRLR HW_REGISTER_RW( 0x7e102920 )
1731 #define A2W_PLLC_CTRLR_MASK 0x000373ff
1732 #define A2W_PLLC_CTRLR_WIDTH 18
1733 #define A2W_PLLC_CTRLR_RESET 0x00010000
1734 #define A2W_PLLC_FRACR HW_REGISTER_RW( 0x7e102a20 )
1735 #define A2W_PLLC_FRACR_MASK 0x000fffff
1736 #define A2W_PLLC_FRACR_WIDTH 20
1737 #define A2W_PLLC_FRACR_RESET 0000000000
1738 #define A2W_PLLC_CORE2R HW_REGISTER_RW( 0x7e102b20 )
1739 #define A2W_PLLC_CORE2R_MASK 0x000003ff
1740 #define A2W_PLLC_CORE2R_WIDTH 10
1741 #define A2W_PLLC_CORE2R_RESET 0x00000100
1742 #define A2W_PLLC_CORE1R HW_REGISTER_RW( 0x7e102c20 )
1743 #define A2W_PLLC_CORE1R_MASK 0x000003ff
1744 #define A2W_PLLC_CORE1R_WIDTH 10
1745 #define A2W_PLLC_CORE1R_RESET 0x00000100
1746 #define A2W_PLLC_PERR HW_REGISTER_RW( 0x7e102d20 )
1747 #define A2W_PLLC_PERR_MASK 0x000003ff
1748 #define A2W_PLLC_PERR_WIDTH 10
1749 #define A2W_PLLC_PERR_RESET 0x00000100
1750 #define A2W_PLLC_CORE0R HW_REGISTER_RW( 0x7e102e20 )
1751 #define A2W_PLLC_CORE0R_MASK 0x000003ff
1752 #define A2W_PLLC_CORE0R_WIDTH 10
1753 #define A2W_PLLC_CORE0R_RESET 0x00000100
1754 #define A2W_PLLC_MULTI HW_REGISTER_RW( 0x7e102f20 )
1755 #define A2W_PLLC_MULTI_MASK 0000000000
1756 #define A2W_PLLC_MULTI_WIDTH 0
1757 #define A2W_PLLC_MULTI_RESET 0000000000
1758 #define A2W_PLLD_CTRLR HW_REGISTER_RW( 0x7e102940 )
1759 #define A2W_PLLD_CTRLR_MASK 0x000373ff
1760 #define A2W_PLLD_CTRLR_WIDTH 18
1761 #define A2W_PLLD_CTRLR_RESET 0x00010000
1762 #define A2W_PLLD_FRACR HW_REGISTER_RW( 0x7e102a40 )
1763 #define A2W_PLLD_FRACR_MASK 0x000fffff
1764 #define A2W_PLLD_FRACR_WIDTH 20
1765 #define A2W_PLLD_FRACR_RESET 0000000000
1766 #define A2W_PLLD_DSI0R HW_REGISTER_RW( 0x7e102b40 )
1767 #define A2W_PLLD_DSI0R_MASK 0x000003ff
1768 #define A2W_PLLD_DSI0R_WIDTH 10
1769 #define A2W_PLLD_DSI0R_RESET 0x00000100
1770 #define A2W_PLLD_CORER HW_REGISTER_RW( 0x7e102c40 )
1771 #define A2W_PLLD_CORER_MASK 0x000003ff
1772 #define A2W_PLLD_CORER_WIDTH 10
1773 #define A2W_PLLD_CORER_RESET 0x00000100
1774 #define A2W_PLLD_PERR HW_REGISTER_RW( 0x7e102d40 )
1775 #define A2W_PLLD_PERR_MASK 0x000003ff
1776 #define A2W_PLLD_PERR_WIDTH 10
1777 #define A2W_PLLD_PERR_RESET 0x00000100
1778 #define A2W_PLLD_DSI1R HW_REGISTER_RW( 0x7e102e40 )
1779 #define A2W_PLLD_DSI1R_MASK 0x000003ff
1780 #define A2W_PLLD_DSI1R_WIDTH 10
1781 #define A2W_PLLD_DSI1R_RESET 0x00000100
1782 #define A2W_PLLD_MULTI HW_REGISTER_RW( 0x7e102f40 )
1783 #define A2W_PLLD_MULTI_MASK 0000000000
1784 #define A2W_PLLD_MULTI_WIDTH 0
1785 #define A2W_PLLD_MULTI_RESET 0000000000
1786 #define A2W_PLLH_CTRLR HW_REGISTER_RW( 0x7e102960 )
1787 #define A2W_PLLH_CTRLR_MASK 0x000370ff
1788 #define A2W_PLLH_CTRLR_WIDTH 18
1789 #define A2W_PLLH_CTRLR_RESET 0x00010000
1790 #define A2W_PLLH_FRACR HW_REGISTER_RW( 0x7e102a60 )
1791 #define A2W_PLLH_FRACR_MASK 0x000fffff
1792 #define A2W_PLLH_FRACR_WIDTH 20
1793 #define A2W_PLLH_FRACR_RESET 0000000000
1794 #define A2W_PLLH_AUXR HW_REGISTER_RW( 0x7e102b60 )
1795 #define A2W_PLLH_AUXR_MASK 0x000003ff
1796 #define A2W_PLLH_AUXR_WIDTH 10
1797 #define A2W_PLLH_AUXR_RESET 0x00000100
1798 #define A2W_PLLH_RCALR HW_REGISTER_RW( 0x7e102c60 )
1799 #define A2W_PLLH_RCALR_MASK 0x000003ff
1800 #define A2W_PLLH_RCALR_WIDTH 10
1801 #define A2W_PLLH_RCALR_RESET 0x00000100
1802 #define A2W_PLLH_PIXR HW_REGISTER_RW( 0x7e102d60 )
1803 #define A2W_PLLH_PIXR_MASK 0x000003ff
1804 #define A2W_PLLH_PIXR_WIDTH 10
1805 #define A2W_PLLH_PIXR_RESET 0x00000100
1806 #define A2W_PLLH_MULTI HW_REGISTER_RW( 0x7e102f60 )
1807 #define A2W_PLLH_MULTI_MASK 0000000000
1808 #define A2W_PLLH_MULTI_WIDTH 0
1809 #define A2W_PLLH_MULTI_RESET 0000000000
1810 #define A2W_SMPS_A_MODER HW_REGISTER_RW( 0x7e1029a0 )
1811 #define A2W_SMPS_A_MODER_MASK 0x00000001
1812 #define A2W_SMPS_A_MODER_WIDTH 1
1813 #define A2W_SMPS_A_MODER_RESET 0000000000
1814 #define A2W_SMPS_A_VOLTSR HW_REGISTER_RW( 0x7e102aa0 )
1815 #define A2W_SMPS_A_VOLTSR_MASK 0x0000001f
1816 #define A2W_SMPS_A_VOLTSR_WIDTH 5
1817 #define A2W_SMPS_A_VOLTSR_RESET 0000000000
1818 #define A2W_SMPS_A_GAINR HW_REGISTER_RW( 0x7e102ba0 )
1819 #define A2W_SMPS_A_GAINR_MASK 0x00000007
1820 #define A2W_SMPS_A_GAINR_WIDTH 3
1821 #define A2W_SMPS_A_GAINR_RESET 0000000000
1822 #define A2W_SMPS_A_MULTI HW_REGISTER_RW( 0x7e102fa0 )
1823 #define A2W_SMPS_A_MULTI_MASK 0000000000
1824 #define A2W_SMPS_A_MULTI_WIDTH 0
1825 #define A2W_SMPS_A_MULTI_RESET 0000000000
1826 #define A2W_SMPS_B_STATR HW_REGISTER_RW( 0x7e1029b0 )
1827 #define A2W_SMPS_B_STATR_MASK 0x0000111f
1828 #define A2W_SMPS_B_STATR_WIDTH 13
1829 #define A2W_SMPS_B_STATR_RESET 0000000000
1830 #define A2W_SMPS_B_MULTI HW_REGISTER_RW( 0x7e102fb0 )
1831 #define A2W_SMPS_B_MULTI_MASK 0000000000
1832 #define A2W_SMPS_B_MULTI_WIDTH 0
1833 #define A2W_SMPS_B_MULTI_RESET 0000000000
1834 #define A2W_SMPS_C_CLKR HW_REGISTER_RW( 0x7e1029c0 )
1835 #define A2W_SMPS_C_CLKR_MASK 0x0000000f
1836 #define A2W_SMPS_C_CLKR_WIDTH 4
1837 #define A2W_SMPS_C_CLKR_RESET 0000000000
1838 #define A2W_SMPS_C_CTLR HW_REGISTER_RW( 0x7e102ac0 )
1839 #define A2W_SMPS_C_CTLR_MASK 0x00000003
1840 #define A2W_SMPS_C_CTLR_WIDTH 2
1841 #define A2W_SMPS_C_CTLR_RESET 0000000000
1842 #define A2W_SMPS_C_MULTI HW_REGISTER_RW( 0x7e102fc0 )
1843 #define A2W_SMPS_C_MULTI_MASK 0000000000
1844 #define A2W_SMPS_C_MULTI_WIDTH 0
1845 #define A2W_SMPS_C_MULTI_RESET 0000000000
1846 #define A2W_SMPS_L_SPVR HW_REGISTER_RW( 0x7e1029d0 )
1847 #define A2W_SMPS_L_SPVR_MASK 0x0000001f
1848 #define A2W_SMPS_L_SPVR_WIDTH 5
1849 #define A2W_SMPS_L_SPVR_RESET 0000000000
1850 #define A2W_SMPS_L_SPAR HW_REGISTER_RW( 0x7e102ad0 )
1851 #define A2W_SMPS_L_SPAR_MASK 0x000003ff
1852 #define A2W_SMPS_L_SPAR_WIDTH 10
1853 #define A2W_SMPS_L_SPAR_RESET 0000000000
1854 #define A2W_SMPS_L_SCVR HW_REGISTER_RW( 0x7e102bd0 )
1855 #define A2W_SMPS_L_SCVR_MASK 0x0000001f
1856 #define A2W_SMPS_L_SCVR_WIDTH 5
1857 #define A2W_SMPS_L_SCVR_RESET 0000000000
1858 #define A2W_SMPS_L_SCAR HW_REGISTER_RW( 0x7e102cd0 )
1859 #define A2W_SMPS_L_SCAR_MASK 0x00000fff
1860 #define A2W_SMPS_L_SCAR_WIDTH 12
1861 #define A2W_SMPS_L_SCAR_RESET 0000000000
1862 #define A2W_SMPS_L_SIVR HW_REGISTER_RW( 0x7e102dd0 )
1863 #define A2W_SMPS_L_SIVR_MASK 0x0000001f
1864 #define A2W_SMPS_L_SIVR_WIDTH 5
1865 #define A2W_SMPS_L_SIVR_RESET 0000000000
1866 #define A2W_SMPS_L_SIAR HW_REGISTER_RW( 0x7e102ed0 )
1867 #define A2W_SMPS_L_SIAR_MASK 0x000003ff
1868 #define A2W_SMPS_L_SIAR_WIDTH 10
1869 #define A2W_SMPS_L_SIAR_RESET 0000000000
1870 #define A2W_SMPS_L_MULTI HW_REGISTER_RW( 0x7e102fd0 )
1871 #define A2W_SMPS_L_MULTI_MASK 0000000000
1872 #define A2W_SMPS_L_MULTI_WIDTH 0
1873 #define A2W_SMPS_L_MULTI_RESET 0000000000
1874 #define A2W_XOSC_CTRLR HW_REGISTER_RW( 0x7e102990 )
1875 #define A2W_XOSC_CTRLR_MASK 0x000000ff
1876 #define A2W_XOSC_CTRLR_WIDTH 8
1877 #define A2W_XOSC_CTRLR_RESET 0000000000
1878 #define A2W_XOSC_CPRR HW_REGISTER_RW( 0x7e102a90 )
1879 #define A2W_XOSC_CPRR_MASK 0x00000013
1880 #define A2W_XOSC_CPRR_WIDTH 5
1881 #define A2W_XOSC_CPRR_RESET 0000000000
1882 #define A2W_XOSC_BIASR HW_REGISTER_RW( 0x7e102b90 )
1883 #define A2W_XOSC_BIASR_MASK 0x0000001f
1884 #define A2W_XOSC_BIASR_WIDTH 5
1885 #define A2W_XOSC_BIASR_RESET 0x00000018
1886 #define A2W_XOSC_PWRR HW_REGISTER_RW( 0x7e102c90 )
1887 #define A2W_XOSC_PWRR_MASK 0x00000007
1888 #define A2W_XOSC_PWRR_WIDTH 3
1889 #define A2W_XOSC_PWRR_RESET 0x00000004
1890 #define A2W_XOSC_MULTI HW_REGISTER_RW( 0x7e102f90 )
1891 #define A2W_XOSC_MULTI_MASK 0000000000
1892 #define A2W_XOSC_MULTI_WIDTH 0
1893 #define A2W_XOSC_MULTI_RESET 0000000000
1894 #define A2W_PLLA_ANA_SSCSR HW_REGISTER_RW( 0x7e102910 )
1895 #define A2W_PLLA_ANA_SSCSR_MASK 0x0001ffff
1896 #define A2W_PLLA_ANA_SSCSR_WIDTH 17
1897 #define A2W_PLLA_ANA_SSCSR_RESET 0000000000
1898 #define A2W_PLLA_ANA_SSCLR HW_REGISTER_RW( 0x7e102a10 )
1899 #define A2W_PLLA_ANA_SSCLR_MASK 0x0001ffff
1900 #define A2W_PLLA_ANA_SSCLR_WIDTH 17
1901 #define A2W_PLLA_ANA_SSCLR_RESET 0000000000
1902 #define A2W_PLLA_ANA_KAIPR HW_REGISTER_RW( 0x7e102b10 )
1903 #define A2W_PLLA_ANA_KAIPR_MASK 0x0000077f
1904 #define A2W_PLLA_ANA_KAIPR_WIDTH 11
1905 #define A2W_PLLA_ANA_KAIPR_RESET 0x0000033a
1906 #define A2W_PLLA_ANA_STATR HW_REGISTER_RW( 0x7e102c10 )
1907 #define A2W_PLLA_ANA_STATR_MASK 0x00000fff
1908 #define A2W_PLLA_ANA_STATR_WIDTH 12
1909 #define A2W_PLLA_ANA_STATR_RESET 0000000000
1910 #define A2W_PLLA_ANA_SCTLR HW_REGISTER_RW( 0x7e102d10 )
1911 #define A2W_PLLA_ANA_SCTLR_MASK 0x0000001f
1912 #define A2W_PLLA_ANA_SCTLR_WIDTH 5
1913 #define A2W_PLLA_ANA_SCTLR_RESET 0000000000
1914 #define A2W_PLLA_ANA_VCOR HW_REGISTER_RW( 0x7e102e10 )
1915 #define A2W_PLLA_ANA_VCOR_MASK 0x00000001
1916 #define A2W_PLLA_ANA_VCOR_WIDTH 1
1917 #define A2W_PLLA_ANA_VCOR_RESET 0000000000
1918 #define A2W_PLLA_ANA_MULTI HW_REGISTER_RW( 0x7e102f10 )
1919 #define A2W_PLLA_ANA_MULTI_MASK 0000000000
1920 #define A2W_PLLA_ANA_MULTI_WIDTH 0
1921 #define A2W_PLLA_ANA_MULTI_RESET 0000000000
1922 #define A2W_PLLB_ANA_SSCSR HW_REGISTER_RW( 0x7e1029f0 )
1923 #define A2W_PLLB_ANA_SSCSR_MASK 0x0001ffff
1924 #define A2W_PLLB_ANA_SSCSR_WIDTH 17
1925 #define A2W_PLLB_ANA_SSCSR_RESET 0000000000
1926 #define A2W_PLLB_ANA_SSCLR HW_REGISTER_RW( 0x7e102af0 )
1927 #define A2W_PLLB_ANA_SSCLR_MASK 0x0001ffff
1928 #define A2W_PLLB_ANA_SSCLR_WIDTH 17
1929 #define A2W_PLLB_ANA_SSCLR_RESET 0000000000
1930 #define A2W_PLLB_ANA_KAIPR HW_REGISTER_RW( 0x7e102bf0 )
1931 #define A2W_PLLB_ANA_KAIPR_MASK 0x0000077f
1932 #define A2W_PLLB_ANA_KAIPR_WIDTH 11
1933 #define A2W_PLLB_ANA_KAIPR_RESET 0x0000033a
1934 #define A2W_PLLB_ANA_STATR HW_REGISTER_RW( 0x7e102cf0 )
1935 #define A2W_PLLB_ANA_STATR_MASK 0x00000fff
1936 #define A2W_PLLB_ANA_STATR_WIDTH 12
1937 #define A2W_PLLB_ANA_STATR_RESET 0000000000
1938 #define A2W_PLLB_ANA_SCTLR HW_REGISTER_RW( 0x7e102df0 )
1939 #define A2W_PLLB_ANA_SCTLR_MASK 0x0000001f
1940 #define A2W_PLLB_ANA_SCTLR_WIDTH 5
1941 #define A2W_PLLB_ANA_SCTLR_RESET 0000000000
1942 #define A2W_PLLB_ANA_VCOR HW_REGISTER_RW( 0x7e102ef0 )
1943 #define A2W_PLLB_ANA_VCOR_MASK 0x00000001
1944 #define A2W_PLLB_ANA_VCOR_WIDTH 1
1945 #define A2W_PLLB_ANA_VCOR_RESET 0000000000
1946 #define A2W_PLLB_ANA_MULTI HW_REGISTER_RW( 0x7e102ff0 )
1947 #define A2W_PLLB_ANA_MULTI_MASK 0000000000
1948 #define A2W_PLLB_ANA_MULTI_WIDTH 0
1949 #define A2W_PLLB_ANA_MULTI_RESET 0000000000
1950 #define A2W_PLLC_ANA_SSCSR HW_REGISTER_RW( 0x7e102930 )
1951 #define A2W_PLLC_ANA_SSCSR_MASK 0x0001ffff
1952 #define A2W_PLLC_ANA_SSCSR_WIDTH 17
1953 #define A2W_PLLC_ANA_SSCSR_RESET 0000000000
1954 #define A2W_PLLC_ANA_SSCLR HW_REGISTER_RW( 0x7e102a30 )
1955 #define A2W_PLLC_ANA_SSCLR_MASK 0x0001ffff
1956 #define A2W_PLLC_ANA_SSCLR_WIDTH 17
1957 #define A2W_PLLC_ANA_SSCLR_RESET 0000000000
1958 #define A2W_PLLC_ANA_KAIPR HW_REGISTER_RW( 0x7e102b30 )
1959 #define A2W_PLLC_ANA_KAIPR_MASK 0x0000077f
1960 #define A2W_PLLC_ANA_KAIPR_WIDTH 11
1961 #define A2W_PLLC_ANA_KAIPR_RESET 0x0000033a
1962 #define A2W_PLLC_ANA_STATR HW_REGISTER_RW( 0x7e102c30 )
1963 #define A2W_PLLC_ANA_STATR_MASK 0x00000fff
1964 #define A2W_PLLC_ANA_STATR_WIDTH 12
1965 #define A2W_PLLC_ANA_STATR_RESET 0000000000
1966 #define A2W_PLLC_ANA_SCTLR HW_REGISTER_RW( 0x7e102d30 )
1967 #define A2W_PLLC_ANA_SCTLR_MASK 0x0000001f
1968 #define A2W_PLLC_ANA_SCTLR_WIDTH 5
1969 #define A2W_PLLC_ANA_SCTLR_RESET 0000000000
1970 #define A2W_PLLC_ANA_VCOR HW_REGISTER_RW( 0x7e102e30 )
1971 #define A2W_PLLC_ANA_VCOR_MASK 0x00000001
1972 #define A2W_PLLC_ANA_VCOR_WIDTH 1
1973 #define A2W_PLLC_ANA_VCOR_RESET 0000000000
1974 #define A2W_PLLC_ANA_MULTI HW_REGISTER_RW( 0x7e102f30 )
1975 #define A2W_PLLC_ANA_MULTI_MASK 0000000000
1976 #define A2W_PLLC_ANA_MULTI_WIDTH 0
1977 #define A2W_PLLC_ANA_MULTI_RESET 0000000000
1978 #define A2W_PLLD_ANA_SSCSR HW_REGISTER_RW( 0x7e102950 )
1979 #define A2W_PLLD_ANA_SSCSR_MASK 0x0001ffff
1980 #define A2W_PLLD_ANA_SSCSR_WIDTH 17
1981 #define A2W_PLLD_ANA_SSCSR_RESET 0000000000
1982 #define A2W_PLLD_ANA_SSCLR HW_REGISTER_RW( 0x7e102a50 )
1983 #define A2W_PLLD_ANA_SSCLR_MASK 0x0001ffff
1984 #define A2W_PLLD_ANA_SSCLR_WIDTH 17
1985 #define A2W_PLLD_ANA_SSCLR_RESET 0000000000
1986 #define A2W_PLLD_ANA_KAIPR HW_REGISTER_RW( 0x7e102b50 )
1987 #define A2W_PLLD_ANA_KAIPR_MASK 0x0000077f
1988 #define A2W_PLLD_ANA_KAIPR_WIDTH 11
1989 #define A2W_PLLD_ANA_KAIPR_RESET 0x0000033a
1990 #define A2W_PLLD_ANA_STATR HW_REGISTER_RW( 0x7e102c50 )
1991 #define A2W_PLLD_ANA_STATR_MASK 0x00000fff
1992 #define A2W_PLLD_ANA_STATR_WIDTH 12
1993 #define A2W_PLLD_ANA_STATR_RESET 0000000000
1994 #define A2W_PLLD_ANA_SCTLR HW_REGISTER_RW( 0x7e102d50 )
1995 #define A2W_PLLD_ANA_SCTLR_MASK 0x0000001f
1996 #define A2W_PLLD_ANA_SCTLR_WIDTH 5
1997 #define A2W_PLLD_ANA_SCTLR_RESET 0000000000
1998 #define A2W_PLLD_ANA_VCOR HW_REGISTER_RW( 0x7e102e50 )
1999 #define A2W_PLLD_ANA_VCOR_MASK 0x00000001
2000 #define A2W_PLLD_ANA_VCOR_WIDTH 1
2001 #define A2W_PLLD_ANA_VCOR_RESET 0000000000
2002 #define A2W_PLLD_ANA_MULTI HW_REGISTER_RW( 0x7e102f50 )
2003 #define A2W_PLLD_ANA_MULTI_MASK 0000000000
2004 #define A2W_PLLD_ANA_MULTI_WIDTH 0
2005 #define A2W_PLLD_ANA_MULTI_RESET 0000000000
2006 #define A2W_PLLH_ANA_KAIPR HW_REGISTER_RW( 0x7e102b70 )
2007 #define A2W_PLLH_ANA_KAIPR_MASK 0x0000077f
2008 #define A2W_PLLH_ANA_KAIPR_WIDTH 11
2009 #define A2W_PLLH_ANA_KAIPR_RESET 0x0000033a
2010 #define A2W_PLLH_ANA_STATR HW_REGISTER_RW( 0x7e102e60 )
2011 #define A2W_PLLH_ANA_STATR_MASK 0x001f1fff
2012 #define A2W_PLLH_ANA_STATR_WIDTH 21
2013 #define A2W_PLLH_ANA_STATR_RESET 0000000000
2014 #define A2W_PLLH_ANA_SCTLR HW_REGISTER_RW( 0x7e102d70 )
2015 #define A2W_PLLH_ANA_SCTLR_MASK 0x0000001f
2016 #define A2W_PLLH_ANA_SCTLR_WIDTH 5
2017 #define A2W_PLLH_ANA_SCTLR_RESET 0000000000
2018 #define A2W_PLLH_ANA_VCOR HW_REGISTER_RW( 0x7e102e70 )
2019 #define A2W_PLLH_ANA_VCOR_MASK 0x00000001
2020 #define A2W_PLLH_ANA_VCOR_WIDTH 1
2021 #define A2W_PLLH_ANA_VCOR_RESET 0000000000
2022 #define A2W_PLLH_ANA_MULTI HW_REGISTER_RW( 0x7e102f70 )
2023 #define A2W_PLLH_ANA_MULTI_MASK 0000000000
2024 #define A2W_PLLH_ANA_MULTI_WIDTH 0
2025 #define A2W_PLLH_ANA_MULTI_RESET 0000000000
2026 #define A2W_HDMI_CTL_RCALR HW_REGISTER_RW( 0x7e102980 )
2027 #define A2W_HDMI_CTL_RCALR_MASK 0x00011f33
2028 #define A2W_HDMI_CTL_RCALR_WIDTH 17
2029 #define A2W_HDMI_CTL_RCALR_RESET 0x00010000
2030 #define A2W_HDMI_CTL_HFENR HW_REGISTER_RW( 0x7e102a80 )
2031 #define A2W_HDMI_CTL_HFENR_MASK 0x00000001
2032 #define A2W_HDMI_CTL_HFENR_WIDTH 1
2033 #define A2W_HDMI_CTL_HFENR_RESET 0000000000
2034 #define A2W_HDMI_CTL_MULTI HW_REGISTER_RW( 0x7e102f80 )
2035 #define A2W_HDMI_CTL_MULTI_MASK 0000000000
2036 #define A2W_HDMI_CTL_MULTI_WIDTH 0
2037 #define A2W_HDMI_CTL_MULTI_RESET 0000000000
This page took 0.300346 seconds and 3 git commands to generate.