Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / cpr_clkman_a0.h
1 #ifndef __BCM2708A0__
2
3
4 #define CM_SMPSCTL HW_REGISTER_RW( 0x7e1010b8 )
5 #define CM_SMPSCTL_MASK 0x000000f3
6 #define CM_SMPSCTL_WIDTH 8
7 #define CM_SMPSCTL_RESET 0000000000
8 #define CM_SMPSCTL_BUSY_BITS 7:7
9 #define CM_SMPSCTL_BUSY_SET 0x00000080
10 #define CM_SMPSCTL_BUSY_CLR 0xffffff7f
11 #define CM_SMPSCTL_BUSY_MSB 7
12 #define CM_SMPSCTL_BUSY_LSB 7
13 #define CM_SMPSCTL_GATE_BITS 6:6
14 #define CM_SMPSCTL_GATE_SET 0x00000040
15 #define CM_SMPSCTL_GATE_CLR 0xffffffbf
16 #define CM_SMPSCTL_GATE_MSB 6
17 #define CM_SMPSCTL_GATE_LSB 6
18 #define CM_SMPSCTL_KILL_BITS 5:5
19 #define CM_SMPSCTL_KILL_SET 0x00000020
20 #define CM_SMPSCTL_KILL_CLR 0xffffffdf
21 #define CM_SMPSCTL_KILL_MSB 5
22 #define CM_SMPSCTL_KILL_LSB 5
23 #define CM_SMPSCTL_ENAB_BITS 4:4
24 #define CM_SMPSCTL_ENAB_SET 0x00000010
25 #define CM_SMPSCTL_ENAB_CLR 0xffffffef
26 #define CM_SMPSCTL_ENAB_MSB 4
27 #define CM_SMPSCTL_ENAB_LSB 4
28 #define CM_SMPSCTL_SRC_BITS 1:0
29 #define CM_SMPSCTL_SRC_SET 0x00000003
30 #define CM_SMPSCTL_SRC_CLR 0xfffffffc
31 #define CM_SMPSCTL_SRC_MSB 1
32 #define CM_SMPSCTL_SRC_LSB 0
33 #define CM_SMPSDIV HW_REGISTER_RW( 0x7e1010bc )
34 #define CM_SMPSDIV_MASK 0x00007000
35 #define CM_SMPSDIV_WIDTH 15
36 #define CM_SMPSDIV_RESET 0000000000
37 #define CM_SMPSDIV_DIV_BITS 14:12
38 #define CM_SMPSDIV_DIV_SET 0x00007000
39 #define CM_SMPSDIV_DIV_CLR 0xffff8fff
40 #define CM_SMPSDIV_DIV_MSB 14
41 #define CM_SMPSDIV_DIV_LSB 12
42
43
44 // This file was generated by the create_regs script
45 #define CM_PASSWORD 0x5a000000
46 #define CM_BASE 0x7e101000
47 #define CM_APB_ID 0x0000636d
48 #define CM_GNRICCTL HW_REGISTER_RW( 0x7e101000 )
49 #define CM_GNRICCTL_MASK 0x000fffff
50 #define CM_GNRICCTL_WIDTH 20
51 #define CM_GNRICCTL_RESET 0000000000
52 #define CM_GNRICCTL_FLIP_BITS 11:11
53 #define CM_GNRICCTL_FLIP_SET 0x00000800
54 #define CM_GNRICCTL_FLIP_CLR 0xfffff7ff
55 #define CM_GNRICCTL_FLIP_MSB 11
56 #define CM_GNRICCTL_FLIP_LSB 11
57 #define CM_GNRICCTL_MASH_BITS 10:9
58 #define CM_GNRICCTL_MASH_SET 0x00000600
59 #define CM_GNRICCTL_MASH_CLR 0xfffff9ff
60 #define CM_GNRICCTL_MASH_MSB 10
61 #define CM_GNRICCTL_MASH_LSB 9
62 #define CM_GNRICCTL_BUSYD_BITS 8:8
63 #define CM_GNRICCTL_BUSYD_SET 0x00000100
64 #define CM_GNRICCTL_BUSYD_CLR 0xfffffeff
65 #define CM_GNRICCTL_BUSYD_MSB 8
66 #define CM_GNRICCTL_BUSYD_LSB 8
67 #define CM_GNRICCTL_BUSY_BITS 7:7
68 #define CM_GNRICCTL_BUSY_SET 0x00000080
69 #define CM_GNRICCTL_BUSY_CLR 0xffffff7f
70 #define CM_GNRICCTL_BUSY_MSB 7
71 #define CM_GNRICCTL_BUSY_LSB 7
72 #define CM_GNRICCTL_GATE_BITS 6:6
73 #define CM_GNRICCTL_GATE_SET 0x00000040
74 #define CM_GNRICCTL_GATE_CLR 0xffffffbf
75 #define CM_GNRICCTL_GATE_MSB 6
76 #define CM_GNRICCTL_GATE_LSB 6
77 #define CM_GNRICCTL_KILL_BITS 5:5
78 #define CM_GNRICCTL_KILL_SET 0x00000020
79 #define CM_GNRICCTL_KILL_CLR 0xffffffdf
80 #define CM_GNRICCTL_KILL_MSB 5
81 #define CM_GNRICCTL_KILL_LSB 5
82 #define CM_GNRICCTL_ENAB_BITS 4:4
83 #define CM_GNRICCTL_ENAB_SET 0x00000010
84 #define CM_GNRICCTL_ENAB_CLR 0xffffffef
85 #define CM_GNRICCTL_ENAB_MSB 4
86 #define CM_GNRICCTL_ENAB_LSB 4
87 #define CM_GNRICCTL_SRC_BITS 3:0
88 #define CM_GNRICCTL_SRC_SET 0x0000000f
89 #define CM_GNRICCTL_SRC_CLR 0xfffffff0
90 #define CM_GNRICCTL_SRC_MSB 3
91 #define CM_GNRICCTL_SRC_LSB 0
92 #define CM_GNRICDIV HW_REGISTER_RW( 0x7e101004 )
93 #define CM_GNRICDIV_MASK 0x00ffffff
94 #define CM_GNRICDIV_WIDTH 24
95 #define CM_GNRICDIV_RESET 0000000000
96 #define CM_GNRICDIV_DIV_BITS 23:0
97 #define CM_GNRICDIV_DIV_SET 0x00ffffff
98 #define CM_GNRICDIV_DIV_CLR 0xff000000
99 #define CM_GNRICDIV_DIV_MSB 23
100 #define CM_GNRICDIV_DIV_LSB 0
101 #define CM_VPUCTL HW_REGISTER_RW( 0x7e101008 )
102 #define CM_VPUCTL_MASK 0x000003cf
103 #define CM_VPUCTL_WIDTH 10
104 #define CM_VPUCTL_RESET 0x00000041
105 #define CM_VPUCTL_FRAC_BITS 9:9
106 #define CM_VPUCTL_FRAC_SET 0x00000200
107 #define CM_VPUCTL_FRAC_CLR 0xfffffdff
108 #define CM_VPUCTL_FRAC_MSB 9
109 #define CM_VPUCTL_FRAC_LSB 9
110 #define CM_VPUCTL_BUSYD_BITS 8:8
111 #define CM_VPUCTL_BUSYD_SET 0x00000100
112 #define CM_VPUCTL_BUSYD_CLR 0xfffffeff
113 #define CM_VPUCTL_BUSYD_MSB 8
114 #define CM_VPUCTL_BUSYD_LSB 8
115 #define CM_VPUCTL_BUSY_BITS 7:7
116 #define CM_VPUCTL_BUSY_SET 0x00000080
117 #define CM_VPUCTL_BUSY_CLR 0xffffff7f
118 #define CM_VPUCTL_BUSY_MSB 7
119 #define CM_VPUCTL_BUSY_LSB 7
120 #define CM_VPUCTL_GATE_BITS 6:6
121 #define CM_VPUCTL_GATE_SET 0x00000040
122 #define CM_VPUCTL_GATE_CLR 0xffffffbf
123 #define CM_VPUCTL_GATE_MSB 6
124 #define CM_VPUCTL_GATE_LSB 6
125 #define CM_VPUCTL_SRC_BITS 3:0
126 #define CM_VPUCTL_SRC_SET 0x0000000f
127 #define CM_VPUCTL_SRC_CLR 0xfffffff0
128 #define CM_VPUCTL_SRC_MSB 3
129 #define CM_VPUCTL_SRC_LSB 0
130 #define CM_VPUDIV HW_REGISTER_RW( 0x7e10100c )
131 #define CM_VPUDIV_MASK 0x00fffff0
132 #define CM_VPUDIV_WIDTH 24
133 #define CM_VPUDIV_RESET 0x00001000
134 #define CM_VPUDIV_DIV_BITS 23:4
135 #define CM_VPUDIV_DIV_SET 0x00fffff0
136 #define CM_VPUDIV_DIV_CLR 0xff00000f
137 #define CM_VPUDIV_DIV_MSB 23
138 #define CM_VPUDIV_DIV_LSB 4
139 #define CM_SYSCTL HW_REGISTER_RW( 0x7e101010 )
140 #define CM_SYSCTL_MASK 0x00000040
141 #define CM_SYSCTL_WIDTH 7
142 #define CM_SYSCTL_RESET 0x00000040
143 #define CM_SYSCTL_GATE_BITS 6:6
144 #define CM_SYSCTL_GATE_SET 0x00000040
145 #define CM_SYSCTL_GATE_CLR 0xffffffbf
146 #define CM_SYSCTL_GATE_MSB 6
147 #define CM_SYSCTL_GATE_LSB 6
148 #define CM_SYSDIV HW_REGISTER_RO( 0x7e101014 )
149 #define CM_SYSDIV_MASK 0x00001000
150 #define CM_SYSDIV_WIDTH 13
151 #define CM_SYSDIV_RESET 0x00001000
152 #define CM_SYSDIV_DIV_BITS 12:12
153 #define CM_SYSDIV_DIV_SET 0x00001000
154 #define CM_SYSDIV_DIV_CLR 0xffffefff
155 #define CM_SYSDIV_DIV_MSB 12
156 #define CM_SYSDIV_DIV_LSB 12
157 #define CM_PERIACTL HW_REGISTER_RW( 0x7e101018 )
158 #define CM_PERIACTL_MASK 0x00000040
159 #define CM_PERIACTL_WIDTH 7
160 #define CM_PERIACTL_RESET 0x00000040
161 #define CM_PERIACTL_GATE_BITS 6:6
162 #define CM_PERIACTL_GATE_SET 0x00000040
163 #define CM_PERIACTL_GATE_CLR 0xffffffbf
164 #define CM_PERIACTL_GATE_MSB 6
165 #define CM_PERIACTL_GATE_LSB 6
166 #define CM_PERIADIV HW_REGISTER_RO( 0x7e10101c )
167 #define CM_PERIADIV_MASK 0x00001000
168 #define CM_PERIADIV_WIDTH 13
169 #define CM_PERIADIV_RESET 0x00001000
170 #define CM_PERIADIV_DIV_BITS 12:12
171 #define CM_PERIADIV_DIV_SET 0x00001000
172 #define CM_PERIADIV_DIV_CLR 0xffffefff
173 #define CM_PERIADIV_DIV_MSB 12
174 #define CM_PERIADIV_DIV_LSB 12
175 #define CM_PERIICTL HW_REGISTER_RW( 0x7e101020 )
176 #define CM_PERIICTL_MASK 0x00000040
177 #define CM_PERIICTL_WIDTH 7
178 #define CM_PERIICTL_RESET 0000000000
179 #define CM_PERIICTL_GATE_BITS 6:6
180 #define CM_PERIICTL_GATE_SET 0x00000040
181 #define CM_PERIICTL_GATE_CLR 0xffffffbf
182 #define CM_PERIICTL_GATE_MSB 6
183 #define CM_PERIICTL_GATE_LSB 6
184 #define CM_PERIIDIV HW_REGISTER_RO( 0x7e101024 )
185 #define CM_PERIIDIV_MASK 0x00001000
186 #define CM_PERIIDIV_WIDTH 13
187 #define CM_PERIIDIV_RESET 0x00001000
188 #define CM_PERIIDIV_DIV_BITS 12:12
189 #define CM_PERIIDIV_DIV_SET 0x00001000
190 #define CM_PERIIDIV_DIV_CLR 0xffffefff
191 #define CM_PERIIDIV_DIV_MSB 12
192 #define CM_PERIIDIV_DIV_LSB 12
193 #define CM_H264CTL HW_REGISTER_RW( 0x7e101028 )
194 #define CM_H264CTL_MASK 0x000003ff
195 #define CM_H264CTL_WIDTH 10
196 #define CM_H264CTL_RESET 0x00000040
197 #define CM_H264CTL_FRAC_BITS 9:9
198 #define CM_H264CTL_FRAC_SET 0x00000200
199 #define CM_H264CTL_FRAC_CLR 0xfffffdff
200 #define CM_H264CTL_FRAC_MSB 9
201 #define CM_H264CTL_FRAC_LSB 9
202 #define CM_H264CTL_BUSYD_BITS 8:8
203 #define CM_H264CTL_BUSYD_SET 0x00000100
204 #define CM_H264CTL_BUSYD_CLR 0xfffffeff
205 #define CM_H264CTL_BUSYD_MSB 8
206 #define CM_H264CTL_BUSYD_LSB 8
207 #define CM_H264CTL_BUSY_BITS 7:7
208 #define CM_H264CTL_BUSY_SET 0x00000080
209 #define CM_H264CTL_BUSY_CLR 0xffffff7f
210 #define CM_H264CTL_BUSY_MSB 7
211 #define CM_H264CTL_BUSY_LSB 7
212 #define CM_H264CTL_GATE_BITS 6:6
213 #define CM_H264CTL_GATE_SET 0x00000040
214 #define CM_H264CTL_GATE_CLR 0xffffffbf
215 #define CM_H264CTL_GATE_MSB 6
216 #define CM_H264CTL_GATE_LSB 6
217 #define CM_H264CTL_KILL_BITS 5:5
218 #define CM_H264CTL_KILL_SET 0x00000020
219 #define CM_H264CTL_KILL_CLR 0xffffffdf
220 #define CM_H264CTL_KILL_MSB 5
221 #define CM_H264CTL_KILL_LSB 5
222 #define CM_H264CTL_ENAB_BITS 4:4
223 #define CM_H264CTL_ENAB_SET 0x00000010
224 #define CM_H264CTL_ENAB_CLR 0xffffffef
225 #define CM_H264CTL_ENAB_MSB 4
226 #define CM_H264CTL_ENAB_LSB 4
227 #define CM_H264CTL_SRC_BITS 3:0
228 #define CM_H264CTL_SRC_SET 0x0000000f
229 #define CM_H264CTL_SRC_CLR 0xfffffff0
230 #define CM_H264CTL_SRC_MSB 3
231 #define CM_H264CTL_SRC_LSB 0
232 #define CM_H264DIV HW_REGISTER_RW( 0x7e10102c )
233 #define CM_H264DIV_MASK 0x0000fff0
234 #define CM_H264DIV_WIDTH 16
235 #define CM_H264DIV_RESET 0000000000
236 #define CM_H264DIV_DIV_BITS 15:4
237 #define CM_H264DIV_DIV_SET 0x0000fff0
238 #define CM_H264DIV_DIV_CLR 0xffff000f
239 #define CM_H264DIV_DIV_MSB 15
240 #define CM_H264DIV_DIV_LSB 4
241 #define CM_ISPCTL HW_REGISTER_RW( 0x7e101030 )
242 #define CM_ISPCTL_MASK 0x000003ff
243 #define CM_ISPCTL_WIDTH 10
244 #define CM_ISPCTL_RESET 0x00000040
245 #define CM_ISPCTL_FRAC_BITS 9:9
246 #define CM_ISPCTL_FRAC_SET 0x00000200
247 #define CM_ISPCTL_FRAC_CLR 0xfffffdff
248 #define CM_ISPCTL_FRAC_MSB 9
249 #define CM_ISPCTL_FRAC_LSB 9
250 #define CM_ISPCTL_BUSYD_BITS 8:8
251 #define CM_ISPCTL_BUSYD_SET 0x00000100
252 #define CM_ISPCTL_BUSYD_CLR 0xfffffeff
253 #define CM_ISPCTL_BUSYD_MSB 8
254 #define CM_ISPCTL_BUSYD_LSB 8
255 #define CM_ISPCTL_BUSY_BITS 7:7
256 #define CM_ISPCTL_BUSY_SET 0x00000080
257 #define CM_ISPCTL_BUSY_CLR 0xffffff7f
258 #define CM_ISPCTL_BUSY_MSB 7
259 #define CM_ISPCTL_BUSY_LSB 7
260 #define CM_ISPCTL_GATE_BITS 6:6
261 #define CM_ISPCTL_GATE_SET 0x00000040
262 #define CM_ISPCTL_GATE_CLR 0xffffffbf
263 #define CM_ISPCTL_GATE_MSB 6
264 #define CM_ISPCTL_GATE_LSB 6
265 #define CM_ISPCTL_KILL_BITS 5:5
266 #define CM_ISPCTL_KILL_SET 0x00000020
267 #define CM_ISPCTL_KILL_CLR 0xffffffdf
268 #define CM_ISPCTL_KILL_MSB 5
269 #define CM_ISPCTL_KILL_LSB 5
270 #define CM_ISPCTL_ENAB_BITS 4:4
271 #define CM_ISPCTL_ENAB_SET 0x00000010
272 #define CM_ISPCTL_ENAB_CLR 0xffffffef
273 #define CM_ISPCTL_ENAB_MSB 4
274 #define CM_ISPCTL_ENAB_LSB 4
275 #define CM_ISPCTL_SRC_BITS 3:0
276 #define CM_ISPCTL_SRC_SET 0x0000000f
277 #define CM_ISPCTL_SRC_CLR 0xfffffff0
278 #define CM_ISPCTL_SRC_MSB 3
279 #define CM_ISPCTL_SRC_LSB 0
280 #define CM_ISPDIV HW_REGISTER_RW( 0x7e101034 )
281 #define CM_ISPDIV_MASK 0x0000fff0
282 #define CM_ISPDIV_WIDTH 16
283 #define CM_ISPDIV_RESET 0000000000
284 #define CM_ISPDIV_DIV_BITS 15:4
285 #define CM_ISPDIV_DIV_SET 0x0000fff0
286 #define CM_ISPDIV_DIV_CLR 0xffff000f
287 #define CM_ISPDIV_DIV_MSB 15
288 #define CM_ISPDIV_DIV_LSB 4
289 #define CM_ARMCTL HW_REGISTER_RW( 0x7e1011b0 )
290 #define CM_ARMCTL_MASK 0x000013bf
291 #define CM_ARMCTL_WIDTH 13
292 #define CM_ARMCTL_RESET 0x00000004
293 #define CM_ARMCTL_AXIHALF_BITS 12:12
294 #define CM_ARMCTL_AXIHALF_SET 0x00001000
295 #define CM_ARMCTL_AXIHALF_CLR 0xffffefff
296 #define CM_ARMCTL_AXIHALF_MSB 12
297 #define CM_ARMCTL_AXIHALF_LSB 12
298 #define CM_ARMCTL_FRAC_BITS 9:9
299 #define CM_ARMCTL_FRAC_SET 0x00000200
300 #define CM_ARMCTL_FRAC_CLR 0xfffffdff
301 #define CM_ARMCTL_FRAC_MSB 9
302 #define CM_ARMCTL_FRAC_LSB 9
303 #define CM_ARMCTL_BUSYD_BITS 8:8
304 #define CM_ARMCTL_BUSYD_SET 0x00000100
305 #define CM_ARMCTL_BUSYD_CLR 0xfffffeff
306 #define CM_ARMCTL_BUSYD_MSB 8
307 #define CM_ARMCTL_BUSYD_LSB 8
308 #define CM_ARMCTL_BUSY_BITS 7:7
309 #define CM_ARMCTL_BUSY_SET 0x00000080
310 #define CM_ARMCTL_BUSY_CLR 0xffffff7f
311 #define CM_ARMCTL_BUSY_MSB 7
312 #define CM_ARMCTL_BUSY_LSB 7
313 #define CM_ARMCTL_KILL_BITS 5:5
314 #define CM_ARMCTL_KILL_SET 0x00000020
315 #define CM_ARMCTL_KILL_CLR 0xffffffdf
316 #define CM_ARMCTL_KILL_MSB 5
317 #define CM_ARMCTL_KILL_LSB 5
318 #define CM_ARMCTL_ENAB_BITS 4:4
319 #define CM_ARMCTL_ENAB_SET 0x00000010
320 #define CM_ARMCTL_ENAB_CLR 0xffffffef
321 #define CM_ARMCTL_ENAB_MSB 4
322 #define CM_ARMCTL_ENAB_LSB 4
323 #define CM_ARMCTL_SRC_BITS 3:0
324 #define CM_ARMCTL_SRC_SET 0x0000000f
325 #define CM_ARMCTL_SRC_CLR 0xfffffff0
326 #define CM_ARMCTL_SRC_MSB 3
327 #define CM_ARMCTL_SRC_LSB 0
328 #define CM_ARMDIV HW_REGISTER_RO( 0x7e1011b4 )
329 #define CM_ARMDIV_MASK 0x00001000
330 #define CM_ARMDIV_WIDTH 13
331 #define CM_ARMDIV_RESET 0x00001000
332 #define CM_ARMDIV_DIV_BITS 12:12
333 #define CM_ARMDIV_DIV_SET 0x00001000
334 #define CM_ARMDIV_DIV_CLR 0xffffefff
335 #define CM_ARMDIV_DIV_MSB 12
336 #define CM_ARMDIV_DIV_LSB 12
337 #define CM_SDCCTL HW_REGISTER_RW( 0x7e1011a8 )
338 #define CM_SDCCTL_MASK 0x0003f3bf
339 #define CM_SDCCTL_WIDTH 18
340 #define CM_SDCCTL_RESET 0x00004000
341 #define CM_SDCCTL_UPDATE_BITS 17:17
342 #define CM_SDCCTL_UPDATE_SET 0x00020000
343 #define CM_SDCCTL_UPDATE_CLR 0xfffdffff
344 #define CM_SDCCTL_UPDATE_MSB 17
345 #define CM_SDCCTL_UPDATE_LSB 17
346 #define CM_SDCCTL_ACCPT_BITS 16:16
347 #define CM_SDCCTL_ACCPT_SET 0x00010000
348 #define CM_SDCCTL_ACCPT_CLR 0xfffeffff
349 #define CM_SDCCTL_ACCPT_MSB 16
350 #define CM_SDCCTL_ACCPT_LSB 16
351 #define CM_SDCCTL_CTRL_BITS 15:12
352 #define CM_SDCCTL_CTRL_SET 0x0000f000
353 #define CM_SDCCTL_CTRL_CLR 0xffff0fff
354 #define CM_SDCCTL_CTRL_MSB 15
355 #define CM_SDCCTL_CTRL_LSB 12
356 #define CM_SDCCTL_FRAC_BITS 9:9
357 #define CM_SDCCTL_FRAC_SET 0x00000200
358 #define CM_SDCCTL_FRAC_CLR 0xfffffdff
359 #define CM_SDCCTL_FRAC_MSB 9
360 #define CM_SDCCTL_FRAC_LSB 9
361 #define CM_SDCCTL_BUSYD_BITS 8:8
362 #define CM_SDCCTL_BUSYD_SET 0x00000100
363 #define CM_SDCCTL_BUSYD_CLR 0xfffffeff
364 #define CM_SDCCTL_BUSYD_MSB 8
365 #define CM_SDCCTL_BUSYD_LSB 8
366 #define CM_SDCCTL_BUSY_BITS 7:7
367 #define CM_SDCCTL_BUSY_SET 0x00000080
368 #define CM_SDCCTL_BUSY_CLR 0xffffff7f
369 #define CM_SDCCTL_BUSY_MSB 7
370 #define CM_SDCCTL_BUSY_LSB 7
371 #define CM_SDCCTL_KILL_BITS 5:5
372 #define CM_SDCCTL_KILL_SET 0x00000020
373 #define CM_SDCCTL_KILL_CLR 0xffffffdf
374 #define CM_SDCCTL_KILL_MSB 5
375 #define CM_SDCCTL_KILL_LSB 5
376 #define CM_SDCCTL_ENAB_BITS 4:4
377 #define CM_SDCCTL_ENAB_SET 0x00000010
378 #define CM_SDCCTL_ENAB_CLR 0xffffffef
379 #define CM_SDCCTL_ENAB_MSB 4
380 #define CM_SDCCTL_ENAB_LSB 4
381 #define CM_SDCCTL_SRC_BITS 3:0
382 #define CM_SDCCTL_SRC_SET 0x0000000f
383 #define CM_SDCCTL_SRC_CLR 0xfffffff0
384 #define CM_SDCCTL_SRC_MSB 3
385 #define CM_SDCCTL_SRC_LSB 0
386 #define CM_SDCDIV HW_REGISTER_RW( 0x7e1011ac )
387 #define CM_SDCDIV_MASK 0x0003f000
388 #define CM_SDCDIV_WIDTH 18
389 #define CM_SDCDIV_RESET 0000000000
390 #define CM_SDCDIV_DIV_BITS 17:12
391 #define CM_SDCDIV_DIV_SET 0x0003f000
392 #define CM_SDCDIV_DIV_CLR 0xfffc0fff
393 #define CM_SDCDIV_DIV_MSB 17
394 #define CM_SDCDIV_DIV_LSB 12
395 #define CM_V3DCTL HW_REGISTER_RW( 0x7e101038 )
396 #define CM_V3DCTL_MASK 0x000003ff
397 #define CM_V3DCTL_WIDTH 10
398 #define CM_V3DCTL_RESET 0x00000040
399 #define CM_V3DCTL_FRAC_BITS 9:9
400 #define CM_V3DCTL_FRAC_SET 0x00000200
401 #define CM_V3DCTL_FRAC_CLR 0xfffffdff
402 #define CM_V3DCTL_FRAC_MSB 9
403 #define CM_V3DCTL_FRAC_LSB 9
404 #define CM_V3DCTL_BUSYD_BITS 8:8
405 #define CM_V3DCTL_BUSYD_SET 0x00000100
406 #define CM_V3DCTL_BUSYD_CLR 0xfffffeff
407 #define CM_V3DCTL_BUSYD_MSB 8
408 #define CM_V3DCTL_BUSYD_LSB 8
409 #define CM_V3DCTL_BUSY_BITS 7:7
410 #define CM_V3DCTL_BUSY_SET 0x00000080
411 #define CM_V3DCTL_BUSY_CLR 0xffffff7f
412 #define CM_V3DCTL_BUSY_MSB 7
413 #define CM_V3DCTL_BUSY_LSB 7
414 #define CM_V3DCTL_GATE_BITS 6:6
415 #define CM_V3DCTL_GATE_SET 0x00000040
416 #define CM_V3DCTL_GATE_CLR 0xffffffbf
417 #define CM_V3DCTL_GATE_MSB 6
418 #define CM_V3DCTL_GATE_LSB 6
419 #define CM_V3DCTL_KILL_BITS 5:5
420 #define CM_V3DCTL_KILL_SET 0x00000020
421 #define CM_V3DCTL_KILL_CLR 0xffffffdf
422 #define CM_V3DCTL_KILL_MSB 5
423 #define CM_V3DCTL_KILL_LSB 5
424 #define CM_V3DCTL_ENAB_BITS 4:4
425 #define CM_V3DCTL_ENAB_SET 0x00000010
426 #define CM_V3DCTL_ENAB_CLR 0xffffffef
427 #define CM_V3DCTL_ENAB_MSB 4
428 #define CM_V3DCTL_ENAB_LSB 4
429 #define CM_V3DCTL_SRC_BITS 3:0
430 #define CM_V3DCTL_SRC_SET 0x0000000f
431 #define CM_V3DCTL_SRC_CLR 0xfffffff0
432 #define CM_V3DCTL_SRC_MSB 3
433 #define CM_V3DCTL_SRC_LSB 0
434 #define CM_V3DDIV HW_REGISTER_RW( 0x7e10103c )
435 #define CM_V3DDIV_MASK 0x0000fff0
436 #define CM_V3DDIV_WIDTH 16
437 #define CM_V3DDIV_RESET 0000000000
438 #define CM_V3DDIV_DIV_BITS 15:4
439 #define CM_V3DDIV_DIV_SET 0x0000fff0
440 #define CM_V3DDIV_DIV_CLR 0xffff000f
441 #define CM_V3DDIV_DIV_MSB 15
442 #define CM_V3DDIV_DIV_LSB 4
443 #define CM_CAM0CTL HW_REGISTER_RW( 0x7e101040 )
444 #define CM_CAM0CTL_MASK 0x000003bf
445 #define CM_CAM0CTL_WIDTH 10
446 #define CM_CAM0CTL_RESET 0000000000
447 #define CM_CAM0CTL_FRAC_BITS 9:9
448 #define CM_CAM0CTL_FRAC_SET 0x00000200
449 #define CM_CAM0CTL_FRAC_CLR 0xfffffdff
450 #define CM_CAM0CTL_FRAC_MSB 9
451 #define CM_CAM0CTL_FRAC_LSB 9
452 #define CM_CAM0CTL_BUSYD_BITS 8:8
453 #define CM_CAM0CTL_BUSYD_SET 0x00000100
454 #define CM_CAM0CTL_BUSYD_CLR 0xfffffeff
455 #define CM_CAM0CTL_BUSYD_MSB 8
456 #define CM_CAM0CTL_BUSYD_LSB 8
457 #define CM_CAM0CTL_BUSY_BITS 7:7
458 #define CM_CAM0CTL_BUSY_SET 0x00000080
459 #define CM_CAM0CTL_BUSY_CLR 0xffffff7f
460 #define CM_CAM0CTL_BUSY_MSB 7
461 #define CM_CAM0CTL_BUSY_LSB 7
462 #define CM_CAM0CTL_KILL_BITS 5:5
463 #define CM_CAM0CTL_KILL_SET 0x00000020
464 #define CM_CAM0CTL_KILL_CLR 0xffffffdf
465 #define CM_CAM0CTL_KILL_MSB 5
466 #define CM_CAM0CTL_KILL_LSB 5
467 #define CM_CAM0CTL_ENAB_BITS 4:4
468 #define CM_CAM0CTL_ENAB_SET 0x00000010
469 #define CM_CAM0CTL_ENAB_CLR 0xffffffef
470 #define CM_CAM0CTL_ENAB_MSB 4
471 #define CM_CAM0CTL_ENAB_LSB 4
472 #define CM_CAM0CTL_SRC_BITS 3:0
473 #define CM_CAM0CTL_SRC_SET 0x0000000f
474 #define CM_CAM0CTL_SRC_CLR 0xfffffff0
475 #define CM_CAM0CTL_SRC_MSB 3
476 #define CM_CAM0CTL_SRC_LSB 0
477 #define CM_CAM0DIV HW_REGISTER_RW( 0x7e101044 )
478 #define CM_CAM0DIV_MASK 0x0000fff0
479 #define CM_CAM0DIV_WIDTH 16
480 #define CM_CAM0DIV_RESET 0000000000
481 #define CM_CAM0DIV_DIV_BITS 15:4
482 #define CM_CAM0DIV_DIV_SET 0x0000fff0
483 #define CM_CAM0DIV_DIV_CLR 0xffff000f
484 #define CM_CAM0DIV_DIV_MSB 15
485 #define CM_CAM0DIV_DIV_LSB 4
486 #define CM_CAM1CTL HW_REGISTER_RW( 0x7e101048 )
487 #define CM_CAM1CTL_MASK 0x000003bf
488 #define CM_CAM1CTL_WIDTH 10
489 #define CM_CAM1CTL_RESET 0000000000
490 #define CM_CAM1CTL_FRAC_BITS 9:9
491 #define CM_CAM1CTL_FRAC_SET 0x00000200
492 #define CM_CAM1CTL_FRAC_CLR 0xfffffdff
493 #define CM_CAM1CTL_FRAC_MSB 9
494 #define CM_CAM1CTL_FRAC_LSB 9
495 #define CM_CAM1CTL_BUSYD_BITS 8:8
496 #define CM_CAM1CTL_BUSYD_SET 0x00000100
497 #define CM_CAM1CTL_BUSYD_CLR 0xfffffeff
498 #define CM_CAM1CTL_BUSYD_MSB 8
499 #define CM_CAM1CTL_BUSYD_LSB 8
500 #define CM_CAM1CTL_BUSY_BITS 7:7
501 #define CM_CAM1CTL_BUSY_SET 0x00000080
502 #define CM_CAM1CTL_BUSY_CLR 0xffffff7f
503 #define CM_CAM1CTL_BUSY_MSB 7
504 #define CM_CAM1CTL_BUSY_LSB 7
505 #define CM_CAM1CTL_KILL_BITS 5:5
506 #define CM_CAM1CTL_KILL_SET 0x00000020
507 #define CM_CAM1CTL_KILL_CLR 0xffffffdf
508 #define CM_CAM1CTL_KILL_MSB 5
509 #define CM_CAM1CTL_KILL_LSB 5
510 #define CM_CAM1CTL_ENAB_BITS 4:4
511 #define CM_CAM1CTL_ENAB_SET 0x00000010
512 #define CM_CAM1CTL_ENAB_CLR 0xffffffef
513 #define CM_CAM1CTL_ENAB_MSB 4
514 #define CM_CAM1CTL_ENAB_LSB 4
515 #define CM_CAM1CTL_SRC_BITS 3:0
516 #define CM_CAM1CTL_SRC_SET 0x0000000f
517 #define CM_CAM1CTL_SRC_CLR 0xfffffff0
518 #define CM_CAM1CTL_SRC_MSB 3
519 #define CM_CAM1CTL_SRC_LSB 0
520 #define CM_CAM1DIV HW_REGISTER_RW( 0x7e10104c )
521 #define CM_CAM1DIV_MASK 0x0000fff0
522 #define CM_CAM1DIV_WIDTH 16
523 #define CM_CAM1DIV_RESET 0000000000
524 #define CM_CAM1DIV_DIV_BITS 15:4
525 #define CM_CAM1DIV_DIV_SET 0x0000fff0
526 #define CM_CAM1DIV_DIV_CLR 0xffff000f
527 #define CM_CAM1DIV_DIV_MSB 15
528 #define CM_CAM1DIV_DIV_LSB 4
529 #define CM_CCP2CTL HW_REGISTER_RW( 0x7e101050 )
530 #define CM_CCP2CTL_MASK 0x00000397
531 #define CM_CCP2CTL_WIDTH 10
532 #define CM_CCP2CTL_RESET 0000000000
533 #define CM_CCP2CTL_FRAC_BITS 9:9
534 #define CM_CCP2CTL_FRAC_SET 0x00000200
535 #define CM_CCP2CTL_FRAC_CLR 0xfffffdff
536 #define CM_CCP2CTL_FRAC_MSB 9
537 #define CM_CCP2CTL_FRAC_LSB 9
538 #define CM_CCP2CTL_BUSYD_BITS 8:8
539 #define CM_CCP2CTL_BUSYD_SET 0x00000100
540 #define CM_CCP2CTL_BUSYD_CLR 0xfffffeff
541 #define CM_CCP2CTL_BUSYD_MSB 8
542 #define CM_CCP2CTL_BUSYD_LSB 8
543 #define CM_CCP2CTL_BUSY_BITS 7:7
544 #define CM_CCP2CTL_BUSY_SET 0x00000080
545 #define CM_CCP2CTL_BUSY_CLR 0xffffff7f
546 #define CM_CCP2CTL_BUSY_MSB 7
547 #define CM_CCP2CTL_BUSY_LSB 7
548 #define CM_CCP2CTL_ENAB_BITS 4:4
549 #define CM_CCP2CTL_ENAB_SET 0x00000010
550 #define CM_CCP2CTL_ENAB_CLR 0xffffffef
551 #define CM_CCP2CTL_ENAB_MSB 4
552 #define CM_CCP2CTL_ENAB_LSB 4
553 #define CM_CCP2CTL_SRC_BITS 2:0
554 #define CM_CCP2CTL_SRC_SET 0x00000007
555 #define CM_CCP2CTL_SRC_CLR 0xfffffff8
556 #define CM_CCP2CTL_SRC_MSB 2
557 #define CM_CCP2CTL_SRC_LSB 0
558 #define CM_CCP2DIV HW_REGISTER_RO( 0x7e101054 )
559 #define CM_CCP2DIV_MASK 0x00001000
560 #define CM_CCP2DIV_WIDTH 13
561 #define CM_CCP2DIV_RESET 0x00001000
562 #define CM_CCP2DIV_DIV_BITS 12:12
563 #define CM_CCP2DIV_DIV_SET 0x00001000
564 #define CM_CCP2DIV_DIV_CLR 0xffffefff
565 #define CM_CCP2DIV_DIV_MSB 12
566 #define CM_CCP2DIV_DIV_LSB 12
567 #define CM_DSI0ECTL HW_REGISTER_RW( 0x7e101058 )
568 #define CM_DSI0ECTL_MASK 0x000003bf
569 #define CM_DSI0ECTL_WIDTH 10
570 #define CM_DSI0ECTL_RESET 0000000000
571 #define CM_DSI0ECTL_FRAC_BITS 9:9
572 #define CM_DSI0ECTL_FRAC_SET 0x00000200
573 #define CM_DSI0ECTL_FRAC_CLR 0xfffffdff
574 #define CM_DSI0ECTL_FRAC_MSB 9
575 #define CM_DSI0ECTL_FRAC_LSB 9
576 #define CM_DSI0ECTL_BUSYD_BITS 8:8
577 #define CM_DSI0ECTL_BUSYD_SET 0x00000100
578 #define CM_DSI0ECTL_BUSYD_CLR 0xfffffeff
579 #define CM_DSI0ECTL_BUSYD_MSB 8
580 #define CM_DSI0ECTL_BUSYD_LSB 8
581 #define CM_DSI0ECTL_BUSY_BITS 7:7
582 #define CM_DSI0ECTL_BUSY_SET 0x00000080
583 #define CM_DSI0ECTL_BUSY_CLR 0xffffff7f
584 #define CM_DSI0ECTL_BUSY_MSB 7
585 #define CM_DSI0ECTL_BUSY_LSB 7
586 #define CM_DSI0ECTL_KILL_BITS 5:5
587 #define CM_DSI0ECTL_KILL_SET 0x00000020
588 #define CM_DSI0ECTL_KILL_CLR 0xffffffdf
589 #define CM_DSI0ECTL_KILL_MSB 5
590 #define CM_DSI0ECTL_KILL_LSB 5
591 #define CM_DSI0ECTL_ENAB_BITS 4:4
592 #define CM_DSI0ECTL_ENAB_SET 0x00000010
593 #define CM_DSI0ECTL_ENAB_CLR 0xffffffef
594 #define CM_DSI0ECTL_ENAB_MSB 4
595 #define CM_DSI0ECTL_ENAB_LSB 4
596 #define CM_DSI0ECTL_SRC_BITS 3:0
597 #define CM_DSI0ECTL_SRC_SET 0x0000000f
598 #define CM_DSI0ECTL_SRC_CLR 0xfffffff0
599 #define CM_DSI0ECTL_SRC_MSB 3
600 #define CM_DSI0ECTL_SRC_LSB 0
601 #define CM_DSI0EDIV HW_REGISTER_RW( 0x7e10105c )
602 #define CM_DSI0EDIV_MASK 0x0000fff0
603 #define CM_DSI0EDIV_WIDTH 16
604 #define CM_DSI0EDIV_RESET 0000000000
605 #define CM_DSI0EDIV_DIV_BITS 15:4
606 #define CM_DSI0EDIV_DIV_SET 0x0000fff0
607 #define CM_DSI0EDIV_DIV_CLR 0xffff000f
608 #define CM_DSI0EDIV_DIV_MSB 15
609 #define CM_DSI0EDIV_DIV_LSB 4
610 #define CM_DSI0PCTL HW_REGISTER_RW( 0x7e101060 )
611 #define CM_DSI0PCTL_MASK 0x0000039f
612 #define CM_DSI0PCTL_WIDTH 10
613 #define CM_DSI0PCTL_RESET 0000000000
614 #define CM_DSI0PCTL_FRAC_BITS 9:9
615 #define CM_DSI0PCTL_FRAC_SET 0x00000200
616 #define CM_DSI0PCTL_FRAC_CLR 0xfffffdff
617 #define CM_DSI0PCTL_FRAC_MSB 9
618 #define CM_DSI0PCTL_FRAC_LSB 9
619 #define CM_DSI0PCTL_BUSYD_BITS 8:8
620 #define CM_DSI0PCTL_BUSYD_SET 0x00000100
621 #define CM_DSI0PCTL_BUSYD_CLR 0xfffffeff
622 #define CM_DSI0PCTL_BUSYD_MSB 8
623 #define CM_DSI0PCTL_BUSYD_LSB 8
624 #define CM_DSI0PCTL_BUSY_BITS 7:7
625 #define CM_DSI0PCTL_BUSY_SET 0x00000080
626 #define CM_DSI0PCTL_BUSY_CLR 0xffffff7f
627 #define CM_DSI0PCTL_BUSY_MSB 7
628 #define CM_DSI0PCTL_BUSY_LSB 7
629 #define CM_DSI0PCTL_ENAB_BITS 4:4
630 #define CM_DSI0PCTL_ENAB_SET 0x00000010
631 #define CM_DSI0PCTL_ENAB_CLR 0xffffffef
632 #define CM_DSI0PCTL_ENAB_MSB 4
633 #define CM_DSI0PCTL_ENAB_LSB 4
634 #define CM_DSI0PCTL_SRC_BITS 3:0
635 #define CM_DSI0PCTL_SRC_SET 0x0000000f
636 #define CM_DSI0PCTL_SRC_CLR 0xfffffff0
637 #define CM_DSI0PCTL_SRC_MSB 3
638 #define CM_DSI0PCTL_SRC_LSB 0
639 #define CM_DSI0PDIV HW_REGISTER_RO( 0x7e101064 )
640 #define CM_DSI0PDIV_MASK 0x00001000
641 #define CM_DSI0PDIV_WIDTH 13
642 #define CM_DSI0PDIV_RESET 0x00001000
643 #define CM_DSI0PDIV_DIV_BITS 12:12
644 #define CM_DSI0PDIV_DIV_SET 0x00001000
645 #define CM_DSI0PDIV_DIV_CLR 0xffffefff
646 #define CM_DSI0PDIV_DIV_MSB 12
647 #define CM_DSI0PDIV_DIV_LSB 12
648 #define CM_DSI1ECTL HW_REGISTER_RW( 0x7e101158 )
649 #define CM_DSI1ECTL_MASK 0x000003bf
650 #define CM_DSI1ECTL_WIDTH 10
651 #define CM_DSI1ECTL_RESET 0000000000
652 #define CM_DSI1ECTL_FRAC_BITS 9:9
653 #define CM_DSI1ECTL_FRAC_SET 0x00000200
654 #define CM_DSI1ECTL_FRAC_CLR 0xfffffdff
655 #define CM_DSI1ECTL_FRAC_MSB 9
656 #define CM_DSI1ECTL_FRAC_LSB 9
657 #define CM_DSI1ECTL_BUSYD_BITS 8:8
658 #define CM_DSI1ECTL_BUSYD_SET 0x00000100
659 #define CM_DSI1ECTL_BUSYD_CLR 0xfffffeff
660 #define CM_DSI1ECTL_BUSYD_MSB 8
661 #define CM_DSI1ECTL_BUSYD_LSB 8
662 #define CM_DSI1ECTL_BUSY_BITS 7:7
663 #define CM_DSI1ECTL_BUSY_SET 0x00000080
664 #define CM_DSI1ECTL_BUSY_CLR 0xffffff7f
665 #define CM_DSI1ECTL_BUSY_MSB 7
666 #define CM_DSI1ECTL_BUSY_LSB 7
667 #define CM_DSI1ECTL_KILL_BITS 5:5
668 #define CM_DSI1ECTL_KILL_SET 0x00000020
669 #define CM_DSI1ECTL_KILL_CLR 0xffffffdf
670 #define CM_DSI1ECTL_KILL_MSB 5
671 #define CM_DSI1ECTL_KILL_LSB 5
672 #define CM_DSI1ECTL_ENAB_BITS 4:4
673 #define CM_DSI1ECTL_ENAB_SET 0x00000010
674 #define CM_DSI1ECTL_ENAB_CLR 0xffffffef
675 #define CM_DSI1ECTL_ENAB_MSB 4
676 #define CM_DSI1ECTL_ENAB_LSB 4
677 #define CM_DSI1ECTL_SRC_BITS 3:0
678 #define CM_DSI1ECTL_SRC_SET 0x0000000f
679 #define CM_DSI1ECTL_SRC_CLR 0xfffffff0
680 #define CM_DSI1ECTL_SRC_MSB 3
681 #define CM_DSI1ECTL_SRC_LSB 0
682 #define CM_DSI1EDIV HW_REGISTER_RW( 0x7e10115c )
683 #define CM_DSI1EDIV_MASK 0x0000fff0
684 #define CM_DSI1EDIV_WIDTH 16
685 #define CM_DSI1EDIV_RESET 0000000000
686 #define CM_DSI1EDIV_DIV_BITS 15:4
687 #define CM_DSI1EDIV_DIV_SET 0x0000fff0
688 #define CM_DSI1EDIV_DIV_CLR 0xffff000f
689 #define CM_DSI1EDIV_DIV_MSB 15
690 #define CM_DSI1EDIV_DIV_LSB 4
691 #define CM_DSI1PCTL HW_REGISTER_RW( 0x7e101160 )
692 #define CM_DSI1PCTL_MASK 0x0000039f
693 #define CM_DSI1PCTL_WIDTH 10
694 #define CM_DSI1PCTL_RESET 0000000000
695 #define CM_DSI1PCTL_FRAC_BITS 9:9
696 #define CM_DSI1PCTL_FRAC_SET 0x00000200
697 #define CM_DSI1PCTL_FRAC_CLR 0xfffffdff
698 #define CM_DSI1PCTL_FRAC_MSB 9
699 #define CM_DSI1PCTL_FRAC_LSB 9
700 #define CM_DSI1PCTL_BUSYD_BITS 8:8
701 #define CM_DSI1PCTL_BUSYD_SET 0x00000100
702 #define CM_DSI1PCTL_BUSYD_CLR 0xfffffeff
703 #define CM_DSI1PCTL_BUSYD_MSB 8
704 #define CM_DSI1PCTL_BUSYD_LSB 8
705 #define CM_DSI1PCTL_BUSY_BITS 7:7
706 #define CM_DSI1PCTL_BUSY_SET 0x00000080
707 #define CM_DSI1PCTL_BUSY_CLR 0xffffff7f
708 #define CM_DSI1PCTL_BUSY_MSB 7
709 #define CM_DSI1PCTL_BUSY_LSB 7
710 #define CM_DSI1PCTL_ENAB_BITS 4:4
711 #define CM_DSI1PCTL_ENAB_SET 0x00000010
712 #define CM_DSI1PCTL_ENAB_CLR 0xffffffef
713 #define CM_DSI1PCTL_ENAB_MSB 4
714 #define CM_DSI1PCTL_ENAB_LSB 4
715 #define CM_DSI1PCTL_SRC_BITS 3:0
716 #define CM_DSI1PCTL_SRC_SET 0x0000000f
717 #define CM_DSI1PCTL_SRC_CLR 0xfffffff0
718 #define CM_DSI1PCTL_SRC_MSB 3
719 #define CM_DSI1PCTL_SRC_LSB 0
720 #define CM_DSI1PDIV HW_REGISTER_RO( 0x7e101164 )
721 #define CM_DSI1PDIV_MASK 0x00001000
722 #define CM_DSI1PDIV_WIDTH 13
723 #define CM_DSI1PDIV_RESET 0x00001000
724 #define CM_DSI1PDIV_DIV_BITS 12:12
725 #define CM_DSI1PDIV_DIV_SET 0x00001000
726 #define CM_DSI1PDIV_DIV_CLR 0xffffefff
727 #define CM_DSI1PDIV_DIV_MSB 12
728 #define CM_DSI1PDIV_DIV_LSB 12
729 #define CM_DPICTL HW_REGISTER_RW( 0x7e101068 )
730 #define CM_DPICTL_MASK 0x000003bf
731 #define CM_DPICTL_WIDTH 10
732 #define CM_DPICTL_RESET 0000000000
733 #define CM_DPICTL_FRAC_BITS 9:9
734 #define CM_DPICTL_FRAC_SET 0x00000200
735 #define CM_DPICTL_FRAC_CLR 0xfffffdff
736 #define CM_DPICTL_FRAC_MSB 9
737 #define CM_DPICTL_FRAC_LSB 9
738 #define CM_DPICTL_BUSYD_BITS 8:8
739 #define CM_DPICTL_BUSYD_SET 0x00000100
740 #define CM_DPICTL_BUSYD_CLR 0xfffffeff
741 #define CM_DPICTL_BUSYD_MSB 8
742 #define CM_DPICTL_BUSYD_LSB 8
743 #define CM_DPICTL_BUSY_BITS 7:7
744 #define CM_DPICTL_BUSY_SET 0x00000080
745 #define CM_DPICTL_BUSY_CLR 0xffffff7f
746 #define CM_DPICTL_BUSY_MSB 7
747 #define CM_DPICTL_BUSY_LSB 7
748 #define CM_DPICTL_KILL_BITS 5:5
749 #define CM_DPICTL_KILL_SET 0x00000020
750 #define CM_DPICTL_KILL_CLR 0xffffffdf
751 #define CM_DPICTL_KILL_MSB 5
752 #define CM_DPICTL_KILL_LSB 5
753 #define CM_DPICTL_ENAB_BITS 4:4
754 #define CM_DPICTL_ENAB_SET 0x00000010
755 #define CM_DPICTL_ENAB_CLR 0xffffffef
756 #define CM_DPICTL_ENAB_MSB 4
757 #define CM_DPICTL_ENAB_LSB 4
758 #define CM_DPICTL_SRC_BITS 3:0
759 #define CM_DPICTL_SRC_SET 0x0000000f
760 #define CM_DPICTL_SRC_CLR 0xfffffff0
761 #define CM_DPICTL_SRC_MSB 3
762 #define CM_DPICTL_SRC_LSB 0
763 #define CM_DPIDIV HW_REGISTER_RW( 0x7e10106c )
764 #define CM_DPIDIV_MASK 0x0000fff0
765 #define CM_DPIDIV_WIDTH 16
766 #define CM_DPIDIV_RESET 0000000000
767 #define CM_DPIDIV_DIV_BITS 15:4
768 #define CM_DPIDIV_DIV_SET 0x0000fff0
769 #define CM_DPIDIV_DIV_CLR 0xffff000f
770 #define CM_DPIDIV_DIV_MSB 15
771 #define CM_DPIDIV_DIV_LSB 4
772 #define CM_DFTCTL HW_REGISTER_RW( 0x7e101168 )
773 #define CM_DFTCTL_MASK 0x000003bf
774 #define CM_DFTCTL_WIDTH 10
775 #define CM_DFTCTL_RESET 0000000000
776 #define CM_DFTCTL_FRAC_BITS 9:9
777 #define CM_DFTCTL_FRAC_SET 0x00000200
778 #define CM_DFTCTL_FRAC_CLR 0xfffffdff
779 #define CM_DFTCTL_FRAC_MSB 9
780 #define CM_DFTCTL_FRAC_LSB 9
781 #define CM_DFTCTL_BUSYD_BITS 8:8
782 #define CM_DFTCTL_BUSYD_SET 0x00000100
783 #define CM_DFTCTL_BUSYD_CLR 0xfffffeff
784 #define CM_DFTCTL_BUSYD_MSB 8
785 #define CM_DFTCTL_BUSYD_LSB 8
786 #define CM_DFTCTL_BUSY_BITS 7:7
787 #define CM_DFTCTL_BUSY_SET 0x00000080
788 #define CM_DFTCTL_BUSY_CLR 0xffffff7f
789 #define CM_DFTCTL_BUSY_MSB 7
790 #define CM_DFTCTL_BUSY_LSB 7
791 #define CM_DFTCTL_KILL_BITS 5:5
792 #define CM_DFTCTL_KILL_SET 0x00000020
793 #define CM_DFTCTL_KILL_CLR 0xffffffdf
794 #define CM_DFTCTL_KILL_MSB 5
795 #define CM_DFTCTL_KILL_LSB 5
796 #define CM_DFTCTL_ENAB_BITS 4:4
797 #define CM_DFTCTL_ENAB_SET 0x00000010
798 #define CM_DFTCTL_ENAB_CLR 0xffffffef
799 #define CM_DFTCTL_ENAB_MSB 4
800 #define CM_DFTCTL_ENAB_LSB 4
801 #define CM_DFTCTL_SRC_BITS 3:0
802 #define CM_DFTCTL_SRC_SET 0x0000000f
803 #define CM_DFTCTL_SRC_CLR 0xfffffff0
804 #define CM_DFTCTL_SRC_MSB 3
805 #define CM_DFTCTL_SRC_LSB 0
806 #define CM_DFTDIV HW_REGISTER_RW( 0x7e10116c )
807 #define CM_DFTDIV_MASK 0x0001f000
808 #define CM_DFTDIV_WIDTH 17
809 #define CM_DFTDIV_RESET 0000000000
810 #define CM_DFTDIV_DIV_BITS 16:12
811 #define CM_DFTDIV_DIV_SET 0x0001f000
812 #define CM_DFTDIV_DIV_CLR 0xfffe0fff
813 #define CM_DFTDIV_DIV_MSB 16
814 #define CM_DFTDIV_DIV_LSB 12
815 #define CM_GP0CTL HW_REGISTER_RW( 0x7e101070 )
816 #define CM_GP0CTL_MASK 0x000007bf
817 #define CM_GP0CTL_WIDTH 11
818 #define CM_GP0CTL_RESET 0x00000200
819 #define CM_GP0CTL_MASH_BITS 10:9
820 #define CM_GP0CTL_MASH_SET 0x00000600
821 #define CM_GP0CTL_MASH_CLR 0xfffff9ff
822 #define CM_GP0CTL_MASH_MSB 10
823 #define CM_GP0CTL_MASH_LSB 9
824 #define CM_GP0CTL_BUSYD_BITS 8:8
825 #define CM_GP0CTL_BUSYD_SET 0x00000100
826 #define CM_GP0CTL_BUSYD_CLR 0xfffffeff
827 #define CM_GP0CTL_BUSYD_MSB 8
828 #define CM_GP0CTL_BUSYD_LSB 8
829 #define CM_GP0CTL_BUSY_BITS 7:7
830 #define CM_GP0CTL_BUSY_SET 0x00000080
831 #define CM_GP0CTL_BUSY_CLR 0xffffff7f
832 #define CM_GP0CTL_BUSY_MSB 7
833 #define CM_GP0CTL_BUSY_LSB 7
834 #define CM_GP0CTL_KILL_BITS 5:5
835 #define CM_GP0CTL_KILL_SET 0x00000020
836 #define CM_GP0CTL_KILL_CLR 0xffffffdf
837 #define CM_GP0CTL_KILL_MSB 5
838 #define CM_GP0CTL_KILL_LSB 5
839 #define CM_GP0CTL_ENAB_BITS 4:4
840 #define CM_GP0CTL_ENAB_SET 0x00000010
841 #define CM_GP0CTL_ENAB_CLR 0xffffffef
842 #define CM_GP0CTL_ENAB_MSB 4
843 #define CM_GP0CTL_ENAB_LSB 4
844 #define CM_GP0CTL_SRC_BITS 3:0
845 #define CM_GP0CTL_SRC_SET 0x0000000f
846 #define CM_GP0CTL_SRC_CLR 0xfffffff0
847 #define CM_GP0CTL_SRC_MSB 3
848 #define CM_GP0CTL_SRC_LSB 0
849 #define CM_GP0DIV HW_REGISTER_RW( 0x7e101074 )
850 #define CM_GP0DIV_MASK 0x00ffffff
851 #define CM_GP0DIV_WIDTH 24
852 #define CM_GP0DIV_RESET 0000000000
853 #define CM_GP0DIV_DIV_BITS 23:0
854 #define CM_GP0DIV_DIV_SET 0x00ffffff
855 #define CM_GP0DIV_DIV_CLR 0xff000000
856 #define CM_GP0DIV_DIV_MSB 23
857 #define CM_GP0DIV_DIV_LSB 0
858 #define CM_GP1CTL HW_REGISTER_RW( 0x7e101078 )
859 #define CM_GP1CTL_MASK 0x000007bf
860 #define CM_GP1CTL_WIDTH 11
861 #define CM_GP1CTL_RESET 0x00000200
862 #define CM_GP1CTL_MASH_BITS 10:9
863 #define CM_GP1CTL_MASH_SET 0x00000600
864 #define CM_GP1CTL_MASH_CLR 0xfffff9ff
865 #define CM_GP1CTL_MASH_MSB 10
866 #define CM_GP1CTL_MASH_LSB 9
867 #define CM_GP1CTL_BUSYD_BITS 8:8
868 #define CM_GP1CTL_BUSYD_SET 0x00000100
869 #define CM_GP1CTL_BUSYD_CLR 0xfffffeff
870 #define CM_GP1CTL_BUSYD_MSB 8
871 #define CM_GP1CTL_BUSYD_LSB 8
872 #define CM_GP1CTL_BUSY_BITS 7:7
873 #define CM_GP1CTL_BUSY_SET 0x00000080
874 #define CM_GP1CTL_BUSY_CLR 0xffffff7f
875 #define CM_GP1CTL_BUSY_MSB 7
876 #define CM_GP1CTL_BUSY_LSB 7
877 #define CM_GP1CTL_KILL_BITS 5:5
878 #define CM_GP1CTL_KILL_SET 0x00000020
879 #define CM_GP1CTL_KILL_CLR 0xffffffdf
880 #define CM_GP1CTL_KILL_MSB 5
881 #define CM_GP1CTL_KILL_LSB 5
882 #define CM_GP1CTL_ENAB_BITS 4:4
883 #define CM_GP1CTL_ENAB_SET 0x00000010
884 #define CM_GP1CTL_ENAB_CLR 0xffffffef
885 #define CM_GP1CTL_ENAB_MSB 4
886 #define CM_GP1CTL_ENAB_LSB 4
887 #define CM_GP1CTL_SRC_BITS 3:0
888 #define CM_GP1CTL_SRC_SET 0x0000000f
889 #define CM_GP1CTL_SRC_CLR 0xfffffff0
890 #define CM_GP1CTL_SRC_MSB 3
891 #define CM_GP1CTL_SRC_LSB 0
892 #define CM_GP1DIV HW_REGISTER_RW( 0x7e10107c )
893 #define CM_GP1DIV_MASK 0x00ffffff
894 #define CM_GP1DIV_WIDTH 24
895 #define CM_GP1DIV_RESET 0000000000
896 #define CM_GP1DIV_DIV_BITS 23:0
897 #define CM_GP1DIV_DIV_SET 0x00ffffff
898 #define CM_GP1DIV_DIV_CLR 0xff000000
899 #define CM_GP1DIV_DIV_MSB 23
900 #define CM_GP1DIV_DIV_LSB 0
901 #define CM_GP2CTL HW_REGISTER_RW( 0x7e101080 )
902 #define CM_GP2CTL_MASK 0x000003bf
903 #define CM_GP2CTL_WIDTH 10
904 #define CM_GP2CTL_RESET 0000000000
905 #define CM_GP2CTL_FRAC_BITS 9:9
906 #define CM_GP2CTL_FRAC_SET 0x00000200
907 #define CM_GP2CTL_FRAC_CLR 0xfffffdff
908 #define CM_GP2CTL_FRAC_MSB 9
909 #define CM_GP2CTL_FRAC_LSB 9
910 #define CM_GP2CTL_BUSYD_BITS 8:8
911 #define CM_GP2CTL_BUSYD_SET 0x00000100
912 #define CM_GP2CTL_BUSYD_CLR 0xfffffeff
913 #define CM_GP2CTL_BUSYD_MSB 8
914 #define CM_GP2CTL_BUSYD_LSB 8
915 #define CM_GP2CTL_BUSY_BITS 7:7
916 #define CM_GP2CTL_BUSY_SET 0x00000080
917 #define CM_GP2CTL_BUSY_CLR 0xffffff7f
918 #define CM_GP2CTL_BUSY_MSB 7
919 #define CM_GP2CTL_BUSY_LSB 7
920 #define CM_GP2CTL_KILL_BITS 5:5
921 #define CM_GP2CTL_KILL_SET 0x00000020
922 #define CM_GP2CTL_KILL_CLR 0xffffffdf
923 #define CM_GP2CTL_KILL_MSB 5
924 #define CM_GP2CTL_KILL_LSB 5
925 #define CM_GP2CTL_ENAB_BITS 4:4
926 #define CM_GP2CTL_ENAB_SET 0x00000010
927 #define CM_GP2CTL_ENAB_CLR 0xffffffef
928 #define CM_GP2CTL_ENAB_MSB 4
929 #define CM_GP2CTL_ENAB_LSB 4
930 #define CM_GP2CTL_SRC_BITS 3:0
931 #define CM_GP2CTL_SRC_SET 0x0000000f
932 #define CM_GP2CTL_SRC_CLR 0xfffffff0
933 #define CM_GP2CTL_SRC_MSB 3
934 #define CM_GP2CTL_SRC_LSB 0
935 #define CM_GP2DIV HW_REGISTER_RW( 0x7e101084 )
936 #define CM_GP2DIV_MASK 0x00ffffff
937 #define CM_GP2DIV_WIDTH 24
938 #define CM_GP2DIV_RESET 0000000000
939 #define CM_GP2DIV_DIV_BITS 23:0
940 #define CM_GP2DIV_DIV_SET 0x00ffffff
941 #define CM_GP2DIV_DIV_CLR 0xff000000
942 #define CM_GP2DIV_DIV_MSB 23
943 #define CM_GP2DIV_DIV_LSB 0
944 #define CM_HSMCTL HW_REGISTER_RW( 0x7e101088 )
945 #define CM_HSMCTL_MASK 0x000003ff
946 #define CM_HSMCTL_WIDTH 10
947 #define CM_HSMCTL_RESET 0000000000
948 #define CM_HSMCTL_FRAC_BITS 9:9
949 #define CM_HSMCTL_FRAC_SET 0x00000200
950 #define CM_HSMCTL_FRAC_CLR 0xfffffdff
951 #define CM_HSMCTL_FRAC_MSB 9
952 #define CM_HSMCTL_FRAC_LSB 9
953 #define CM_HSMCTL_BUSYD_BITS 8:8
954 #define CM_HSMCTL_BUSYD_SET 0x00000100
955 #define CM_HSMCTL_BUSYD_CLR 0xfffffeff
956 #define CM_HSMCTL_BUSYD_MSB 8
957 #define CM_HSMCTL_BUSYD_LSB 8
958 #define CM_HSMCTL_BUSY_BITS 7:7
959 #define CM_HSMCTL_BUSY_SET 0x00000080
960 #define CM_HSMCTL_BUSY_CLR 0xffffff7f
961 #define CM_HSMCTL_BUSY_MSB 7
962 #define CM_HSMCTL_BUSY_LSB 7
963 #define CM_HSMCTL_GATE_BITS 6:6
964 #define CM_HSMCTL_GATE_SET 0x00000040
965 #define CM_HSMCTL_GATE_CLR 0xffffffbf
966 #define CM_HSMCTL_GATE_MSB 6
967 #define CM_HSMCTL_GATE_LSB 6
968 #define CM_HSMCTL_KILL_BITS 5:5
969 #define CM_HSMCTL_KILL_SET 0x00000020
970 #define CM_HSMCTL_KILL_CLR 0xffffffdf
971 #define CM_HSMCTL_KILL_MSB 5
972 #define CM_HSMCTL_KILL_LSB 5
973 #define CM_HSMCTL_ENAB_BITS 4:4
974 #define CM_HSMCTL_ENAB_SET 0x00000010
975 #define CM_HSMCTL_ENAB_CLR 0xffffffef
976 #define CM_HSMCTL_ENAB_MSB 4
977 #define CM_HSMCTL_ENAB_LSB 4
978 #define CM_HSMCTL_SRC_BITS 3:0
979 #define CM_HSMCTL_SRC_SET 0x0000000f
980 #define CM_HSMCTL_SRC_CLR 0xfffffff0
981 #define CM_HSMCTL_SRC_MSB 3
982 #define CM_HSMCTL_SRC_LSB 0
983 #define CM_HSMDIV HW_REGISTER_RW( 0x7e10108c )
984 #define CM_HSMDIV_MASK 0x0000fff0
985 #define CM_HSMDIV_WIDTH 16
986 #define CM_HSMDIV_RESET 0000000000
987 #define CM_HSMDIV_DIV_BITS 15:4
988 #define CM_HSMDIV_DIV_SET 0x0000fff0
989 #define CM_HSMDIV_DIV_CLR 0xffff000f
990 #define CM_HSMDIV_DIV_MSB 15
991 #define CM_HSMDIV_DIV_LSB 4
992 #define CM_OTPCTL HW_REGISTER_RW( 0x7e101090 )
993 #define CM_OTPCTL_MASK 0x000003b3
994 #define CM_OTPCTL_WIDTH 10
995 #define CM_OTPCTL_RESET 0x00000011
996 #define CM_OTPCTL_FRAC_BITS 9:9
997 #define CM_OTPCTL_FRAC_SET 0x00000200
998 #define CM_OTPCTL_FRAC_CLR 0xfffffdff
999 #define CM_OTPCTL_FRAC_MSB 9
1000 #define CM_OTPCTL_FRAC_LSB 9
1001 #define CM_OTPCTL_BUSYD_BITS 8:8
1002 #define CM_OTPCTL_BUSYD_SET 0x00000100
1003 #define CM_OTPCTL_BUSYD_CLR 0xfffffeff
1004 #define CM_OTPCTL_BUSYD_MSB 8
1005 #define CM_OTPCTL_BUSYD_LSB 8
1006 #define CM_OTPCTL_BUSY_BITS 7:7
1007 #define CM_OTPCTL_BUSY_SET 0x00000080
1008 #define CM_OTPCTL_BUSY_CLR 0xffffff7f
1009 #define CM_OTPCTL_BUSY_MSB 7
1010 #define CM_OTPCTL_BUSY_LSB 7
1011 #define CM_OTPCTL_KILL_BITS 5:5
1012 #define CM_OTPCTL_KILL_SET 0x00000020
1013 #define CM_OTPCTL_KILL_CLR 0xffffffdf
1014 #define CM_OTPCTL_KILL_MSB 5
1015 #define CM_OTPCTL_KILL_LSB 5
1016 #define CM_OTPCTL_ENAB_BITS 4:4
1017 #define CM_OTPCTL_ENAB_SET 0x00000010
1018 #define CM_OTPCTL_ENAB_CLR 0xffffffef
1019 #define CM_OTPCTL_ENAB_MSB 4
1020 #define CM_OTPCTL_ENAB_LSB 4
1021 #define CM_OTPCTL_SRC_BITS 1:0
1022 #define CM_OTPCTL_SRC_SET 0x00000003
1023 #define CM_OTPCTL_SRC_CLR 0xfffffffc
1024 #define CM_OTPCTL_SRC_MSB 1
1025 #define CM_OTPCTL_SRC_LSB 0
1026 #define CM_OTPDIV HW_REGISTER_RW( 0x7e101094 )
1027 #define CM_OTPDIV_MASK 0x0001f000
1028 #define CM_OTPDIV_WIDTH 17
1029 #define CM_OTPDIV_RESET 0x00004000
1030 #define CM_OTPDIV_DIV_BITS 16:12
1031 #define CM_OTPDIV_DIV_SET 0x0001f000
1032 #define CM_OTPDIV_DIV_CLR 0xfffe0fff
1033 #define CM_OTPDIV_DIV_MSB 16
1034 #define CM_OTPDIV_DIV_LSB 12
1035 #define CM_PULSECTL HW_REGISTER_RW( 0x7e101190 )
1036 #define CM_PULSECTL_MASK 0x000003b3
1037 #define CM_PULSECTL_WIDTH 10
1038 #define CM_PULSECTL_RESET 0x00000011
1039 #define CM_PULSECTL_FRAC_BITS 9:9
1040 #define CM_PULSECTL_FRAC_SET 0x00000200
1041 #define CM_PULSECTL_FRAC_CLR 0xfffffdff
1042 #define CM_PULSECTL_FRAC_MSB 9
1043 #define CM_PULSECTL_FRAC_LSB 9
1044 #define CM_PULSECTL_BUSYD_BITS 8:8
1045 #define CM_PULSECTL_BUSYD_SET 0x00000100
1046 #define CM_PULSECTL_BUSYD_CLR 0xfffffeff
1047 #define CM_PULSECTL_BUSYD_MSB 8
1048 #define CM_PULSECTL_BUSYD_LSB 8
1049 #define CM_PULSECTL_BUSY_BITS 7:7
1050 #define CM_PULSECTL_BUSY_SET 0x00000080
1051 #define CM_PULSECTL_BUSY_CLR 0xffffff7f
1052 #define CM_PULSECTL_BUSY_MSB 7
1053 #define CM_PULSECTL_BUSY_LSB 7
1054 #define CM_PULSECTL_KILL_BITS 5:5
1055 #define CM_PULSECTL_KILL_SET 0x00000020
1056 #define CM_PULSECTL_KILL_CLR 0xffffffdf
1057 #define CM_PULSECTL_KILL_MSB 5
1058 #define CM_PULSECTL_KILL_LSB 5
1059 #define CM_PULSECTL_ENAB_BITS 4:4
1060 #define CM_PULSECTL_ENAB_SET 0x00000010
1061 #define CM_PULSECTL_ENAB_CLR 0xffffffef
1062 #define CM_PULSECTL_ENAB_MSB 4
1063 #define CM_PULSECTL_ENAB_LSB 4
1064 #define CM_PULSECTL_SRC_BITS 1:0
1065 #define CM_PULSECTL_SRC_SET 0x00000003
1066 #define CM_PULSECTL_SRC_CLR 0xfffffffc
1067 #define CM_PULSECTL_SRC_MSB 1
1068 #define CM_PULSECTL_SRC_LSB 0
1069 #define CM_PULSEDIV HW_REGISTER_RW( 0x7e101194 )
1070 #define CM_PULSEDIV_MASK 0x00fff000
1071 #define CM_PULSEDIV_WIDTH 24
1072 #define CM_PULSEDIV_RESET 0x00014000
1073 #define CM_PULSEDIV_DIV_BITS 23:12
1074 #define CM_PULSEDIV_DIV_SET 0x00fff000
1075 #define CM_PULSEDIV_DIV_CLR 0xff000fff
1076 #define CM_PULSEDIV_DIV_MSB 23
1077 #define CM_PULSEDIV_DIV_LSB 12
1078 #define CM_PCMCTL HW_REGISTER_RW( 0x7e101098 )
1079 #define CM_PCMCTL_MASK 0x000007bf
1080 #define CM_PCMCTL_WIDTH 11
1081 #define CM_PCMCTL_RESET 0x00000200
1082 #define CM_PCMCTL_MASH_BITS 10:9
1083 #define CM_PCMCTL_MASH_SET 0x00000600
1084 #define CM_PCMCTL_MASH_CLR 0xfffff9ff
1085 #define CM_PCMCTL_MASH_MSB 10
1086 #define CM_PCMCTL_MASH_LSB 9
1087 #define CM_PCMCTL_BUSYD_BITS 8:8
1088 #define CM_PCMCTL_BUSYD_SET 0x00000100
1089 #define CM_PCMCTL_BUSYD_CLR 0xfffffeff
1090 #define CM_PCMCTL_BUSYD_MSB 8
1091 #define CM_PCMCTL_BUSYD_LSB 8
1092 #define CM_PCMCTL_BUSY_BITS 7:7
1093 #define CM_PCMCTL_BUSY_SET 0x00000080
1094 #define CM_PCMCTL_BUSY_CLR 0xffffff7f
1095 #define CM_PCMCTL_BUSY_MSB 7
1096 #define CM_PCMCTL_BUSY_LSB 7
1097 #define CM_PCMCTL_KILL_BITS 5:5
1098 #define CM_PCMCTL_KILL_SET 0x00000020
1099 #define CM_PCMCTL_KILL_CLR 0xffffffdf
1100 #define CM_PCMCTL_KILL_MSB 5
1101 #define CM_PCMCTL_KILL_LSB 5
1102 #define CM_PCMCTL_ENAB_BITS 4:4
1103 #define CM_PCMCTL_ENAB_SET 0x00000010
1104 #define CM_PCMCTL_ENAB_CLR 0xffffffef
1105 #define CM_PCMCTL_ENAB_MSB 4
1106 #define CM_PCMCTL_ENAB_LSB 4
1107 #define CM_PCMCTL_SRC_BITS 3:0
1108 #define CM_PCMCTL_SRC_SET 0x0000000f
1109 #define CM_PCMCTL_SRC_CLR 0xfffffff0
1110 #define CM_PCMCTL_SRC_MSB 3
1111 #define CM_PCMCTL_SRC_LSB 0
1112 #define CM_PCMDIV HW_REGISTER_RW( 0x7e10109c )
1113 #define CM_PCMDIV_MASK 0x00ffffff
1114 #define CM_PCMDIV_WIDTH 24
1115 #define CM_PCMDIV_RESET 0000000000
1116 #define CM_PCMDIV_DIV_BITS 23:0
1117 #define CM_PCMDIV_DIV_SET 0x00ffffff
1118 #define CM_PCMDIV_DIV_CLR 0xff000000
1119 #define CM_PCMDIV_DIV_MSB 23
1120 #define CM_PCMDIV_DIV_LSB 0
1121 #define CM_PWMCTL HW_REGISTER_RW( 0x7e1010a0 )
1122 #define CM_PWMCTL_MASK 0x000007bf
1123 #define CM_PWMCTL_WIDTH 11
1124 #define CM_PWMCTL_RESET 0x00000200
1125 #define CM_PWMCTL_MASH_BITS 10:9
1126 #define CM_PWMCTL_MASH_SET 0x00000600
1127 #define CM_PWMCTL_MASH_CLR 0xfffff9ff
1128 #define CM_PWMCTL_MASH_MSB 10
1129 #define CM_PWMCTL_MASH_LSB 9
1130 #define CM_PWMCTL_BUSYD_BITS 8:8
1131 #define CM_PWMCTL_BUSYD_SET 0x00000100
1132 #define CM_PWMCTL_BUSYD_CLR 0xfffffeff
1133 #define CM_PWMCTL_BUSYD_MSB 8
1134 #define CM_PWMCTL_BUSYD_LSB 8
1135 #define CM_PWMCTL_BUSY_BITS 7:7
1136 #define CM_PWMCTL_BUSY_SET 0x00000080
1137 #define CM_PWMCTL_BUSY_CLR 0xffffff7f
1138 #define CM_PWMCTL_BUSY_MSB 7
1139 #define CM_PWMCTL_BUSY_LSB 7
1140 #define CM_PWMCTL_KILL_BITS 5:5
1141 #define CM_PWMCTL_KILL_SET 0x00000020
1142 #define CM_PWMCTL_KILL_CLR 0xffffffdf
1143 #define CM_PWMCTL_KILL_MSB 5
1144 #define CM_PWMCTL_KILL_LSB 5
1145 #define CM_PWMCTL_ENAB_BITS 4:4
1146 #define CM_PWMCTL_ENAB_SET 0x00000010
1147 #define CM_PWMCTL_ENAB_CLR 0xffffffef
1148 #define CM_PWMCTL_ENAB_MSB 4
1149 #define CM_PWMCTL_ENAB_LSB 4
1150 #define CM_PWMCTL_SRC_BITS 3:0
1151 #define CM_PWMCTL_SRC_SET 0x0000000f
1152 #define CM_PWMCTL_SRC_CLR 0xfffffff0
1153 #define CM_PWMCTL_SRC_MSB 3
1154 #define CM_PWMCTL_SRC_LSB 0
1155 #define CM_PWMDIV HW_REGISTER_RW( 0x7e1010a4 )
1156 #define CM_PWMDIV_MASK 0x00ffffff
1157 #define CM_PWMDIV_WIDTH 24
1158 #define CM_PWMDIV_RESET 0000000000
1159 #define CM_PWMDIV_DIV_BITS 23:0
1160 #define CM_PWMDIV_DIV_SET 0x00ffffff
1161 #define CM_PWMDIV_DIV_CLR 0xff000000
1162 #define CM_PWMDIV_DIV_MSB 23
1163 #define CM_PWMDIV_DIV_LSB 0
1164 #define CM_SLIMCTL HW_REGISTER_RW( 0x7e1010a8 )
1165 #define CM_SLIMCTL_MASK 0x000007bf
1166 #define CM_SLIMCTL_WIDTH 11
1167 #define CM_SLIMCTL_RESET 0x00000200
1168 #define CM_SLIMCTL_MASH_BITS 10:9
1169 #define CM_SLIMCTL_MASH_SET 0x00000600
1170 #define CM_SLIMCTL_MASH_CLR 0xfffff9ff
1171 #define CM_SLIMCTL_MASH_MSB 10
1172 #define CM_SLIMCTL_MASH_LSB 9
1173 #define CM_SLIMCTL_BUSYD_BITS 8:8
1174 #define CM_SLIMCTL_BUSYD_SET 0x00000100
1175 #define CM_SLIMCTL_BUSYD_CLR 0xfffffeff
1176 #define CM_SLIMCTL_BUSYD_MSB 8
1177 #define CM_SLIMCTL_BUSYD_LSB 8
1178 #define CM_SLIMCTL_BUSY_BITS 7:7
1179 #define CM_SLIMCTL_BUSY_SET 0x00000080
1180 #define CM_SLIMCTL_BUSY_CLR 0xffffff7f
1181 #define CM_SLIMCTL_BUSY_MSB 7
1182 #define CM_SLIMCTL_BUSY_LSB 7
1183 #define CM_SLIMCTL_KILL_BITS 5:5
1184 #define CM_SLIMCTL_KILL_SET 0x00000020
1185 #define CM_SLIMCTL_KILL_CLR 0xffffffdf
1186 #define CM_SLIMCTL_KILL_MSB 5
1187 #define CM_SLIMCTL_KILL_LSB 5
1188 #define CM_SLIMCTL_ENAB_BITS 4:4
1189 #define CM_SLIMCTL_ENAB_SET 0x00000010
1190 #define CM_SLIMCTL_ENAB_CLR 0xffffffef
1191 #define CM_SLIMCTL_ENAB_MSB 4
1192 #define CM_SLIMCTL_ENAB_LSB 4
1193 #define CM_SLIMCTL_SRC_BITS 3:0
1194 #define CM_SLIMCTL_SRC_SET 0x0000000f
1195 #define CM_SLIMCTL_SRC_CLR 0xfffffff0
1196 #define CM_SLIMCTL_SRC_MSB 3
1197 #define CM_SLIMCTL_SRC_LSB 0
1198 #define CM_SLIMDIV HW_REGISTER_RW( 0x7e1010ac )
1199 #define CM_SLIMDIV_MASK 0x00ffffff
1200 #define CM_SLIMDIV_WIDTH 24
1201 #define CM_SLIMDIV_RESET 0000000000
1202 #define CM_SLIMDIV_DIV_BITS 23:0
1203 #define CM_SLIMDIV_DIV_SET 0x00ffffff
1204 #define CM_SLIMDIV_DIV_CLR 0xff000000
1205 #define CM_SLIMDIV_DIV_MSB 23
1206 #define CM_SLIMDIV_DIV_LSB 0
1207 #define CM_SMICTL HW_REGISTER_RW( 0x7e1010b0 )
1208 #define CM_SMICTL_MASK 0x000003bf
1209 #define CM_SMICTL_WIDTH 10
1210 #define CM_SMICTL_RESET 0000000000
1211 #define CM_SMICTL_FRAC_BITS 9:9
1212 #define CM_SMICTL_FRAC_SET 0x00000200
1213 #define CM_SMICTL_FRAC_CLR 0xfffffdff
1214 #define CM_SMICTL_FRAC_MSB 9
1215 #define CM_SMICTL_FRAC_LSB 9
1216 #define CM_SMICTL_BUSYD_BITS 8:8
1217 #define CM_SMICTL_BUSYD_SET 0x00000100
1218 #define CM_SMICTL_BUSYD_CLR 0xfffffeff
1219 #define CM_SMICTL_BUSYD_MSB 8
1220 #define CM_SMICTL_BUSYD_LSB 8
1221 #define CM_SMICTL_BUSY_BITS 7:7
1222 #define CM_SMICTL_BUSY_SET 0x00000080
1223 #define CM_SMICTL_BUSY_CLR 0xffffff7f
1224 #define CM_SMICTL_BUSY_MSB 7
1225 #define CM_SMICTL_BUSY_LSB 7
1226 #define CM_SMICTL_KILL_BITS 5:5
1227 #define CM_SMICTL_KILL_SET 0x00000020
1228 #define CM_SMICTL_KILL_CLR 0xffffffdf
1229 #define CM_SMICTL_KILL_MSB 5
1230 #define CM_SMICTL_KILL_LSB 5
1231 #define CM_SMICTL_ENAB_BITS 4:4
1232 #define CM_SMICTL_ENAB_SET 0x00000010
1233 #define CM_SMICTL_ENAB_CLR 0xffffffef
1234 #define CM_SMICTL_ENAB_MSB 4
1235 #define CM_SMICTL_ENAB_LSB 4
1236 #define CM_SMICTL_SRC_BITS 3:0
1237 #define CM_SMICTL_SRC_SET 0x0000000f
1238 #define CM_SMICTL_SRC_CLR 0xfffffff0
1239 #define CM_SMICTL_SRC_MSB 3
1240 #define CM_SMICTL_SRC_LSB 0
1241 #define CM_SMIDIV HW_REGISTER_RW( 0x7e1010b4 )
1242 #define CM_SMIDIV_MASK 0x0000fff0
1243 #define CM_SMIDIV_WIDTH 16
1244 #define CM_SMIDIV_RESET 0000000000
1245 #define CM_SMIDIV_DIV_BITS 15:4
1246 #define CM_SMIDIV_DIV_SET 0x0000fff0
1247 #define CM_SMIDIV_DIV_CLR 0xffff000f
1248 #define CM_SMIDIV_DIV_MSB 15
1249 #define CM_SMIDIV_DIV_LSB 4
1250 #define CM_TCNTCTL HW_REGISTER_RW( 0x7e1010c0 )
1251 #define CM_TCNTCTL_MASK 0x000030cf
1252 #define CM_TCNTCTL_WIDTH 14
1253 #define CM_TCNTCTL_RESET 0000000000
1254 #define CM_TCNTCTL_SRC1_BITS 13:12
1255 #define CM_TCNTCTL_SRC1_SET 0x00003000
1256 #define CM_TCNTCTL_SRC1_CLR 0xffffcfff
1257 #define CM_TCNTCTL_SRC1_MSB 13
1258 #define CM_TCNTCTL_SRC1_LSB 12
1259 #define CM_TCNTCTL_BUSY_BITS 7:7
1260 #define CM_TCNTCTL_BUSY_SET 0x00000080
1261 #define CM_TCNTCTL_BUSY_CLR 0xffffff7f
1262 #define CM_TCNTCTL_BUSY_MSB 7
1263 #define CM_TCNTCTL_BUSY_LSB 7
1264 #define CM_TCNTCTL_KILL_BITS 6:6
1265 #define CM_TCNTCTL_KILL_SET 0x00000040
1266 #define CM_TCNTCTL_KILL_CLR 0xffffffbf
1267 #define CM_TCNTCTL_KILL_MSB 6
1268 #define CM_TCNTCTL_KILL_LSB 6
1269 #define CM_TCNTCTL_SRC0_BITS 3:0
1270 #define CM_TCNTCTL_SRC0_SET 0x0000000f
1271 #define CM_TCNTCTL_SRC0_CLR 0xfffffff0
1272 #define CM_TCNTCTL_SRC0_MSB 3
1273 #define CM_TCNTCTL_SRC0_LSB 0
1274 #define CM_TCNTCNT HW_REGISTER_RW( 0x7e1010c4 )
1275 #define CM_TCNTCNT_MASK 0x00ffffff
1276 #define CM_TCNTCNT_WIDTH 24
1277 #define CM_TCNTCNT_RESET 0000000000
1278 #define CM_TCNTCNT_CNT_BITS 23:0
1279 #define CM_TCNTCNT_CNT_SET 0x00ffffff
1280 #define CM_TCNTCNT_CNT_CLR 0xff000000
1281 #define CM_TCNTCNT_CNT_MSB 23
1282 #define CM_TCNTCNT_CNT_LSB 0
1283 #define CM_TECCTL HW_REGISTER_RW( 0x7e1010c8 )
1284 #define CM_TECCTL_MASK 0x000003b3
1285 #define CM_TECCTL_WIDTH 10
1286 #define CM_TECCTL_RESET 0000000000
1287 #define CM_TECCTL_FRAC_BITS 9:9
1288 #define CM_TECCTL_FRAC_SET 0x00000200
1289 #define CM_TECCTL_FRAC_CLR 0xfffffdff
1290 #define CM_TECCTL_FRAC_MSB 9
1291 #define CM_TECCTL_FRAC_LSB 9
1292 #define CM_TECCTL_BUSYD_BITS 8:8
1293 #define CM_TECCTL_BUSYD_SET 0x00000100
1294 #define CM_TECCTL_BUSYD_CLR 0xfffffeff
1295 #define CM_TECCTL_BUSYD_MSB 8
1296 #define CM_TECCTL_BUSYD_LSB 8
1297 #define CM_TECCTL_BUSY_BITS 7:7
1298 #define CM_TECCTL_BUSY_SET 0x00000080
1299 #define CM_TECCTL_BUSY_CLR 0xffffff7f
1300 #define CM_TECCTL_BUSY_MSB 7
1301 #define CM_TECCTL_BUSY_LSB 7
1302 #define CM_TECCTL_KILL_BITS 5:5
1303 #define CM_TECCTL_KILL_SET 0x00000020
1304 #define CM_TECCTL_KILL_CLR 0xffffffdf
1305 #define CM_TECCTL_KILL_MSB 5
1306 #define CM_TECCTL_KILL_LSB 5
1307 #define CM_TECCTL_ENAB_BITS 4:4
1308 #define CM_TECCTL_ENAB_SET 0x00000010
1309 #define CM_TECCTL_ENAB_CLR 0xffffffef
1310 #define CM_TECCTL_ENAB_MSB 4
1311 #define CM_TECCTL_ENAB_LSB 4
1312 #define CM_TECCTL_SRC_BITS 1:0
1313 #define CM_TECCTL_SRC_SET 0x00000003
1314 #define CM_TECCTL_SRC_CLR 0xfffffffc
1315 #define CM_TECCTL_SRC_MSB 1
1316 #define CM_TECCTL_SRC_LSB 0
1317 #define CM_TECDIV HW_REGISTER_RW( 0x7e1010cc )
1318 #define CM_TECDIV_MASK 0x0003f000
1319 #define CM_TECDIV_WIDTH 18
1320 #define CM_TECDIV_RESET 0000000000
1321 #define CM_TECDIV_DIV_BITS 17:12
1322 #define CM_TECDIV_DIV_SET 0x0003f000
1323 #define CM_TECDIV_DIV_CLR 0xfffc0fff
1324 #define CM_TECDIV_DIV_MSB 17
1325 #define CM_TECDIV_DIV_LSB 12
1326 #define CM_TD0CTL HW_REGISTER_RW( 0x7e1010d0 )
1327 #define CM_TD0CTL_MASK 0x00001bff
1328 #define CM_TD0CTL_WIDTH 13
1329 #define CM_TD0CTL_RESET 0000000000
1330 #define CM_TD0CTL_STEP_BITS 12:12
1331 #define CM_TD0CTL_STEP_SET 0x00001000
1332 #define CM_TD0CTL_STEP_CLR 0xffffefff
1333 #define CM_TD0CTL_STEP_MSB 12
1334 #define CM_TD0CTL_STEP_LSB 12
1335 #define CM_TD0CTL_FLIP_BITS 11:11
1336 #define CM_TD0CTL_FLIP_SET 0x00000800
1337 #define CM_TD0CTL_FLIP_CLR 0xfffff7ff
1338 #define CM_TD0CTL_FLIP_MSB 11
1339 #define CM_TD0CTL_FLIP_LSB 11
1340 #define CM_TD0CTL_FRAC_BITS 9:9
1341 #define CM_TD0CTL_FRAC_SET 0x00000200
1342 #define CM_TD0CTL_FRAC_CLR 0xfffffdff
1343 #define CM_TD0CTL_FRAC_MSB 9
1344 #define CM_TD0CTL_FRAC_LSB 9
1345 #define CM_TD0CTL_BUSYD_BITS 8:8
1346 #define CM_TD0CTL_BUSYD_SET 0x00000100
1347 #define CM_TD0CTL_BUSYD_CLR 0xfffffeff
1348 #define CM_TD0CTL_BUSYD_MSB 8
1349 #define CM_TD0CTL_BUSYD_LSB 8
1350 #define CM_TD0CTL_BUSY_BITS 7:7
1351 #define CM_TD0CTL_BUSY_SET 0x00000080
1352 #define CM_TD0CTL_BUSY_CLR 0xffffff7f
1353 #define CM_TD0CTL_BUSY_MSB 7
1354 #define CM_TD0CTL_BUSY_LSB 7
1355 #define CM_TD0CTL_GATE_BITS 6:6
1356 #define CM_TD0CTL_GATE_SET 0x00000040
1357 #define CM_TD0CTL_GATE_CLR 0xffffffbf
1358 #define CM_TD0CTL_GATE_MSB 6
1359 #define CM_TD0CTL_GATE_LSB 6
1360 #define CM_TD0CTL_KILL_BITS 5:5
1361 #define CM_TD0CTL_KILL_SET 0x00000020
1362 #define CM_TD0CTL_KILL_CLR 0xffffffdf
1363 #define CM_TD0CTL_KILL_MSB 5
1364 #define CM_TD0CTL_KILL_LSB 5
1365 #define CM_TD0CTL_ENAB_BITS 4:4
1366 #define CM_TD0CTL_ENAB_SET 0x00000010
1367 #define CM_TD0CTL_ENAB_CLR 0xffffffef
1368 #define CM_TD0CTL_ENAB_MSB 4
1369 #define CM_TD0CTL_ENAB_LSB 4
1370 #define CM_TD0CTL_SRC_BITS 3:0
1371 #define CM_TD0CTL_SRC_SET 0x0000000f
1372 #define CM_TD0CTL_SRC_CLR 0xfffffff0
1373 #define CM_TD0CTL_SRC_MSB 3
1374 #define CM_TD0CTL_SRC_LSB 0
1375 #define CM_TD0DIV HW_REGISTER_RW( 0x7e1010d4 )
1376 #define CM_TD0DIV_MASK 0x00ffffff
1377 #define CM_TD0DIV_WIDTH 24
1378 #define CM_TD0DIV_RESET 0000000000
1379 #define CM_TD0DIV_DIV_BITS 23:0
1380 #define CM_TD0DIV_DIV_SET 0x00ffffff
1381 #define CM_TD0DIV_DIV_CLR 0xff000000
1382 #define CM_TD0DIV_DIV_MSB 23
1383 #define CM_TD0DIV_DIV_LSB 0
1384 #define CM_TD1CTL HW_REGISTER_RW( 0x7e1010d8 )
1385 #define CM_TD1CTL_MASK 0x00001bff
1386 #define CM_TD1CTL_WIDTH 13
1387 #define CM_TD1CTL_RESET 0000000000
1388 #define CM_TD1CTL_STEP_BITS 12:12
1389 #define CM_TD1CTL_STEP_SET 0x00001000
1390 #define CM_TD1CTL_STEP_CLR 0xffffefff
1391 #define CM_TD1CTL_STEP_MSB 12
1392 #define CM_TD1CTL_STEP_LSB 12
1393 #define CM_TD1CTL_FLIP_BITS 11:11
1394 #define CM_TD1CTL_FLIP_SET 0x00000800
1395 #define CM_TD1CTL_FLIP_CLR 0xfffff7ff
1396 #define CM_TD1CTL_FLIP_MSB 11
1397 #define CM_TD1CTL_FLIP_LSB 11
1398 #define CM_TD1CTL_FRAC_BITS 9:9
1399 #define CM_TD1CTL_FRAC_SET 0x00000200
1400 #define CM_TD1CTL_FRAC_CLR 0xfffffdff
1401 #define CM_TD1CTL_FRAC_MSB 9
1402 #define CM_TD1CTL_FRAC_LSB 9
1403 #define CM_TD1CTL_BUSYD_BITS 8:8
1404 #define CM_TD1CTL_BUSYD_SET 0x00000100
1405 #define CM_TD1CTL_BUSYD_CLR 0xfffffeff
1406 #define CM_TD1CTL_BUSYD_MSB 8
1407 #define CM_TD1CTL_BUSYD_LSB 8
1408 #define CM_TD1CTL_BUSY_BITS 7:7
1409 #define CM_TD1CTL_BUSY_SET 0x00000080
1410 #define CM_TD1CTL_BUSY_CLR 0xffffff7f
1411 #define CM_TD1CTL_BUSY_MSB 7
1412 #define CM_TD1CTL_BUSY_LSB 7
1413 #define CM_TD1CTL_GATE_BITS 6:6
1414 #define CM_TD1CTL_GATE_SET 0x00000040
1415 #define CM_TD1CTL_GATE_CLR 0xffffffbf
1416 #define CM_TD1CTL_GATE_MSB 6
1417 #define CM_TD1CTL_GATE_LSB 6
1418 #define CM_TD1CTL_KILL_BITS 5:5
1419 #define CM_TD1CTL_KILL_SET 0x00000020
1420 #define CM_TD1CTL_KILL_CLR 0xffffffdf
1421 #define CM_TD1CTL_KILL_MSB 5
1422 #define CM_TD1CTL_KILL_LSB 5
1423 #define CM_TD1CTL_ENAB_BITS 4:4
1424 #define CM_TD1CTL_ENAB_SET 0x00000010
1425 #define CM_TD1CTL_ENAB_CLR 0xffffffef
1426 #define CM_TD1CTL_ENAB_MSB 4
1427 #define CM_TD1CTL_ENAB_LSB 4
1428 #define CM_TD1CTL_SRC_BITS 3:0
1429 #define CM_TD1CTL_SRC_SET 0x0000000f
1430 #define CM_TD1CTL_SRC_CLR 0xfffffff0
1431 #define CM_TD1CTL_SRC_MSB 3
1432 #define CM_TD1CTL_SRC_LSB 0
1433 #define CM_TD1DIV HW_REGISTER_RW( 0x7e1010dc )
1434 #define CM_TD1DIV_MASK 0x00ffffff
1435 #define CM_TD1DIV_WIDTH 24
1436 #define CM_TD1DIV_RESET 0000000000
1437 #define CM_TD1DIV_DIV_BITS 23:0
1438 #define CM_TD1DIV_DIV_SET 0x00ffffff
1439 #define CM_TD1DIV_DIV_CLR 0xff000000
1440 #define CM_TD1DIV_DIV_MSB 23
1441 #define CM_TD1DIV_DIV_LSB 0
1442 #define CM_TSENSCTL HW_REGISTER_RW( 0x7e1010e0 )
1443 #define CM_TSENSCTL_MASK 0x000003b3
1444 #define CM_TSENSCTL_WIDTH 10
1445 #define CM_TSENSCTL_RESET 0000000000
1446 #define CM_TSENSCTL_FRAC_BITS 9:9
1447 #define CM_TSENSCTL_FRAC_SET 0x00000200
1448 #define CM_TSENSCTL_FRAC_CLR 0xfffffdff
1449 #define CM_TSENSCTL_FRAC_MSB 9
1450 #define CM_TSENSCTL_FRAC_LSB 9
1451 #define CM_TSENSCTL_BUSYD_BITS 8:8
1452 #define CM_TSENSCTL_BUSYD_SET 0x00000100
1453 #define CM_TSENSCTL_BUSYD_CLR 0xfffffeff
1454 #define CM_TSENSCTL_BUSYD_MSB 8
1455 #define CM_TSENSCTL_BUSYD_LSB 8
1456 #define CM_TSENSCTL_BUSY_BITS 7:7
1457 #define CM_TSENSCTL_BUSY_SET 0x00000080
1458 #define CM_TSENSCTL_BUSY_CLR 0xffffff7f
1459 #define CM_TSENSCTL_BUSY_MSB 7
1460 #define CM_TSENSCTL_BUSY_LSB 7
1461 #define CM_TSENSCTL_KILL_BITS 5:5
1462 #define CM_TSENSCTL_KILL_SET 0x00000020
1463 #define CM_TSENSCTL_KILL_CLR 0xffffffdf
1464 #define CM_TSENSCTL_KILL_MSB 5
1465 #define CM_TSENSCTL_KILL_LSB 5
1466 #define CM_TSENSCTL_ENAB_BITS 4:4
1467 #define CM_TSENSCTL_ENAB_SET 0x00000010
1468 #define CM_TSENSCTL_ENAB_CLR 0xffffffef
1469 #define CM_TSENSCTL_ENAB_MSB 4
1470 #define CM_TSENSCTL_ENAB_LSB 4
1471 #define CM_TSENSCTL_SRC_BITS 1:0
1472 #define CM_TSENSCTL_SRC_SET 0x00000003
1473 #define CM_TSENSCTL_SRC_CLR 0xfffffffc
1474 #define CM_TSENSCTL_SRC_MSB 1
1475 #define CM_TSENSCTL_SRC_LSB 0
1476 #define CM_TSENSDIV HW_REGISTER_RW( 0x7e1010e4 )
1477 #define CM_TSENSDIV_MASK 0x0001f000
1478 #define CM_TSENSDIV_WIDTH 17
1479 #define CM_TSENSDIV_RESET 0000000000
1480 #define CM_TSENSDIV_DIV_BITS 16:12
1481 #define CM_TSENSDIV_DIV_SET 0x0001f000
1482 #define CM_TSENSDIV_DIV_CLR 0xfffe0fff
1483 #define CM_TSENSDIV_DIV_MSB 16
1484 #define CM_TSENSDIV_DIV_LSB 12
1485 #define CM_TIMERCTL HW_REGISTER_RW( 0x7e1010e8 )
1486 #define CM_TIMERCTL_MASK 0x000003b3
1487 #define CM_TIMERCTL_WIDTH 10
1488 #define CM_TIMERCTL_RESET 0000000000
1489 #define CM_TIMERCTL_FRAC_BITS 9:9
1490 #define CM_TIMERCTL_FRAC_SET 0x00000200
1491 #define CM_TIMERCTL_FRAC_CLR 0xfffffdff
1492 #define CM_TIMERCTL_FRAC_MSB 9
1493 #define CM_TIMERCTL_FRAC_LSB 9
1494 #define CM_TIMERCTL_BUSYD_BITS 8:8
1495 #define CM_TIMERCTL_BUSYD_SET 0x00000100
1496 #define CM_TIMERCTL_BUSYD_CLR 0xfffffeff
1497 #define CM_TIMERCTL_BUSYD_MSB 8
1498 #define CM_TIMERCTL_BUSYD_LSB 8
1499 #define CM_TIMERCTL_BUSY_BITS 7:7
1500 #define CM_TIMERCTL_BUSY_SET 0x00000080
1501 #define CM_TIMERCTL_BUSY_CLR 0xffffff7f
1502 #define CM_TIMERCTL_BUSY_MSB 7
1503 #define CM_TIMERCTL_BUSY_LSB 7
1504 #define CM_TIMERCTL_KILL_BITS 5:5
1505 #define CM_TIMERCTL_KILL_SET 0x00000020
1506 #define CM_TIMERCTL_KILL_CLR 0xffffffdf
1507 #define CM_TIMERCTL_KILL_MSB 5
1508 #define CM_TIMERCTL_KILL_LSB 5
1509 #define CM_TIMERCTL_ENAB_BITS 4:4
1510 #define CM_TIMERCTL_ENAB_SET 0x00000010
1511 #define CM_TIMERCTL_ENAB_CLR 0xffffffef
1512 #define CM_TIMERCTL_ENAB_MSB 4
1513 #define CM_TIMERCTL_ENAB_LSB 4
1514 #define CM_TIMERCTL_SRC_BITS 1:0
1515 #define CM_TIMERCTL_SRC_SET 0x00000003
1516 #define CM_TIMERCTL_SRC_CLR 0xfffffffc
1517 #define CM_TIMERCTL_SRC_MSB 1
1518 #define CM_TIMERCTL_SRC_LSB 0
1519 #define CM_TIMERDIV HW_REGISTER_RW( 0x7e1010ec )
1520 #define CM_TIMERDIV_MASK 0x0003ffff
1521 #define CM_TIMERDIV_WIDTH 18
1522 #define CM_TIMERDIV_RESET 0000000000
1523 #define CM_TIMERDIV_DIV_BITS 17:0
1524 #define CM_TIMERDIV_DIV_SET 0x0003ffff
1525 #define CM_TIMERDIV_DIV_CLR 0xfffc0000
1526 #define CM_TIMERDIV_DIV_MSB 17
1527 #define CM_TIMERDIV_DIV_LSB 0
1528 #define CM_UARTCTL HW_REGISTER_RW( 0x7e1010f0 )
1529 #define CM_UARTCTL_MASK 0x000003bf
1530 #define CM_UARTCTL_WIDTH 10
1531 #define CM_UARTCTL_RESET 0000000000
1532 #define CM_UARTCTL_FRAC_BITS 9:9
1533 #define CM_UARTCTL_FRAC_SET 0x00000200
1534 #define CM_UARTCTL_FRAC_CLR 0xfffffdff
1535 #define CM_UARTCTL_FRAC_MSB 9
1536 #define CM_UARTCTL_FRAC_LSB 9
1537 #define CM_UARTCTL_BUSYD_BITS 8:8
1538 #define CM_UARTCTL_BUSYD_SET 0x00000100
1539 #define CM_UARTCTL_BUSYD_CLR 0xfffffeff
1540 #define CM_UARTCTL_BUSYD_MSB 8
1541 #define CM_UARTCTL_BUSYD_LSB 8
1542 #define CM_UARTCTL_BUSY_BITS 7:7
1543 #define CM_UARTCTL_BUSY_SET 0x00000080
1544 #define CM_UARTCTL_BUSY_CLR 0xffffff7f
1545 #define CM_UARTCTL_BUSY_MSB 7
1546 #define CM_UARTCTL_BUSY_LSB 7
1547 #define CM_UARTCTL_KILL_BITS 5:5
1548 #define CM_UARTCTL_KILL_SET 0x00000020
1549 #define CM_UARTCTL_KILL_CLR 0xffffffdf
1550 #define CM_UARTCTL_KILL_MSB 5
1551 #define CM_UARTCTL_KILL_LSB 5
1552 #define CM_UARTCTL_ENAB_BITS 4:4
1553 #define CM_UARTCTL_ENAB_SET 0x00000010
1554 #define CM_UARTCTL_ENAB_CLR 0xffffffef
1555 #define CM_UARTCTL_ENAB_MSB 4
1556 #define CM_UARTCTL_ENAB_LSB 4
1557 #define CM_UARTCTL_SRC_BITS 3:0
1558 #define CM_UARTCTL_SRC_SET 0x0000000f
1559 #define CM_UARTCTL_SRC_CLR 0xfffffff0
1560 #define CM_UARTCTL_SRC_MSB 3
1561 #define CM_UARTCTL_SRC_LSB 0
1562 #define CM_UARTDIV HW_REGISTER_RW( 0x7e1010f4 )
1563 #define CM_UARTDIV_MASK 0x003fffff
1564 #define CM_UARTDIV_WIDTH 22
1565 #define CM_UARTDIV_RESET 0000000000
1566 #define CM_UARTDIV_DIV_BITS 21:0
1567 #define CM_UARTDIV_DIV_SET 0x003fffff
1568 #define CM_UARTDIV_DIV_CLR 0xffc00000
1569 #define CM_UARTDIV_DIV_MSB 21
1570 #define CM_UARTDIV_DIV_LSB 0
1571 #define CM_VECCTL HW_REGISTER_RW( 0x7e1010f8 )
1572 #define CM_VECCTL_MASK 0x000003bf
1573 #define CM_VECCTL_WIDTH 10
1574 #define CM_VECCTL_RESET 0000000000
1575 #define CM_VECCTL_FRAC_BITS 9:9
1576 #define CM_VECCTL_FRAC_SET 0x00000200
1577 #define CM_VECCTL_FRAC_CLR 0xfffffdff
1578 #define CM_VECCTL_FRAC_MSB 9
1579 #define CM_VECCTL_FRAC_LSB 9
1580 #define CM_VECCTL_BUSYD_BITS 8:8
1581 #define CM_VECCTL_BUSYD_SET 0x00000100
1582 #define CM_VECCTL_BUSYD_CLR 0xfffffeff
1583 #define CM_VECCTL_BUSYD_MSB 8
1584 #define CM_VECCTL_BUSYD_LSB 8
1585 #define CM_VECCTL_BUSY_BITS 7:7
1586 #define CM_VECCTL_BUSY_SET 0x00000080
1587 #define CM_VECCTL_BUSY_CLR 0xffffff7f
1588 #define CM_VECCTL_BUSY_MSB 7
1589 #define CM_VECCTL_BUSY_LSB 7
1590 #define CM_VECCTL_KILL_BITS 5:5
1591 #define CM_VECCTL_KILL_SET 0x00000020
1592 #define CM_VECCTL_KILL_CLR 0xffffffdf
1593 #define CM_VECCTL_KILL_MSB 5
1594 #define CM_VECCTL_KILL_LSB 5
1595 #define CM_VECCTL_ENAB_BITS 4:4
1596 #define CM_VECCTL_ENAB_SET 0x00000010
1597 #define CM_VECCTL_ENAB_CLR 0xffffffef
1598 #define CM_VECCTL_ENAB_MSB 4
1599 #define CM_VECCTL_ENAB_LSB 4
1600 #define CM_VECCTL_SRC_BITS 3:0
1601 #define CM_VECCTL_SRC_SET 0x0000000f
1602 #define CM_VECCTL_SRC_CLR 0xfffffff0
1603 #define CM_VECCTL_SRC_MSB 3
1604 #define CM_VECCTL_SRC_LSB 0
1605 #define CM_VECDIV HW_REGISTER_RW( 0x7e1010fc )
1606 #define CM_VECDIV_MASK 0x0000f000
1607 #define CM_VECDIV_WIDTH 16
1608 #define CM_VECDIV_RESET 0000000000
1609 #define CM_VECDIV_DIV_BITS 15:12
1610 #define CM_VECDIV_DIV_SET 0x0000f000
1611 #define CM_VECDIV_DIV_CLR 0xffff0fff
1612 #define CM_VECDIV_DIV_MSB 15
1613 #define CM_VECDIV_DIV_LSB 12
1614 #define CM_AVEOCTL HW_REGISTER_RW( 0x7e1011b8 )
1615 #define CM_AVEOCTL_MASK 0x000003bf
1616 #define CM_AVEOCTL_WIDTH 10
1617 #define CM_AVEOCTL_RESET 0000000000
1618 #define CM_AVEOCTL_FRAC_BITS 9:9
1619 #define CM_AVEOCTL_FRAC_SET 0x00000200
1620 #define CM_AVEOCTL_FRAC_CLR 0xfffffdff
1621 #define CM_AVEOCTL_FRAC_MSB 9
1622 #define CM_AVEOCTL_FRAC_LSB 9
1623 #define CM_AVEOCTL_BUSYD_BITS 8:8
1624 #define CM_AVEOCTL_BUSYD_SET 0x00000100
1625 #define CM_AVEOCTL_BUSYD_CLR 0xfffffeff
1626 #define CM_AVEOCTL_BUSYD_MSB 8
1627 #define CM_AVEOCTL_BUSYD_LSB 8
1628 #define CM_AVEOCTL_BUSY_BITS 7:7
1629 #define CM_AVEOCTL_BUSY_SET 0x00000080
1630 #define CM_AVEOCTL_BUSY_CLR 0xffffff7f
1631 #define CM_AVEOCTL_BUSY_MSB 7
1632 #define CM_AVEOCTL_BUSY_LSB 7
1633 #define CM_AVEOCTL_KILL_BITS 5:5
1634 #define CM_AVEOCTL_KILL_SET 0x00000020
1635 #define CM_AVEOCTL_KILL_CLR 0xffffffdf
1636 #define CM_AVEOCTL_KILL_MSB 5
1637 #define CM_AVEOCTL_KILL_LSB 5
1638 #define CM_AVEOCTL_ENAB_BITS 4:4
1639 #define CM_AVEOCTL_ENAB_SET 0x00000010
1640 #define CM_AVEOCTL_ENAB_CLR 0xffffffef
1641 #define CM_AVEOCTL_ENAB_MSB 4
1642 #define CM_AVEOCTL_ENAB_LSB 4
1643 #define CM_AVEOCTL_SRC_BITS 3:0
1644 #define CM_AVEOCTL_SRC_SET 0x0000000f
1645 #define CM_AVEOCTL_SRC_CLR 0xfffffff0
1646 #define CM_AVEOCTL_SRC_MSB 3
1647 #define CM_AVEOCTL_SRC_LSB 0
1648 #define CM_AVEODIV HW_REGISTER_RW( 0x7e1011bc )
1649 #define CM_AVEODIV_MASK 0x0000f000
1650 #define CM_AVEODIV_WIDTH 16
1651 #define CM_AVEODIV_RESET 0000000000
1652 #define CM_AVEODIV_DIV_BITS 15:12
1653 #define CM_AVEODIV_DIV_SET 0x0000f000
1654 #define CM_AVEODIV_DIV_CLR 0xffff0fff
1655 #define CM_AVEODIV_DIV_MSB 15
1656 #define CM_AVEODIV_DIV_LSB 12
1657 #define CM_EMMCCTL HW_REGISTER_RW( 0x7e1011c0 )
1658 #define CM_EMMCCTL_MASK 0x000003bf
1659 #define CM_EMMCCTL_WIDTH 10
1660 #define CM_EMMCCTL_RESET 0000000000
1661 #define CM_EMMCCTL_FRAC_BITS 9:9
1662 #define CM_EMMCCTL_FRAC_SET 0x00000200
1663 #define CM_EMMCCTL_FRAC_CLR 0xfffffdff
1664 #define CM_EMMCCTL_FRAC_MSB 9
1665 #define CM_EMMCCTL_FRAC_LSB 9
1666 #define CM_EMMCCTL_BUSYD_BITS 8:8
1667 #define CM_EMMCCTL_BUSYD_SET 0x00000100
1668 #define CM_EMMCCTL_BUSYD_CLR 0xfffffeff
1669 #define CM_EMMCCTL_BUSYD_MSB 8
1670 #define CM_EMMCCTL_BUSYD_LSB 8
1671 #define CM_EMMCCTL_BUSY_BITS 7:7
1672 #define CM_EMMCCTL_BUSY_SET 0x00000080
1673 #define CM_EMMCCTL_BUSY_CLR 0xffffff7f
1674 #define CM_EMMCCTL_BUSY_MSB 7
1675 #define CM_EMMCCTL_BUSY_LSB 7
1676 #define CM_EMMCCTL_KILL_BITS 5:5
1677 #define CM_EMMCCTL_KILL_SET 0x00000020
1678 #define CM_EMMCCTL_KILL_CLR 0xffffffdf
1679 #define CM_EMMCCTL_KILL_MSB 5
1680 #define CM_EMMCCTL_KILL_LSB 5
1681 #define CM_EMMCCTL_ENAB_BITS 4:4
1682 #define CM_EMMCCTL_ENAB_SET 0x00000010
1683 #define CM_EMMCCTL_ENAB_CLR 0xffffffef
1684 #define CM_EMMCCTL_ENAB_MSB 4
1685 #define CM_EMMCCTL_ENAB_LSB 4
1686 #define CM_EMMCCTL_SRC_BITS 3:0
1687 #define CM_EMMCCTL_SRC_SET 0x0000000f
1688 #define CM_EMMCCTL_SRC_CLR 0xfffffff0
1689 #define CM_EMMCCTL_SRC_MSB 3
1690 #define CM_EMMCCTL_SRC_LSB 0
1691 #define CM_EMMCDIV HW_REGISTER_RW( 0x7e1011c4 )
1692 #define CM_EMMCDIV_MASK 0x0000fff0
1693 #define CM_EMMCDIV_WIDTH 16
1694 #define CM_EMMCDIV_RESET 0000000000
1695 #define CM_EMMCDIV_DIV_BITS 15:4
1696 #define CM_EMMCDIV_DIV_SET 0x0000fff0
1697 #define CM_EMMCDIV_DIV_CLR 0xffff000f
1698 #define CM_EMMCDIV_DIV_MSB 15
1699 #define CM_EMMCDIV_DIV_LSB 4
1700 #define CM_OSCCOUNT HW_REGISTER_RW( 0x7e101100 )
1701 #define CM_OSCCOUNT_MASK 0x00ffffff
1702 #define CM_OSCCOUNT_WIDTH 24
1703 #define CM_OSCCOUNT_RESET 0000000000
1704 #define CM_OSCCOUNT_NUM_BITS 23:0
1705 #define CM_OSCCOUNT_NUM_SET 0x00ffffff
1706 #define CM_OSCCOUNT_NUM_CLR 0xff000000
1707 #define CM_OSCCOUNT_NUM_MSB 23
1708 #define CM_OSCCOUNT_NUM_LSB 0
1709 #define CM_PLLA HW_REGISTER_RW( 0x7e101104 )
1710 #define CM_PLLA_MASK 0x000003ff
1711 #define CM_PLLA_WIDTH 10
1712 #define CM_PLLA_RESET 0x00000300
1713 #define CM_PLLA_DIGRST_BITS 9:9
1714 #define CM_PLLA_DIGRST_SET 0x00000200
1715 #define CM_PLLA_DIGRST_CLR 0xfffffdff
1716 #define CM_PLLA_DIGRST_MSB 9
1717 #define CM_PLLA_DIGRST_LSB 9
1718 #define CM_PLLA_ANARST_BITS 8:8
1719 #define CM_PLLA_ANARST_SET 0x00000100
1720 #define CM_PLLA_ANARST_CLR 0xfffffeff
1721 #define CM_PLLA_ANARST_MSB 8
1722 #define CM_PLLA_ANARST_LSB 8
1723 #define CM_PLLA_HOLDPER_BITS 7:7
1724 #define CM_PLLA_HOLDPER_SET 0x00000080
1725 #define CM_PLLA_HOLDPER_CLR 0xffffff7f
1726 #define CM_PLLA_HOLDPER_MSB 7
1727 #define CM_PLLA_HOLDPER_LSB 7
1728 #define CM_PLLA_LOADPER_BITS 6:6
1729 #define CM_PLLA_LOADPER_SET 0x00000040
1730 #define CM_PLLA_LOADPER_CLR 0xffffffbf
1731 #define CM_PLLA_LOADPER_MSB 6
1732 #define CM_PLLA_LOADPER_LSB 6
1733 #define CM_PLLA_HOLDCORE_BITS 5:5
1734 #define CM_PLLA_HOLDCORE_SET 0x00000020
1735 #define CM_PLLA_HOLDCORE_CLR 0xffffffdf
1736 #define CM_PLLA_HOLDCORE_MSB 5
1737 #define CM_PLLA_HOLDCORE_LSB 5
1738 #define CM_PLLA_LOADCORE_BITS 4:4
1739 #define CM_PLLA_LOADCORE_SET 0x00000010
1740 #define CM_PLLA_LOADCORE_CLR 0xffffffef
1741 #define CM_PLLA_LOADCORE_MSB 4
1742 #define CM_PLLA_LOADCORE_LSB 4
1743 #define CM_PLLA_HOLDCCP2_BITS 3:3
1744 #define CM_PLLA_HOLDCCP2_SET 0x00000008
1745 #define CM_PLLA_HOLDCCP2_CLR 0xfffffff7
1746 #define CM_PLLA_HOLDCCP2_MSB 3
1747 #define CM_PLLA_HOLDCCP2_LSB 3
1748 #define CM_PLLA_LOADCCP2_BITS 2:2
1749 #define CM_PLLA_LOADCCP2_SET 0x00000004
1750 #define CM_PLLA_LOADCCP2_CLR 0xfffffffb
1751 #define CM_PLLA_LOADCCP2_MSB 2
1752 #define CM_PLLA_LOADCCP2_LSB 2
1753 #define CM_PLLA_HOLDDSI0_BITS 1:1
1754 #define CM_PLLA_HOLDDSI0_SET 0x00000002
1755 #define CM_PLLA_HOLDDSI0_CLR 0xfffffffd
1756 #define CM_PLLA_HOLDDSI0_MSB 1
1757 #define CM_PLLA_HOLDDSI0_LSB 1
1758 #define CM_PLLA_LOADDSI0_BITS 0:0
1759 #define CM_PLLA_LOADDSI0_SET 0x00000001
1760 #define CM_PLLA_LOADDSI0_CLR 0xfffffffe
1761 #define CM_PLLA_LOADDSI0_MSB 0
1762 #define CM_PLLA_LOADDSI0_LSB 0
1763 #define CM_PLLB HW_REGISTER_RW( 0x7e101170 )
1764 #define CM_PLLB_MASK 0x00000303
1765 #define CM_PLLB_WIDTH 10
1766 #define CM_PLLB_RESET 0x00000300
1767 #define CM_PLLB_DIGRST_BITS 9:9
1768 #define CM_PLLB_DIGRST_SET 0x00000200
1769 #define CM_PLLB_DIGRST_CLR 0xfffffdff
1770 #define CM_PLLB_DIGRST_MSB 9
1771 #define CM_PLLB_DIGRST_LSB 9
1772 #define CM_PLLB_ANARST_BITS 8:8
1773 #define CM_PLLB_ANARST_SET 0x00000100
1774 #define CM_PLLB_ANARST_CLR 0xfffffeff
1775 #define CM_PLLB_ANARST_MSB 8
1776 #define CM_PLLB_ANARST_LSB 8
1777 #define CM_PLLB_HOLDARM_BITS 1:1
1778 #define CM_PLLB_HOLDARM_SET 0x00000002
1779 #define CM_PLLB_HOLDARM_CLR 0xfffffffd
1780 #define CM_PLLB_HOLDARM_MSB 1
1781 #define CM_PLLB_HOLDARM_LSB 1
1782 #define CM_PLLB_LOADARM_BITS 0:0
1783 #define CM_PLLB_LOADARM_SET 0x00000001
1784 #define CM_PLLB_LOADARM_CLR 0xfffffffe
1785 #define CM_PLLB_LOADARM_MSB 0
1786 #define CM_PLLB_LOADARM_LSB 0
1787 #define CM_PLLC HW_REGISTER_RW( 0x7e101108 )
1788 #define CM_PLLC_MASK 0x000003ff
1789 #define CM_PLLC_WIDTH 10
1790 #define CM_PLLC_RESET 0x00000300
1791 #define CM_PLLC_DIGRST_BITS 9:9
1792 #define CM_PLLC_DIGRST_SET 0x00000200
1793 #define CM_PLLC_DIGRST_CLR 0xfffffdff
1794 #define CM_PLLC_DIGRST_MSB 9
1795 #define CM_PLLC_DIGRST_LSB 9
1796 #define CM_PLLC_ANARST_BITS 8:8
1797 #define CM_PLLC_ANARST_SET 0x00000100
1798 #define CM_PLLC_ANARST_CLR 0xfffffeff
1799 #define CM_PLLC_ANARST_MSB 8
1800 #define CM_PLLC_ANARST_LSB 8
1801 #define CM_PLLC_HOLDPER_BITS 7:7
1802 #define CM_PLLC_HOLDPER_SET 0x00000080
1803 #define CM_PLLC_HOLDPER_CLR 0xffffff7f
1804 #define CM_PLLC_HOLDPER_MSB 7
1805 #define CM_PLLC_HOLDPER_LSB 7
1806 #define CM_PLLC_LOADPER_BITS 6:6
1807 #define CM_PLLC_LOADPER_SET 0x00000040
1808 #define CM_PLLC_LOADPER_CLR 0xffffffbf
1809 #define CM_PLLC_LOADPER_MSB 6
1810 #define CM_PLLC_LOADPER_LSB 6
1811 #define CM_PLLC_HOLDCORE2_BITS 5:5
1812 #define CM_PLLC_HOLDCORE2_SET 0x00000020
1813 #define CM_PLLC_HOLDCORE2_CLR 0xffffffdf
1814 #define CM_PLLC_HOLDCORE2_MSB 5
1815 #define CM_PLLC_HOLDCORE2_LSB 5
1816 #define CM_PLLC_LOADCORE2_BITS 4:4
1817 #define CM_PLLC_LOADCORE2_SET 0x00000010
1818 #define CM_PLLC_LOADCORE2_CLR 0xffffffef
1819 #define CM_PLLC_LOADCORE2_MSB 4
1820 #define CM_PLLC_LOADCORE2_LSB 4
1821 #define CM_PLLC_HOLDCORE1_BITS 3:3
1822 #define CM_PLLC_HOLDCORE1_SET 0x00000008
1823 #define CM_PLLC_HOLDCORE1_CLR 0xfffffff7
1824 #define CM_PLLC_HOLDCORE1_MSB 3
1825 #define CM_PLLC_HOLDCORE1_LSB 3
1826 #define CM_PLLC_LOADCORE1_BITS 2:2
1827 #define CM_PLLC_LOADCORE1_SET 0x00000004
1828 #define CM_PLLC_LOADCORE1_CLR 0xfffffffb
1829 #define CM_PLLC_LOADCORE1_MSB 2
1830 #define CM_PLLC_LOADCORE1_LSB 2
1831 #define CM_PLLC_HOLDCORE0_BITS 1:1
1832 #define CM_PLLC_HOLDCORE0_SET 0x00000002
1833 #define CM_PLLC_HOLDCORE0_CLR 0xfffffffd
1834 #define CM_PLLC_HOLDCORE0_MSB 1
1835 #define CM_PLLC_HOLDCORE0_LSB 1
1836 #define CM_PLLC_LOADCORE0_BITS 0:0
1837 #define CM_PLLC_LOADCORE0_SET 0x00000001
1838 #define CM_PLLC_LOADCORE0_CLR 0xfffffffe
1839 #define CM_PLLC_LOADCORE0_MSB 0
1840 #define CM_PLLC_LOADCORE0_LSB 0
1841 #define CM_PLLD HW_REGISTER_RW( 0x7e10110c )
1842 #define CM_PLLD_MASK 0x000003ff
1843 #define CM_PLLD_WIDTH 10
1844 #define CM_PLLD_RESET 0x00000300
1845 #define CM_PLLD_DIGRST_BITS 9:9
1846 #define CM_PLLD_DIGRST_SET 0x00000200
1847 #define CM_PLLD_DIGRST_CLR 0xfffffdff
1848 #define CM_PLLD_DIGRST_MSB 9
1849 #define CM_PLLD_DIGRST_LSB 9
1850 #define CM_PLLD_ANARST_BITS 8:8
1851 #define CM_PLLD_ANARST_SET 0x00000100
1852 #define CM_PLLD_ANARST_CLR 0xfffffeff
1853 #define CM_PLLD_ANARST_MSB 8
1854 #define CM_PLLD_ANARST_LSB 8
1855 #define CM_PLLD_HOLDPER_BITS 7:7
1856 #define CM_PLLD_HOLDPER_SET 0x00000080
1857 #define CM_PLLD_HOLDPER_CLR 0xffffff7f
1858 #define CM_PLLD_HOLDPER_MSB 7
1859 #define CM_PLLD_HOLDPER_LSB 7
1860 #define CM_PLLD_LOADPER_BITS 6:6
1861 #define CM_PLLD_LOADPER_SET 0x00000040
1862 #define CM_PLLD_LOADPER_CLR 0xffffffbf
1863 #define CM_PLLD_LOADPER_MSB 6
1864 #define CM_PLLD_LOADPER_LSB 6
1865 #define CM_PLLD_HOLDCORE_BITS 5:5
1866 #define CM_PLLD_HOLDCORE_SET 0x00000020
1867 #define CM_PLLD_HOLDCORE_CLR 0xffffffdf
1868 #define CM_PLLD_HOLDCORE_MSB 5
1869 #define CM_PLLD_HOLDCORE_LSB 5
1870 #define CM_PLLD_LOADCORE_BITS 4:4
1871 #define CM_PLLD_LOADCORE_SET 0x00000010
1872 #define CM_PLLD_LOADCORE_CLR 0xffffffef
1873 #define CM_PLLD_LOADCORE_MSB 4
1874 #define CM_PLLD_LOADCORE_LSB 4
1875 #define CM_PLLD_HOLDDSI1_BITS 3:3
1876 #define CM_PLLD_HOLDDSI1_SET 0x00000008
1877 #define CM_PLLD_HOLDDSI1_CLR 0xfffffff7
1878 #define CM_PLLD_HOLDDSI1_MSB 3
1879 #define CM_PLLD_HOLDDSI1_LSB 3
1880 #define CM_PLLD_LOADDSI1_BITS 2:2
1881 #define CM_PLLD_LOADDSI1_SET 0x00000004
1882 #define CM_PLLD_LOADDSI1_CLR 0xfffffffb
1883 #define CM_PLLD_LOADDSI1_MSB 2
1884 #define CM_PLLD_LOADDSI1_LSB 2
1885 #define CM_PLLD_HOLDDSI0_BITS 1:1
1886 #define CM_PLLD_HOLDDSI0_SET 0x00000002
1887 #define CM_PLLD_HOLDDSI0_CLR 0xfffffffd
1888 #define CM_PLLD_HOLDDSI0_MSB 1
1889 #define CM_PLLD_HOLDDSI0_LSB 1
1890 #define CM_PLLD_LOADDSI0_BITS 0:0
1891 #define CM_PLLD_LOADDSI0_SET 0x00000001
1892 #define CM_PLLD_LOADDSI0_CLR 0xfffffffe
1893 #define CM_PLLD_LOADDSI0_MSB 0
1894 #define CM_PLLD_LOADDSI0_LSB 0
1895 #define CM_PLLH HW_REGISTER_RW( 0x7e101110 )
1896 #define CM_PLLH_MASK 0x00000307
1897 #define CM_PLLH_WIDTH 10
1898 #define CM_PLLH_RESET 0x00000300
1899 #define CM_PLLH_DIGRST_BITS 9:9
1900 #define CM_PLLH_DIGRST_SET 0x00000200
1901 #define CM_PLLH_DIGRST_CLR 0xfffffdff
1902 #define CM_PLLH_DIGRST_MSB 9
1903 #define CM_PLLH_DIGRST_LSB 9
1904 #define CM_PLLH_ANARST_BITS 8:8
1905 #define CM_PLLH_ANARST_SET 0x00000100
1906 #define CM_PLLH_ANARST_CLR 0xfffffeff
1907 #define CM_PLLH_ANARST_MSB 8
1908 #define CM_PLLH_ANARST_LSB 8
1909 #define CM_PLLH_LOADRCAL_BITS 2:2
1910 #define CM_PLLH_LOADRCAL_SET 0x00000004
1911 #define CM_PLLH_LOADRCAL_CLR 0xfffffffb
1912 #define CM_PLLH_LOADRCAL_MSB 2
1913 #define CM_PLLH_LOADRCAL_LSB 2
1914 #define CM_PLLH_LOADAUX_BITS 1:1
1915 #define CM_PLLH_LOADAUX_SET 0x00000002
1916 #define CM_PLLH_LOADAUX_CLR 0xfffffffd
1917 #define CM_PLLH_LOADAUX_MSB 1
1918 #define CM_PLLH_LOADAUX_LSB 1
1919 #define CM_PLLH_LOADPIX_BITS 0:0
1920 #define CM_PLLH_LOADPIX_SET 0x00000001
1921 #define CM_PLLH_LOADPIX_CLR 0xfffffffe
1922 #define CM_PLLH_LOADPIX_MSB 0
1923 #define CM_PLLH_LOADPIX_LSB 0
1924 #define CM_LOCK HW_REGISTER_RW( 0x7e101114 )
1925 #define CM_LOCK_MASK 0x00001f1f
1926 #define CM_LOCK_WIDTH 13
1927 #define CM_LOCK_RESET 0000000000
1928 #define CM_LOCK_FLOCKH_BITS 12:12
1929 #define CM_LOCK_FLOCKH_SET 0x00001000
1930 #define CM_LOCK_FLOCKH_CLR 0xffffefff
1931 #define CM_LOCK_FLOCKH_MSB 12
1932 #define CM_LOCK_FLOCKH_LSB 12
1933 #define CM_LOCK_FLOCKD_BITS 11:11
1934 #define CM_LOCK_FLOCKD_SET 0x00000800
1935 #define CM_LOCK_FLOCKD_CLR 0xfffff7ff
1936 #define CM_LOCK_FLOCKD_MSB 11
1937 #define CM_LOCK_FLOCKD_LSB 11
1938 #define CM_LOCK_FLOCKC_BITS 10:10
1939 #define CM_LOCK_FLOCKC_SET 0x00000400
1940 #define CM_LOCK_FLOCKC_CLR 0xfffffbff
1941 #define CM_LOCK_FLOCKC_MSB 10
1942 #define CM_LOCK_FLOCKC_LSB 10
1943 #define CM_LOCK_FLOCKB_BITS 9:9
1944 #define CM_LOCK_FLOCKB_SET 0x00000200
1945 #define CM_LOCK_FLOCKB_CLR 0xfffffdff
1946 #define CM_LOCK_FLOCKB_MSB 9
1947 #define CM_LOCK_FLOCKB_LSB 9
1948 #define CM_LOCK_FLOCKA_BITS 8:8
1949 #define CM_LOCK_FLOCKA_SET 0x00000100
1950 #define CM_LOCK_FLOCKA_CLR 0xfffffeff
1951 #define CM_LOCK_FLOCKA_MSB 8
1952 #define CM_LOCK_FLOCKA_LSB 8
1953 #define CM_LOCK_LOCKH_BITS 4:4
1954 #define CM_LOCK_LOCKH_SET 0x00000010
1955 #define CM_LOCK_LOCKH_CLR 0xffffffef
1956 #define CM_LOCK_LOCKH_MSB 4
1957 #define CM_LOCK_LOCKH_LSB 4
1958 #define CM_LOCK_LOCKD_BITS 3:3
1959 #define CM_LOCK_LOCKD_SET 0x00000008
1960 #define CM_LOCK_LOCKD_CLR 0xfffffff7
1961 #define CM_LOCK_LOCKD_MSB 3
1962 #define CM_LOCK_LOCKD_LSB 3
1963 #define CM_LOCK_LOCKC_BITS 2:2
1964 #define CM_LOCK_LOCKC_SET 0x00000004
1965 #define CM_LOCK_LOCKC_CLR 0xfffffffb
1966 #define CM_LOCK_LOCKC_MSB 2
1967 #define CM_LOCK_LOCKC_LSB 2
1968 #define CM_LOCK_LOCKB_BITS 1:1
1969 #define CM_LOCK_LOCKB_SET 0x00000002
1970 #define CM_LOCK_LOCKB_CLR 0xfffffffd
1971 #define CM_LOCK_LOCKB_MSB 1
1972 #define CM_LOCK_LOCKB_LSB 1
1973 #define CM_LOCK_LOCKA_BITS 0:0
1974 #define CM_LOCK_LOCKA_SET 0x00000001
1975 #define CM_LOCK_LOCKA_CLR 0xfffffffe
1976 #define CM_LOCK_LOCKA_MSB 0
1977 #define CM_LOCK_LOCKA_LSB 0
1978 #define CM_EVENT HW_REGISTER_RW( 0x7e101118 )
1979 #define CM_EVENT_MASK 0x00ffffff
1980 #define CM_EVENT_WIDTH 24
1981 #define CM_EVENT_RESET 0000000000
1982 #define CM_EVENT_BURSTDONE_BITS 23:23
1983 #define CM_EVENT_BURSTDONE_SET 0x00800000
1984 #define CM_EVENT_BURSTDONE_CLR 0xff7fffff
1985 #define CM_EVENT_BURSTDONE_MSB 23
1986 #define CM_EVENT_BURSTDONE_LSB 23
1987 #define CM_EVENT_RESUS_BITS 22:22
1988 #define CM_EVENT_RESUS_SET 0x00400000
1989 #define CM_EVENT_RESUS_CLR 0xffbfffff
1990 #define CM_EVENT_RESUS_MSB 22
1991 #define CM_EVENT_RESUS_LSB 22
1992 #define CM_EVENT_OCDONE_BITS 21:21
1993 #define CM_EVENT_OCDONE_SET 0x00200000
1994 #define CM_EVENT_OCDONE_CLR 0xffdfffff
1995 #define CM_EVENT_OCDONE_MSB 21
1996 #define CM_EVENT_OCDONE_LSB 21
1997 #define CM_EVENT_A2WDONE_BITS 20:20
1998 #define CM_EVENT_A2WDONE_SET 0x00100000
1999 #define CM_EVENT_A2WDONE_CLR 0xffefffff
2000 #define CM_EVENT_A2WDONE_MSB 20
2001 #define CM_EVENT_A2WDONE_LSB 20
2002 #define CM_EVENT_WRFAIL_BITS 19:19
2003 #define CM_EVENT_WRFAIL_SET 0x00080000
2004 #define CM_EVENT_WRFAIL_CLR 0xfff7ffff
2005 #define CM_EVENT_WRFAIL_MSB 19
2006 #define CM_EVENT_WRFAIL_LSB 19
2007 #define CM_EVENT_BADPASS_BITS 18:18
2008 #define CM_EVENT_BADPASS_SET 0x00040000
2009 #define CM_EVENT_BADPASS_CLR 0xfffbffff
2010 #define CM_EVENT_BADPASS_MSB 18
2011 #define CM_EVENT_BADPASS_LSB 18
2012 #define CM_EVENT_FLOSSD_BITS 17:17
2013 #define CM_EVENT_FLOSSD_SET 0x00020000
2014 #define CM_EVENT_FLOSSD_CLR 0xfffdffff
2015 #define CM_EVENT_FLOSSD_MSB 17
2016 #define CM_EVENT_FLOSSD_LSB 17
2017 #define CM_EVENT_FLOSSC_BITS 16:16
2018 #define CM_EVENT_FLOSSC_SET 0x00010000
2019 #define CM_EVENT_FLOSSC_CLR 0xfffeffff
2020 #define CM_EVENT_FLOSSC_MSB 16
2021 #define CM_EVENT_FLOSSC_LSB 16
2022 #define CM_EVENT_FLOSSB_BITS 15:15
2023 #define CM_EVENT_FLOSSB_SET 0x00008000
2024 #define CM_EVENT_FLOSSB_CLR 0xffff7fff
2025 #define CM_EVENT_FLOSSB_MSB 15
2026 #define CM_EVENT_FLOSSB_LSB 15
2027 #define CM_EVENT_FLOSSA_BITS 14:14
2028 #define CM_EVENT_FLOSSA_SET 0x00004000
2029 #define CM_EVENT_FLOSSA_CLR 0xffffbfff
2030 #define CM_EVENT_FLOSSA_MSB 14
2031 #define CM_EVENT_FLOSSA_LSB 14
2032 #define CM_EVENT_FGAIND_BITS 13:13
2033 #define CM_EVENT_FGAIND_SET 0x00002000
2034 #define CM_EVENT_FGAIND_CLR 0xffffdfff
2035 #define CM_EVENT_FGAIND_MSB 13
2036 #define CM_EVENT_FGAIND_LSB 13
2037 #define CM_EVENT_FGAINC_BITS 12:12
2038 #define CM_EVENT_FGAINC_SET 0x00001000
2039 #define CM_EVENT_FGAINC_CLR 0xffffefff
2040 #define CM_EVENT_FGAINC_MSB 12
2041 #define CM_EVENT_FGAINC_LSB 12
2042 #define CM_EVENT_FGAINB_BITS 11:11
2043 #define CM_EVENT_FGAINB_SET 0x00000800
2044 #define CM_EVENT_FGAINB_CLR 0xfffff7ff
2045 #define CM_EVENT_FGAINB_MSB 11
2046 #define CM_EVENT_FGAINB_LSB 11
2047 #define CM_EVENT_FGAINA_BITS 10:10
2048 #define CM_EVENT_FGAINA_SET 0x00000400
2049 #define CM_EVENT_FGAINA_CLR 0xfffffbff
2050 #define CM_EVENT_FGAINA_MSB 10
2051 #define CM_EVENT_FGAINA_LSB 10
2052 #define CM_EVENT_LOSSH_BITS 9:9
2053 #define CM_EVENT_LOSSH_SET 0x00000200
2054 #define CM_EVENT_LOSSH_CLR 0xfffffdff
2055 #define CM_EVENT_LOSSH_MSB 9
2056 #define CM_EVENT_LOSSH_LSB 9
2057 #define CM_EVENT_LOSSD_BITS 8:8
2058 #define CM_EVENT_LOSSD_SET 0x00000100
2059 #define CM_EVENT_LOSSD_CLR 0xfffffeff
2060 #define CM_EVENT_LOSSD_MSB 8
2061 #define CM_EVENT_LOSSD_LSB 8
2062 #define CM_EVENT_LOSSC_BITS 7:7
2063 #define CM_EVENT_LOSSC_SET 0x00000080
2064 #define CM_EVENT_LOSSC_CLR 0xffffff7f
2065 #define CM_EVENT_LOSSC_MSB 7
2066 #define CM_EVENT_LOSSC_LSB 7
2067 #define CM_EVENT_LOSSB_BITS 6:6
2068 #define CM_EVENT_LOSSB_SET 0x00000040
2069 #define CM_EVENT_LOSSB_CLR 0xffffffbf
2070 #define CM_EVENT_LOSSB_MSB 6
2071 #define CM_EVENT_LOSSB_LSB 6
2072 #define CM_EVENT_LOSSA_BITS 5:5
2073 #define CM_EVENT_LOSSA_SET 0x00000020
2074 #define CM_EVENT_LOSSA_CLR 0xffffffdf
2075 #define CM_EVENT_LOSSA_MSB 5
2076 #define CM_EVENT_LOSSA_LSB 5
2077 #define CM_EVENT_GAINH_BITS 4:4
2078 #define CM_EVENT_GAINH_SET 0x00000010
2079 #define CM_EVENT_GAINH_CLR 0xffffffef
2080 #define CM_EVENT_GAINH_MSB 4
2081 #define CM_EVENT_GAINH_LSB 4
2082 #define CM_EVENT_GAIND_BITS 3:3
2083 #define CM_EVENT_GAIND_SET 0x00000008
2084 #define CM_EVENT_GAIND_CLR 0xfffffff7
2085 #define CM_EVENT_GAIND_MSB 3
2086 #define CM_EVENT_GAIND_LSB 3
2087 #define CM_EVENT_GAINC_BITS 2:2
2088 #define CM_EVENT_GAINC_SET 0x00000004
2089 #define CM_EVENT_GAINC_CLR 0xfffffffb
2090 #define CM_EVENT_GAINC_MSB 2
2091 #define CM_EVENT_GAINC_LSB 2
2092 #define CM_EVENT_GAINB_BITS 1:1
2093 #define CM_EVENT_GAINB_SET 0x00000002
2094 #define CM_EVENT_GAINB_CLR 0xfffffffd
2095 #define CM_EVENT_GAINB_MSB 1
2096 #define CM_EVENT_GAINB_LSB 1
2097 #define CM_EVENT_GAINA_BITS 0:0
2098 #define CM_EVENT_GAINA_SET 0x00000001
2099 #define CM_EVENT_GAINA_CLR 0xfffffffe
2100 #define CM_EVENT_GAINA_MSB 0
2101 #define CM_EVENT_GAINA_LSB 0
2102 #define CM_INTEN HW_REGISTER_RW( 0x7e10111c )
2103 #define CM_INTEN_MASK 0x00ffffff
2104 #define CM_INTEN_WIDTH 24
2105 #define CM_INTEN_RESET 0000000000
2106 #define CM_INTEN_BURSTDONE_BITS 23:23
2107 #define CM_INTEN_BURSTDONE_SET 0x00800000
2108 #define CM_INTEN_BURSTDONE_CLR 0xff7fffff
2109 #define CM_INTEN_BURSTDONE_MSB 23
2110 #define CM_INTEN_BURSTDONE_LSB 23
2111 #define CM_INTEN_RESUS_BITS 22:22
2112 #define CM_INTEN_RESUS_SET 0x00400000
2113 #define CM_INTEN_RESUS_CLR 0xffbfffff
2114 #define CM_INTEN_RESUS_MSB 22
2115 #define CM_INTEN_RESUS_LSB 22
2116 #define CM_INTEN_OCDONE_BITS 21:21
2117 #define CM_INTEN_OCDONE_SET 0x00200000
2118 #define CM_INTEN_OCDONE_CLR 0xffdfffff
2119 #define CM_INTEN_OCDONE_MSB 21
2120 #define CM_INTEN_OCDONE_LSB 21
2121 #define CM_INTEN_A2WDONE_BITS 20:20
2122 #define CM_INTEN_A2WDONE_SET 0x00100000
2123 #define CM_INTEN_A2WDONE_CLR 0xffefffff
2124 #define CM_INTEN_A2WDONE_MSB 20
2125 #define CM_INTEN_A2WDONE_LSB 20
2126 #define CM_INTEN_WRFAIL_BITS 19:19
2127 #define CM_INTEN_WRFAIL_SET 0x00080000
2128 #define CM_INTEN_WRFAIL_CLR 0xfff7ffff
2129 #define CM_INTEN_WRFAIL_MSB 19
2130 #define CM_INTEN_WRFAIL_LSB 19
2131 #define CM_INTEN_BADPASS_BITS 18:18
2132 #define CM_INTEN_BADPASS_SET 0x00040000
2133 #define CM_INTEN_BADPASS_CLR 0xfffbffff
2134 #define CM_INTEN_BADPASS_MSB 18
2135 #define CM_INTEN_BADPASS_LSB 18
2136 #define CM_INTEN_FLOSSD_BITS 17:17
2137 #define CM_INTEN_FLOSSD_SET 0x00020000
2138 #define CM_INTEN_FLOSSD_CLR 0xfffdffff
2139 #define CM_INTEN_FLOSSD_MSB 17
2140 #define CM_INTEN_FLOSSD_LSB 17
2141 #define CM_INTEN_FLOSSC_BITS 16:16
2142 #define CM_INTEN_FLOSSC_SET 0x00010000
2143 #define CM_INTEN_FLOSSC_CLR 0xfffeffff
2144 #define CM_INTEN_FLOSSC_MSB 16
2145 #define CM_INTEN_FLOSSC_LSB 16
2146 #define CM_INTEN_FLOSSB_BITS 15:15
2147 #define CM_INTEN_FLOSSB_SET 0x00008000
2148 #define CM_INTEN_FLOSSB_CLR 0xffff7fff
2149 #define CM_INTEN_FLOSSB_MSB 15
2150 #define CM_INTEN_FLOSSB_LSB 15
2151 #define CM_INTEN_FLOSSA_BITS 14:14
2152 #define CM_INTEN_FLOSSA_SET 0x00004000
2153 #define CM_INTEN_FLOSSA_CLR 0xffffbfff
2154 #define CM_INTEN_FLOSSA_MSB 14
2155 #define CM_INTEN_FLOSSA_LSB 14
2156 #define CM_INTEN_FGAIND_BITS 13:13
2157 #define CM_INTEN_FGAIND_SET 0x00002000
2158 #define CM_INTEN_FGAIND_CLR 0xffffdfff
2159 #define CM_INTEN_FGAIND_MSB 13
2160 #define CM_INTEN_FGAIND_LSB 13
2161 #define CM_INTEN_FGAINC_BITS 12:12
2162 #define CM_INTEN_FGAINC_SET 0x00001000
2163 #define CM_INTEN_FGAINC_CLR 0xffffefff
2164 #define CM_INTEN_FGAINC_MSB 12
2165 #define CM_INTEN_FGAINC_LSB 12
2166 #define CM_INTEN_FGAINB_BITS 11:11
2167 #define CM_INTEN_FGAINB_SET 0x00000800
2168 #define CM_INTEN_FGAINB_CLR 0xfffff7ff
2169 #define CM_INTEN_FGAINB_MSB 11
2170 #define CM_INTEN_FGAINB_LSB 11
2171 #define CM_INTEN_FGAINA_BITS 10:10
2172 #define CM_INTEN_FGAINA_SET 0x00000400
2173 #define CM_INTEN_FGAINA_CLR 0xfffffbff
2174 #define CM_INTEN_FGAINA_MSB 10
2175 #define CM_INTEN_FGAINA_LSB 10
2176 #define CM_INTEN_LOSSH_BITS 9:9
2177 #define CM_INTEN_LOSSH_SET 0x00000200
2178 #define CM_INTEN_LOSSH_CLR 0xfffffdff
2179 #define CM_INTEN_LOSSH_MSB 9
2180 #define CM_INTEN_LOSSH_LSB 9
2181 #define CM_INTEN_LOSSD_BITS 8:8
2182 #define CM_INTEN_LOSSD_SET 0x00000100
2183 #define CM_INTEN_LOSSD_CLR 0xfffffeff
2184 #define CM_INTEN_LOSSD_MSB 8
2185 #define CM_INTEN_LOSSD_LSB 8
2186 #define CM_INTEN_LOSSC_BITS 7:7
2187 #define CM_INTEN_LOSSC_SET 0x00000080
2188 #define CM_INTEN_LOSSC_CLR 0xffffff7f
2189 #define CM_INTEN_LOSSC_MSB 7
2190 #define CM_INTEN_LOSSC_LSB 7
2191 #define CM_INTEN_LOSSB_BITS 6:6
2192 #define CM_INTEN_LOSSB_SET 0x00000040
2193 #define CM_INTEN_LOSSB_CLR 0xffffffbf
2194 #define CM_INTEN_LOSSB_MSB 6
2195 #define CM_INTEN_LOSSB_LSB 6
2196 #define CM_INTEN_LOSSA_BITS 5:5
2197 #define CM_INTEN_LOSSA_SET 0x00000020
2198 #define CM_INTEN_LOSSA_CLR 0xffffffdf
2199 #define CM_INTEN_LOSSA_MSB 5
2200 #define CM_INTEN_LOSSA_LSB 5
2201 #define CM_INTEN_GAINH_BITS 4:4
2202 #define CM_INTEN_GAINH_SET 0x00000010
2203 #define CM_INTEN_GAINH_CLR 0xffffffef
2204 #define CM_INTEN_GAINH_MSB 4
2205 #define CM_INTEN_GAINH_LSB 4
2206 #define CM_INTEN_GAIND_BITS 3:3
2207 #define CM_INTEN_GAIND_SET 0x00000008
2208 #define CM_INTEN_GAIND_CLR 0xfffffff7
2209 #define CM_INTEN_GAIND_MSB 3
2210 #define CM_INTEN_GAIND_LSB 3
2211 #define CM_INTEN_GAINC_BITS 2:2
2212 #define CM_INTEN_GAINC_SET 0x00000004
2213 #define CM_INTEN_GAINC_CLR 0xfffffffb
2214 #define CM_INTEN_GAINC_MSB 2
2215 #define CM_INTEN_GAINC_LSB 2
2216 #define CM_INTEN_GAINB_BITS 1:1
2217 #define CM_INTEN_GAINB_SET 0x00000002
2218 #define CM_INTEN_GAINB_CLR 0xfffffffd
2219 #define CM_INTEN_GAINB_MSB 1
2220 #define CM_INTEN_GAINB_LSB 1
2221 #define CM_INTEN_GAINA_BITS 0:0
2222 #define CM_INTEN_GAINA_SET 0x00000001
2223 #define CM_INTEN_GAINA_CLR 0xfffffffe
2224 #define CM_INTEN_GAINA_MSB 0
2225 #define CM_INTEN_GAINA_LSB 0
2226 #define CM_DSI0HSCK HW_REGISTER_RW( 0x7e101120 )
2227 #define CM_DSI0HSCK_MASK 0x00000001
2228 #define CM_DSI0HSCK_WIDTH 1
2229 #define CM_DSI0HSCK_RESET 0000000000
2230 #define CM_DSI0HSCK_SELPLLD_BITS 0:0
2231 #define CM_DSI0HSCK_SELPLLD_SET 0x00000001
2232 #define CM_DSI0HSCK_SELPLLD_CLR 0xfffffffe
2233 #define CM_DSI0HSCK_SELPLLD_MSB 0
2234 #define CM_DSI0HSCK_SELPLLD_LSB 0
2235 #define CM_CKSM HW_REGISTER_RW( 0x7e101124 )
2236 #define CM_CKSM_MASK 0x003fffff
2237 #define CM_CKSM_WIDTH 22
2238 #define CM_CKSM_RESET 0000000000
2239 #define CM_CKSM_STEP_BITS 21:21
2240 #define CM_CKSM_STEP_SET 0x00200000
2241 #define CM_CKSM_STEP_CLR 0xffdfffff
2242 #define CM_CKSM_STEP_MSB 21
2243 #define CM_CKSM_STEP_LSB 21
2244 #define CM_CKSM_AUTO_BITS 20:20
2245 #define CM_CKSM_AUTO_SET 0x00100000
2246 #define CM_CKSM_AUTO_CLR 0xffefffff
2247 #define CM_CKSM_AUTO_MSB 20
2248 #define CM_CKSM_AUTO_LSB 20
2249 #define CM_CKSM_OSC_BITS 19:18
2250 #define CM_CKSM_OSC_SET 0x000c0000
2251 #define CM_CKSM_OSC_CLR 0xfff3ffff
2252 #define CM_CKSM_OSC_MSB 19
2253 #define CM_CKSM_OSC_LSB 18
2254 #define CM_CKSM_CFG_BITS 17:16
2255 #define CM_CKSM_CFG_SET 0x00030000
2256 #define CM_CKSM_CFG_CLR 0xfffcffff
2257 #define CM_CKSM_CFG_MSB 17
2258 #define CM_CKSM_CFG_LSB 16
2259 #define CM_CKSM_FRCE_BITS 15:8
2260 #define CM_CKSM_FRCE_SET 0x0000ff00
2261 #define CM_CKSM_FRCE_CLR 0xffff00ff
2262 #define CM_CKSM_FRCE_MSB 15
2263 #define CM_CKSM_FRCE_LSB 8
2264 #define CM_CKSM_STATE_BITS 7:0
2265 #define CM_CKSM_STATE_SET 0x000000ff
2266 #define CM_CKSM_STATE_CLR 0xffffff00
2267 #define CM_CKSM_STATE_MSB 7
2268 #define CM_CKSM_STATE_LSB 0
2269 #define CM_OSCFREQI HW_REGISTER_RW( 0x7e101128 )
2270 #define CM_OSCFREQI_MASK 0x000000ff
2271 #define CM_OSCFREQI_WIDTH 8
2272 #define CM_OSCFREQI_RESET 0000000000
2273 #define CM_OSCFREQI_INT_BITS 7:0
2274 #define CM_OSCFREQI_INT_SET 0x000000ff
2275 #define CM_OSCFREQI_INT_CLR 0xffffff00
2276 #define CM_OSCFREQI_INT_MSB 7
2277 #define CM_OSCFREQI_INT_LSB 0
2278 #define CM_OSCFREQF HW_REGISTER_RW( 0x7e10112c )
2279 #define CM_OSCFREQF_MASK 0x000fffff
2280 #define CM_OSCFREQF_WIDTH 20
2281 #define CM_OSCFREQF_RESET 0000000000
2282 #define CM_OSCFREQF_FRAC_BITS 19:0
2283 #define CM_OSCFREQF_FRAC_SET 0x000fffff
2284 #define CM_OSCFREQF_FRAC_CLR 0xfff00000
2285 #define CM_OSCFREQF_FRAC_MSB 19
2286 #define CM_OSCFREQF_FRAC_LSB 0
2287 #define CM_PLLTCTL HW_REGISTER_RW( 0x7e101130 )
2288 #define CM_PLLTCTL_MASK 0x000000a7
2289 #define CM_PLLTCTL_WIDTH 8
2290 #define CM_PLLTCTL_RESET 0000000000
2291 #define CM_PLLTCTL_BUSY_BITS 7:7
2292 #define CM_PLLTCTL_BUSY_SET 0x00000080
2293 #define CM_PLLTCTL_BUSY_CLR 0xffffff7f
2294 #define CM_PLLTCTL_BUSY_MSB 7
2295 #define CM_PLLTCTL_BUSY_LSB 7
2296 #define CM_PLLTCTL_KILL_BITS 5:5
2297 #define CM_PLLTCTL_KILL_SET 0x00000020
2298 #define CM_PLLTCTL_KILL_CLR 0xffffffdf
2299 #define CM_PLLTCTL_KILL_MSB 5
2300 #define CM_PLLTCTL_KILL_LSB 5
2301 #define CM_PLLTCTL_SRC_BITS 2:0
2302 #define CM_PLLTCTL_SRC_SET 0x00000007
2303 #define CM_PLLTCTL_SRC_CLR 0xfffffff8
2304 #define CM_PLLTCTL_SRC_MSB 2
2305 #define CM_PLLTCTL_SRC_LSB 0
2306 #define CM_PLLTCNT0 HW_REGISTER_RW( 0x7e101134 )
2307 #define CM_PLLTCNT0_MASK 0x00ffffff
2308 #define CM_PLLTCNT0_WIDTH 24
2309 #define CM_PLLTCNT0_RESET 0000000000
2310 #define CM_PLLTCNT0_CNT_BITS 23:0
2311 #define CM_PLLTCNT0_CNT_SET 0x00ffffff
2312 #define CM_PLLTCNT0_CNT_CLR 0xff000000
2313 #define CM_PLLTCNT0_CNT_MSB 23
2314 #define CM_PLLTCNT0_CNT_LSB 0
2315 #define CM_PLLTCNT1 HW_REGISTER_RW( 0x7e101138 )
2316 #define CM_PLLTCNT1_MASK 0x00ffffff
2317 #define CM_PLLTCNT1_WIDTH 24
2318 #define CM_PLLTCNT1_RESET 0000000000
2319 #define CM_PLLTCNT1_CNT_BITS 23:0
2320 #define CM_PLLTCNT1_CNT_SET 0x00ffffff
2321 #define CM_PLLTCNT1_CNT_CLR 0xff000000
2322 #define CM_PLLTCNT1_CNT_MSB 23
2323 #define CM_PLLTCNT1_CNT_LSB 0
2324 #define CM_PLLTCNT2 HW_REGISTER_RW( 0x7e10113c )
2325 #define CM_PLLTCNT2_MASK 0x00ffffff
2326 #define CM_PLLTCNT2_WIDTH 24
2327 #define CM_PLLTCNT2_RESET 0000000000
2328 #define CM_PLLTCNT2_CNT_BITS 23:0
2329 #define CM_PLLTCNT2_CNT_SET 0x00ffffff
2330 #define CM_PLLTCNT2_CNT_CLR 0xff000000
2331 #define CM_PLLTCNT2_CNT_MSB 23
2332 #define CM_PLLTCNT2_CNT_LSB 0
2333 #define CM_PLLTCNT3 HW_REGISTER_RW( 0x7e101140 )
2334 #define CM_PLLTCNT3_MASK 0x00ffffff
2335 #define CM_PLLTCNT3_WIDTH 24
2336 #define CM_PLLTCNT3_RESET 0000000000
2337 #define CM_PLLTCNT3_CNT_BITS 23:0
2338 #define CM_PLLTCNT3_CNT_SET 0x00ffffff
2339 #define CM_PLLTCNT3_CNT_CLR 0xff000000
2340 #define CM_PLLTCNT3_CNT_MSB 23
2341 #define CM_PLLTCNT3_CNT_LSB 0
2342 #define CM_TDCLKEN HW_REGISTER_RW( 0x7e101144 )
2343 #define CM_TDCLKEN_MASK 0x00003fff
2344 #define CM_TDCLKEN_WIDTH 14
2345 #define CM_TDCLKEN_RESET 0000000000
2346 #define CM_TDCLKEN_IMAGETD_BITS 13:13
2347 #define CM_TDCLKEN_IMAGETD_SET 0x00002000
2348 #define CM_TDCLKEN_IMAGETD_CLR 0xffffdfff
2349 #define CM_TDCLKEN_IMAGETD_MSB 13
2350 #define CM_TDCLKEN_IMAGETD_LSB 13
2351 #define CM_TDCLKEN_SLIMDFT_BITS 12:12
2352 #define CM_TDCLKEN_SLIMDFT_SET 0x00001000
2353 #define CM_TDCLKEN_SLIMDFT_CLR 0xffffefff
2354 #define CM_TDCLKEN_SLIMDFT_MSB 12
2355 #define CM_TDCLKEN_SLIMDFT_LSB 12
2356 #define CM_TDCLKEN_USBDFT_BITS 11:11
2357 #define CM_TDCLKEN_USBDFT_SET 0x00000800
2358 #define CM_TDCLKEN_USBDFT_CLR 0xfffff7ff
2359 #define CM_TDCLKEN_USBDFT_MSB 11
2360 #define CM_TDCLKEN_USBDFT_LSB 11
2361 #define CM_TDCLKEN_MPHIRDFT_BITS 10:10
2362 #define CM_TDCLKEN_MPHIRDFT_SET 0x00000400
2363 #define CM_TDCLKEN_MPHIRDFT_CLR 0xfffffbff
2364 #define CM_TDCLKEN_MPHIRDFT_MSB 10
2365 #define CM_TDCLKEN_MPHIRDFT_LSB 10
2366 #define CM_TDCLKEN_MPHIWDFT_BITS 9:9
2367 #define CM_TDCLKEN_MPHIWDFT_SET 0x00000200
2368 #define CM_TDCLKEN_MPHIWDFT_CLR 0xfffffdff
2369 #define CM_TDCLKEN_MPHIWDFT_MSB 9
2370 #define CM_TDCLKEN_MPHIWDFT_LSB 9
2371 #define CM_TDCLKEN_HDMIBYP_BITS 8:8
2372 #define CM_TDCLKEN_HDMIBYP_SET 0x00000100
2373 #define CM_TDCLKEN_HDMIBYP_CLR 0xfffffeff
2374 #define CM_TDCLKEN_HDMIBYP_MSB 8
2375 #define CM_TDCLKEN_HDMIBYP_LSB 8
2376 #define CM_TDCLKEN_PLLDDIV2_BITS 7:7
2377 #define CM_TDCLKEN_PLLDDIV2_SET 0x00000080
2378 #define CM_TDCLKEN_PLLDDIV2_CLR 0xffffff7f
2379 #define CM_TDCLKEN_PLLDDIV2_MSB 7
2380 #define CM_TDCLKEN_PLLDDIV2_LSB 7
2381 #define CM_TDCLKEN_PLLCDIV2_BITS 6:6
2382 #define CM_TDCLKEN_PLLCDIV2_SET 0x00000040
2383 #define CM_TDCLKEN_PLLCDIV2_CLR 0xffffffbf
2384 #define CM_TDCLKEN_PLLCDIV2_MSB 6
2385 #define CM_TDCLKEN_PLLCDIV2_LSB 6
2386 #define CM_TDCLKEN_PLLBDIV2_BITS 5:5
2387 #define CM_TDCLKEN_PLLBDIV2_SET 0x00000020
2388 #define CM_TDCLKEN_PLLBDIV2_CLR 0xffffffdf
2389 #define CM_TDCLKEN_PLLBDIV2_MSB 5
2390 #define CM_TDCLKEN_PLLBDIV2_LSB 5
2391 #define CM_TDCLKEN_PLLADIV2_BITS 4:4
2392 #define CM_TDCLKEN_PLLADIV2_SET 0x00000010
2393 #define CM_TDCLKEN_PLLADIV2_CLR 0xffffffef
2394 #define CM_TDCLKEN_PLLADIV2_MSB 4
2395 #define CM_TDCLKEN_PLLADIV2_LSB 4
2396 #define CM_TDCLKEN_PLLDBYP_BITS 3:3
2397 #define CM_TDCLKEN_PLLDBYP_SET 0x00000008
2398 #define CM_TDCLKEN_PLLDBYP_CLR 0xfffffff7
2399 #define CM_TDCLKEN_PLLDBYP_MSB 3
2400 #define CM_TDCLKEN_PLLDBYP_LSB 3
2401 #define CM_TDCLKEN_PLLCBYP_BITS 2:2
2402 #define CM_TDCLKEN_PLLCBYP_SET 0x00000004
2403 #define CM_TDCLKEN_PLLCBYP_CLR 0xfffffffb
2404 #define CM_TDCLKEN_PLLCBYP_MSB 2
2405 #define CM_TDCLKEN_PLLCBYP_LSB 2
2406 #define CM_TDCLKEN_PLLBBYP_BITS 1:1
2407 #define CM_TDCLKEN_PLLBBYP_SET 0x00000002
2408 #define CM_TDCLKEN_PLLBBYP_CLR 0xfffffffd
2409 #define CM_TDCLKEN_PLLBBYP_MSB 1
2410 #define CM_TDCLKEN_PLLBBYP_LSB 1
2411 #define CM_TDCLKEN_PLLABYP_BITS 0:0
2412 #define CM_TDCLKEN_PLLABYP_SET 0x00000001
2413 #define CM_TDCLKEN_PLLABYP_CLR 0xfffffffe
2414 #define CM_TDCLKEN_PLLABYP_MSB 0
2415 #define CM_TDCLKEN_PLLABYP_LSB 0
2416 #define CM_BURSTCTL HW_REGISTER_RW( 0x7e101148 )
2417 #define CM_BURSTCTL_MASK 0x000000b0
2418 #define CM_BURSTCTL_WIDTH 8
2419 #define CM_BURSTCTL_RESET 0000000000
2420 #define CM_BURSTCTL_BUSY_BITS 7:7
2421 #define CM_BURSTCTL_BUSY_SET 0x00000080
2422 #define CM_BURSTCTL_BUSY_CLR 0xffffff7f
2423 #define CM_BURSTCTL_BUSY_MSB 7
2424 #define CM_BURSTCTL_BUSY_LSB 7
2425 #define CM_BURSTCTL_KILL_BITS 5:5
2426 #define CM_BURSTCTL_KILL_SET 0x00000020
2427 #define CM_BURSTCTL_KILL_CLR 0xffffffdf
2428 #define CM_BURSTCTL_KILL_MSB 5
2429 #define CM_BURSTCTL_KILL_LSB 5
2430 #define CM_BURSTCTL_ENAB_BITS 4:4
2431 #define CM_BURSTCTL_ENAB_SET 0x00000010
2432 #define CM_BURSTCTL_ENAB_CLR 0xffffffef
2433 #define CM_BURSTCTL_ENAB_MSB 4
2434 #define CM_BURSTCTL_ENAB_LSB 4
2435 #define CM_BURSTCNT HW_REGISTER_RW( 0x7e10114c )
2436 #define CM_BURSTCNT_MASK 0x00ffffff
2437 #define CM_BURSTCNT_WIDTH 24
2438 #define CM_BURSTCNT_RESET 0000000000
2439 #define CM_BURSTCNT_CNT_BITS 23:0
2440 #define CM_BURSTCNT_CNT_SET 0x00ffffff
2441 #define CM_BURSTCNT_CNT_CLR 0xff000000
2442 #define CM_BURSTCNT_CNT_MSB 23
2443 #define CM_BURSTCNT_CNT_LSB 0
2444 #define CM_STOPCLK HW_REGISTER_RW( 0x7e101150 )
2445 #define CM_STOPCLK_MASK 0x00000001
2446 #define CM_STOPCLK_WIDTH 1
2447 #define CM_STOPCLK_RESET 0000000000
2448 #define CM_STOPCLK_ALL_BITS 0:0
2449 #define CM_STOPCLK_ALL_SET 0x00000001
2450 #define CM_STOPCLK_ALL_CLR 0xfffffffe
2451 #define CM_STOPCLK_ALL_MSB 0
2452 #define CM_STOPCLK_ALL_LSB 0
2453
2454 #else
2455
2456 // This file was generated by the create_regs script
2457 #define CM_PASSWORD 0x5a000000
2458 #define CM_BASE 0x7e101000
2459 #define CM_APB_ID 0x0000636d
2460 #define CM_GNRICCTL HW_REGISTER_RW( 0x7e101000 )
2461 #define CM_GNRICCTL_MASK 0x000fffff
2462 #define CM_GNRICCTL_WIDTH 20
2463 #define CM_GNRICCTL_RESET 0000000000
2464 #define CM_GNRICCTL_MASH_BITS 10:9
2465 #define CM_GNRICCTL_MASH_SET 0x00000600
2466 #define CM_GNRICCTL_MASH_CLR 0xfffff9ff
2467 #define CM_GNRICCTL_MASH_MSB 10
2468 #define CM_GNRICCTL_MASH_LSB 9
2469 #define CM_GNRICCTL_FLIP_BITS 8:8
2470 #define CM_GNRICCTL_FLIP_SET 0x00000100
2471 #define CM_GNRICCTL_FLIP_CLR 0xfffffeff
2472 #define CM_GNRICCTL_FLIP_MSB 8
2473 #define CM_GNRICCTL_FLIP_LSB 8
2474 #define CM_GNRICCTL_BUSY_BITS 7:7
2475 #define CM_GNRICCTL_BUSY_SET 0x00000080
2476 #define CM_GNRICCTL_BUSY_CLR 0xffffff7f
2477 #define CM_GNRICCTL_BUSY_MSB 7
2478 #define CM_GNRICCTL_BUSY_LSB 7
2479 #define CM_GNRICCTL_GATE_BITS 6:6
2480 #define CM_GNRICCTL_GATE_SET 0x00000040
2481 #define CM_GNRICCTL_GATE_CLR 0xffffffbf
2482 #define CM_GNRICCTL_GATE_MSB 6
2483 #define CM_GNRICCTL_GATE_LSB 6
2484 #define CM_GNRICCTL_KILL_BITS 5:5
2485 #define CM_GNRICCTL_KILL_SET 0x00000020
2486 #define CM_GNRICCTL_KILL_CLR 0xffffffdf
2487 #define CM_GNRICCTL_KILL_MSB 5
2488 #define CM_GNRICCTL_KILL_LSB 5
2489 #define CM_GNRICCTL_ENAB_BITS 4:4
2490 #define CM_GNRICCTL_ENAB_SET 0x00000010
2491 #define CM_GNRICCTL_ENAB_CLR 0xffffffef
2492 #define CM_GNRICCTL_ENAB_MSB 4
2493 #define CM_GNRICCTL_ENAB_LSB 4
2494 #define CM_GNRICCTL_SRC_BITS 3:0
2495 #define CM_GNRICCTL_SRC_SET 0x0000000f
2496 #define CM_GNRICCTL_SRC_CLR 0xfffffff0
2497 #define CM_GNRICCTL_SRC_MSB 3
2498 #define CM_GNRICCTL_SRC_LSB 0
2499 #define CM_GNRICDIV HW_REGISTER_RW( 0x7e101004 )
2500 #define CM_GNRICDIV_MASK 0x00ffffff
2501 #define CM_GNRICDIV_WIDTH 24
2502 #define CM_GNRICDIV_RESET 0000000000
2503 #define CM_GNRICDIV_DIV_BITS 23:0
2504 #define CM_GNRICDIV_DIV_SET 0x00ffffff
2505 #define CM_GNRICDIV_DIV_CLR 0xff000000
2506 #define CM_GNRICDIV_DIV_MSB 23
2507 #define CM_GNRICDIV_DIV_LSB 0
2508 #define CM_VPUCTL HW_REGISTER_RW( 0x7e101008 )
2509 #define CM_VPUCTL_MASK 0x000000cf
2510 #define CM_VPUCTL_WIDTH 8
2511 #define CM_VPUCTL_RESET 0x00000041
2512 #define CM_VPUCTL_BUSY_BITS 7:7
2513 #define CM_VPUCTL_BUSY_SET 0x00000080
2514 #define CM_VPUCTL_BUSY_CLR 0xffffff7f
2515 #define CM_VPUCTL_BUSY_MSB 7
2516 #define CM_VPUCTL_BUSY_LSB 7
2517 #define CM_VPUCTL_GATE_BITS 6:6
2518 #define CM_VPUCTL_GATE_SET 0x00000040
2519 #define CM_VPUCTL_GATE_CLR 0xffffffbf
2520 #define CM_VPUCTL_GATE_MSB 6
2521 #define CM_VPUCTL_GATE_LSB 6
2522 #define CM_VPUCTL_SRC_BITS 3:0
2523 #define CM_VPUCTL_SRC_SET 0x0000000f
2524 #define CM_VPUCTL_SRC_CLR 0xfffffff0
2525 #define CM_VPUCTL_SRC_MSB 3
2526 #define CM_VPUCTL_SRC_LSB 0
2527 #define CM_VPUDIV HW_REGISTER_RW( 0x7e10100c )
2528 #define CM_VPUDIV_MASK 0x00fffff0
2529 #define CM_VPUDIV_WIDTH 24
2530 #define CM_VPUDIV_RESET 0x00001000
2531 #define CM_VPUDIV_DIV_BITS 23:4
2532 #define CM_VPUDIV_DIV_SET 0x00fffff0
2533 #define CM_VPUDIV_DIV_CLR 0xff00000f
2534 #define CM_VPUDIV_DIV_MSB 23
2535 #define CM_VPUDIV_DIV_LSB 4
2536 #define CM_SYSCTL HW_REGISTER_RW( 0x7e101010 )
2537 #define CM_SYSCTL_MASK 0x00000040
2538 #define CM_SYSCTL_WIDTH 7
2539 #define CM_SYSCTL_RESET 0x00000040
2540 #define CM_SYSCTL_GATE_BITS 6:6
2541 #define CM_SYSCTL_GATE_SET 0x00000040
2542 #define CM_SYSCTL_GATE_CLR 0xffffffbf
2543 #define CM_SYSCTL_GATE_MSB 6
2544 #define CM_SYSCTL_GATE_LSB 6
2545 #define CM_SYSDIV HW_REGISTER_RO( 0x7e101014 )
2546 #define CM_SYSDIV_MASK 0x00001000
2547 #define CM_SYSDIV_WIDTH 13
2548 #define CM_SYSDIV_RESET 0x00001000
2549 #define CM_SYSDIV_DIV_BITS 12:12
2550 #define CM_SYSDIV_DIV_SET 0x00001000
2551 #define CM_SYSDIV_DIV_CLR 0xffffefff
2552 #define CM_SYSDIV_DIV_MSB 12
2553 #define CM_SYSDIV_DIV_LSB 12
2554 #define CM_PERIACTL HW_REGISTER_RW( 0x7e101018 )
2555 #define CM_PERIACTL_MASK 0x00000040
2556 #define CM_PERIACTL_WIDTH 7
2557 #define CM_PERIACTL_RESET 0x00000040
2558 #define CM_PERIACTL_GATE_BITS 6:6
2559 #define CM_PERIACTL_GATE_SET 0x00000040
2560 #define CM_PERIACTL_GATE_CLR 0xffffffbf
2561 #define CM_PERIACTL_GATE_MSB 6
2562 #define CM_PERIACTL_GATE_LSB 6
2563 #define CM_PERIADIV HW_REGISTER_RO( 0x7e10101c )
2564 #define CM_PERIADIV_MASK 0x00001000
2565 #define CM_PERIADIV_WIDTH 13
2566 #define CM_PERIADIV_RESET 0x00001000
2567 #define CM_PERIADIV_DIV_BITS 12:12
2568 #define CM_PERIADIV_DIV_SET 0x00001000
2569 #define CM_PERIADIV_DIV_CLR 0xffffefff
2570 #define CM_PERIADIV_DIV_MSB 12
2571 #define CM_PERIADIV_DIV_LSB 12
2572 #define CM_PERIICTL HW_REGISTER_RW( 0x7e101020 )
2573 #define CM_PERIICTL_MASK 0x00000040
2574 #define CM_PERIICTL_WIDTH 7
2575 #define CM_PERIICTL_RESET 0000000000
2576 #define CM_PERIICTL_GATE_BITS 6:6
2577 #define CM_PERIICTL_GATE_SET 0x00000040
2578 #define CM_PERIICTL_GATE_CLR 0xffffffbf
2579 #define CM_PERIICTL_GATE_MSB 6
2580 #define CM_PERIICTL_GATE_LSB 6
2581 #define CM_PERIIDIV HW_REGISTER_RO( 0x7e101024 )
2582 #define CM_PERIIDIV_MASK 0x00001000
2583 #define CM_PERIIDIV_WIDTH 13
2584 #define CM_PERIIDIV_RESET 0x00001000
2585 #define CM_PERIIDIV_DIV_BITS 12:12
2586 #define CM_PERIIDIV_DIV_SET 0x00001000
2587 #define CM_PERIIDIV_DIV_CLR 0xffffefff
2588 #define CM_PERIIDIV_DIV_MSB 12
2589 #define CM_PERIIDIV_DIV_LSB 12
2590 #define CM_H264CTL HW_REGISTER_RW( 0x7e101028 )
2591 #define CM_H264CTL_MASK 0x000000ff
2592 #define CM_H264CTL_WIDTH 8
2593 #define CM_H264CTL_RESET 0x00000040
2594 #define CM_H264CTL_BUSY_BITS 7:7
2595 #define CM_H264CTL_BUSY_SET 0x00000080
2596 #define CM_H264CTL_BUSY_CLR 0xffffff7f
2597 #define CM_H264CTL_BUSY_MSB 7
2598 #define CM_H264CTL_BUSY_LSB 7
2599 #define CM_H264CTL_GATE_BITS 6:6
2600 #define CM_H264CTL_GATE_SET 0x00000040
2601 #define CM_H264CTL_GATE_CLR 0xffffffbf
2602 #define CM_H264CTL_GATE_MSB 6
2603 #define CM_H264CTL_GATE_LSB 6
2604 #define CM_H264CTL_KILL_BITS 5:5
2605 #define CM_H264CTL_KILL_SET 0x00000020
2606 #define CM_H264CTL_KILL_CLR 0xffffffdf
2607 #define CM_H264CTL_KILL_MSB 5
2608 #define CM_H264CTL_KILL_LSB 5
2609 #define CM_H264CTL_ENAB_BITS 4:4
2610 #define CM_H264CTL_ENAB_SET 0x00000010
2611 #define CM_H264CTL_ENAB_CLR 0xffffffef
2612 #define CM_H264CTL_ENAB_MSB 4
2613 #define CM_H264CTL_ENAB_LSB 4
2614 #define CM_H264CTL_SRC_BITS 3:0
2615 #define CM_H264CTL_SRC_SET 0x0000000f
2616 #define CM_H264CTL_SRC_CLR 0xfffffff0
2617 #define CM_H264CTL_SRC_MSB 3
2618 #define CM_H264CTL_SRC_LSB 0
2619 #define CM_H264DIV HW_REGISTER_RW( 0x7e10102c )
2620 #define CM_H264DIV_MASK 0x0000fff0
2621 #define CM_H264DIV_WIDTH 16
2622 #define CM_H264DIV_RESET 0000000000
2623 #define CM_H264DIV_DIV_BITS 15:4
2624 #define CM_H264DIV_DIV_SET 0x0000fff0
2625 #define CM_H264DIV_DIV_CLR 0xffff000f
2626 #define CM_H264DIV_DIV_MSB 15
2627 #define CM_H264DIV_DIV_LSB 4
2628 #define CM_ISPCTL HW_REGISTER_RW( 0x7e101030 )
2629 #define CM_ISPCTL_MASK 0x000000ff
2630 #define CM_ISPCTL_WIDTH 8
2631 #define CM_ISPCTL_RESET 0x00000040
2632 #define CM_ISPCTL_BUSY_BITS 7:7
2633 #define CM_ISPCTL_BUSY_SET 0x00000080
2634 #define CM_ISPCTL_BUSY_CLR 0xffffff7f
2635 #define CM_ISPCTL_BUSY_MSB 7
2636 #define CM_ISPCTL_BUSY_LSB 7
2637 #define CM_ISPCTL_GATE_BITS 6:6
2638 #define CM_ISPCTL_GATE_SET 0x00000040
2639 #define CM_ISPCTL_GATE_CLR 0xffffffbf
2640 #define CM_ISPCTL_GATE_MSB 6
2641 #define CM_ISPCTL_GATE_LSB 6
2642 #define CM_ISPCTL_KILL_BITS 5:5
2643 #define CM_ISPCTL_KILL_SET 0x00000020
2644 #define CM_ISPCTL_KILL_CLR 0xffffffdf
2645 #define CM_ISPCTL_KILL_MSB 5
2646 #define CM_ISPCTL_KILL_LSB 5
2647 #define CM_ISPCTL_ENAB_BITS 4:4
2648 #define CM_ISPCTL_ENAB_SET 0x00000010
2649 #define CM_ISPCTL_ENAB_CLR 0xffffffef
2650 #define CM_ISPCTL_ENAB_MSB 4
2651 #define CM_ISPCTL_ENAB_LSB 4
2652 #define CM_ISPCTL_SRC_BITS 3:0
2653 #define CM_ISPCTL_SRC_SET 0x0000000f
2654 #define CM_ISPCTL_SRC_CLR 0xfffffff0
2655 #define CM_ISPCTL_SRC_MSB 3
2656 #define CM_ISPCTL_SRC_LSB 0
2657 #define CM_ISPDIV HW_REGISTER_RW( 0x7e101034 )
2658 #define CM_ISPDIV_MASK 0x0000fff0
2659 #define CM_ISPDIV_WIDTH 16
2660 #define CM_ISPDIV_RESET 0000000000
2661 #define CM_ISPDIV_DIV_BITS 15:4
2662 #define CM_ISPDIV_DIV_SET 0x0000fff0
2663 #define CM_ISPDIV_DIV_CLR 0xffff000f
2664 #define CM_ISPDIV_DIV_MSB 15
2665 #define CM_ISPDIV_DIV_LSB 4
2666 #define CM_ARMCTL HW_REGISTER_RW( 0x7e1011b0 )
2667 #define CM_ARMCTL_MASK 0x000011b3
2668 #define CM_ARMCTL_WIDTH 13
2669 #define CM_ARMCTL_RESET 0000000000
2670 #define CM_ARMCTL_AXIHALF_BITS 12:12
2671 #define CM_ARMCTL_AXIHALF_SET 0x00001000
2672 #define CM_ARMCTL_AXIHALF_CLR 0xffffefff
2673 #define CM_ARMCTL_AXIHALF_MSB 12
2674 #define CM_ARMCTL_AXIHALF_LSB 12
2675 #define CM_ARMCTL_FLIP_BITS 8:8
2676 #define CM_ARMCTL_FLIP_SET 0x00000100
2677 #define CM_ARMCTL_FLIP_CLR 0xfffffeff
2678 #define CM_ARMCTL_FLIP_MSB 8
2679 #define CM_ARMCTL_FLIP_LSB 8
2680 #define CM_ARMCTL_BUSY_BITS 7:7
2681 #define CM_ARMCTL_BUSY_SET 0x00000080
2682 #define CM_ARMCTL_BUSY_CLR 0xffffff7f
2683 #define CM_ARMCTL_BUSY_MSB 7
2684 #define CM_ARMCTL_BUSY_LSB 7
2685 #define CM_ARMCTL_KILL_BITS 5:5
2686 #define CM_ARMCTL_KILL_SET 0x00000020
2687 #define CM_ARMCTL_KILL_CLR 0xffffffdf
2688 #define CM_ARMCTL_KILL_MSB 5
2689 #define CM_ARMCTL_KILL_LSB 5
2690 #define CM_ARMCTL_ENAB_BITS 4:4
2691 #define CM_ARMCTL_ENAB_SET 0x00000010
2692 #define CM_ARMCTL_ENAB_CLR 0xffffffef
2693 #define CM_ARMCTL_ENAB_MSB 4
2694 #define CM_ARMCTL_ENAB_LSB 4
2695 #define CM_ARMCTL_SRC_BITS 1:0
2696 #define CM_ARMCTL_SRC_SET 0x00000003
2697 #define CM_ARMCTL_SRC_CLR 0xfffffffc
2698 #define CM_ARMCTL_SRC_MSB 1
2699 #define CM_ARMCTL_SRC_LSB 0
2700 #define CM_ARMDIV HW_REGISTER_RO( 0x7e1011b4 )
2701 #define CM_ARMDIV_MASK 0x00001000
2702 #define CM_ARMDIV_WIDTH 13
2703 #define CM_ARMDIV_RESET 0x00001000
2704 #define CM_ARMDIV_DIV_BITS 12:12
2705 #define CM_ARMDIV_DIV_SET 0x00001000
2706 #define CM_ARMDIV_DIV_CLR 0xffffefff
2707 #define CM_ARMDIV_DIV_MSB 12
2708 #define CM_ARMDIV_DIV_LSB 12
2709 #define CM_SDCCTL HW_REGISTER_RW( 0x7e1011a8 )
2710 #define CM_SDCCTL_MASK 0x0003f0bf
2711 #define CM_SDCCTL_WIDTH 18
2712 #define CM_SDCCTL_RESET 0x00004000
2713 #define CM_SDCCTL_UPDATE_BITS 17:17
2714 #define CM_SDCCTL_UPDATE_SET 0x00020000
2715 #define CM_SDCCTL_UPDATE_CLR 0xfffdffff
2716 #define CM_SDCCTL_UPDATE_MSB 17
2717 #define CM_SDCCTL_UPDATE_LSB 17
2718 #define CM_SDCCTL_ACCPT_BITS 16:16
2719 #define CM_SDCCTL_ACCPT_SET 0x00010000
2720 #define CM_SDCCTL_ACCPT_CLR 0xfffeffff
2721 #define CM_SDCCTL_ACCPT_MSB 16
2722 #define CM_SDCCTL_ACCPT_LSB 16
2723 #define CM_SDCCTL_CTRL_BITS 15:12
2724 #define CM_SDCCTL_CTRL_SET 0x0000f000
2725 #define CM_SDCCTL_CTRL_CLR 0xffff0fff
2726 #define CM_SDCCTL_CTRL_MSB 15
2727 #define CM_SDCCTL_CTRL_LSB 12
2728 #define CM_SDCCTL_BUSY_BITS 7:7
2729 #define CM_SDCCTL_BUSY_SET 0x00000080
2730 #define CM_SDCCTL_BUSY_CLR 0xffffff7f
2731 #define CM_SDCCTL_BUSY_MSB 7
2732 #define CM_SDCCTL_BUSY_LSB 7
2733 #define CM_SDCCTL_KILL_BITS 5:5
2734 #define CM_SDCCTL_KILL_SET 0x00000020
2735 #define CM_SDCCTL_KILL_CLR 0xffffffdf
2736 #define CM_SDCCTL_KILL_MSB 5
2737 #define CM_SDCCTL_KILL_LSB 5
2738 #define CM_SDCCTL_ENAB_BITS 4:4
2739 #define CM_SDCCTL_ENAB_SET 0x00000010
2740 #define CM_SDCCTL_ENAB_CLR 0xffffffef
2741 #define CM_SDCCTL_ENAB_MSB 4
2742 #define CM_SDCCTL_ENAB_LSB 4
2743 #define CM_SDCCTL_SRC_BITS 3:0
2744 #define CM_SDCCTL_SRC_SET 0x0000000f
2745 #define CM_SDCCTL_SRC_CLR 0xfffffff0
2746 #define CM_SDCCTL_SRC_MSB 3
2747 #define CM_SDCCTL_SRC_LSB 0
2748 #define CM_SDCDIV HW_REGISTER_RW( 0x7e1011ac )
2749 #define CM_SDCDIV_MASK 0x0003f000
2750 #define CM_SDCDIV_WIDTH 18
2751 #define CM_SDCDIV_RESET 0000000000
2752 #define CM_SDCDIV_DIV_BITS 17:12
2753 #define CM_SDCDIV_DIV_SET 0x0003f000
2754 #define CM_SDCDIV_DIV_CLR 0xfffc0fff
2755 #define CM_SDCDIV_DIV_MSB 17
2756 #define CM_SDCDIV_DIV_LSB 12
2757 #define CM_V3DCTL HW_REGISTER_RW( 0x7e101038 )
2758 #define CM_V3DCTL_MASK 0x000000ff
2759 #define CM_V3DCTL_WIDTH 8
2760 #define CM_V3DCTL_RESET 0x00000040
2761 #define CM_V3DCTL_BUSY_BITS 7:7
2762 #define CM_V3DCTL_BUSY_SET 0x00000080
2763 #define CM_V3DCTL_BUSY_CLR 0xffffff7f
2764 #define CM_V3DCTL_BUSY_MSB 7
2765 #define CM_V3DCTL_BUSY_LSB 7
2766 #define CM_V3DCTL_GATE_BITS 6:6
2767 #define CM_V3DCTL_GATE_SET 0x00000040
2768 #define CM_V3DCTL_GATE_CLR 0xffffffbf
2769 #define CM_V3DCTL_GATE_MSB 6
2770 #define CM_V3DCTL_GATE_LSB 6
2771 #define CM_V3DCTL_KILL_BITS 5:5
2772 #define CM_V3DCTL_KILL_SET 0x00000020
2773 #define CM_V3DCTL_KILL_CLR 0xffffffdf
2774 #define CM_V3DCTL_KILL_MSB 5
2775 #define CM_V3DCTL_KILL_LSB 5
2776 #define CM_V3DCTL_ENAB_BITS 4:4
2777 #define CM_V3DCTL_ENAB_SET 0x00000010
2778 #define CM_V3DCTL_ENAB_CLR 0xffffffef
2779 #define CM_V3DCTL_ENAB_MSB 4
2780 #define CM_V3DCTL_ENAB_LSB 4
2781 #define CM_V3DCTL_SRC_BITS 3:0
2782 #define CM_V3DCTL_SRC_SET 0x0000000f
2783 #define CM_V3DCTL_SRC_CLR 0xfffffff0
2784 #define CM_V3DCTL_SRC_MSB 3
2785 #define CM_V3DCTL_SRC_LSB 0
2786 #define CM_V3DDIV HW_REGISTER_RW( 0x7e10103c )
2787 #define CM_V3DDIV_MASK 0x0000fff0
2788 #define CM_V3DDIV_WIDTH 16
2789 #define CM_V3DDIV_RESET 0000000000
2790 #define CM_V3DDIV_DIV_BITS 15:4
2791 #define CM_V3DDIV_DIV_SET 0x0000fff0
2792 #define CM_V3DDIV_DIV_CLR 0xffff000f
2793 #define CM_V3DDIV_DIV_MSB 15
2794 #define CM_V3DDIV_DIV_LSB 4
2795 #define CM_CAM0CTL HW_REGISTER_RW( 0x7e101040 )
2796 #define CM_CAM0CTL_MASK 0x000000bf
2797 #define CM_CAM0CTL_WIDTH 8
2798 #define CM_CAM0CTL_RESET 0000000000
2799 #define CM_CAM0CTL_BUSY_BITS 7:7
2800 #define CM_CAM0CTL_BUSY_SET 0x00000080
2801 #define CM_CAM0CTL_BUSY_CLR 0xffffff7f
2802 #define CM_CAM0CTL_BUSY_MSB 7
2803 #define CM_CAM0CTL_BUSY_LSB 7
2804 #define CM_CAM0CTL_KILL_BITS 5:5
2805 #define CM_CAM0CTL_KILL_SET 0x00000020
2806 #define CM_CAM0CTL_KILL_CLR 0xffffffdf
2807 #define CM_CAM0CTL_KILL_MSB 5
2808 #define CM_CAM0CTL_KILL_LSB 5
2809 #define CM_CAM0CTL_ENAB_BITS 4:4
2810 #define CM_CAM0CTL_ENAB_SET 0x00000010
2811 #define CM_CAM0CTL_ENAB_CLR 0xffffffef
2812 #define CM_CAM0CTL_ENAB_MSB 4
2813 #define CM_CAM0CTL_ENAB_LSB 4
2814 #define CM_CAM0CTL_SRC_BITS 3:0
2815 #define CM_CAM0CTL_SRC_SET 0x0000000f
2816 #define CM_CAM0CTL_SRC_CLR 0xfffffff0
2817 #define CM_CAM0CTL_SRC_MSB 3
2818 #define CM_CAM0CTL_SRC_LSB 0
2819 #define CM_CAM0DIV HW_REGISTER_RW( 0x7e101044 )
2820 #define CM_CAM0DIV_MASK 0x0000fff0
2821 #define CM_CAM0DIV_WIDTH 16
2822 #define CM_CAM0DIV_RESET 0000000000
2823 #define CM_CAM0DIV_DIV_BITS 15:4
2824 #define CM_CAM0DIV_DIV_SET 0x0000fff0
2825 #define CM_CAM0DIV_DIV_CLR 0xffff000f
2826 #define CM_CAM0DIV_DIV_MSB 15
2827 #define CM_CAM0DIV_DIV_LSB 4
2828 #define CM_CAM1CTL HW_REGISTER_RW( 0x7e101048 )
2829 #define CM_CAM1CTL_MASK 0x000000bf
2830 #define CM_CAM1CTL_WIDTH 8
2831 #define CM_CAM1CTL_RESET 0000000000
2832 #define CM_CAM1CTL_BUSY_BITS 7:7
2833 #define CM_CAM1CTL_BUSY_SET 0x00000080
2834 #define CM_CAM1CTL_BUSY_CLR 0xffffff7f
2835 #define CM_CAM1CTL_BUSY_MSB 7
2836 #define CM_CAM1CTL_BUSY_LSB 7
2837 #define CM_CAM1CTL_KILL_BITS 5:5
2838 #define CM_CAM1CTL_KILL_SET 0x00000020
2839 #define CM_CAM1CTL_KILL_CLR 0xffffffdf
2840 #define CM_CAM1CTL_KILL_MSB 5
2841 #define CM_CAM1CTL_KILL_LSB 5
2842 #define CM_CAM1CTL_ENAB_BITS 4:4
2843 #define CM_CAM1CTL_ENAB_SET 0x00000010
2844 #define CM_CAM1CTL_ENAB_CLR 0xffffffef
2845 #define CM_CAM1CTL_ENAB_MSB 4
2846 #define CM_CAM1CTL_ENAB_LSB 4
2847 #define CM_CAM1CTL_SRC_BITS 3:0
2848 #define CM_CAM1CTL_SRC_SET 0x0000000f
2849 #define CM_CAM1CTL_SRC_CLR 0xfffffff0
2850 #define CM_CAM1CTL_SRC_MSB 3
2851 #define CM_CAM1CTL_SRC_LSB 0
2852 #define CM_CAM1DIV HW_REGISTER_RW( 0x7e10104c )
2853 #define CM_CAM1DIV_MASK 0x0000fff0
2854 #define CM_CAM1DIV_WIDTH 16
2855 #define CM_CAM1DIV_RESET 0000000000
2856 #define CM_CAM1DIV_DIV_BITS 15:4
2857 #define CM_CAM1DIV_DIV_SET 0x0000fff0
2858 #define CM_CAM1DIV_DIV_CLR 0xffff000f
2859 #define CM_CAM1DIV_DIV_MSB 15
2860 #define CM_CAM1DIV_DIV_LSB 4
2861 #define CM_CCP2CTL HW_REGISTER_RW( 0x7e101050 )
2862 #define CM_CCP2CTL_MASK 0x00000017
2863 #define CM_CCP2CTL_WIDTH 5
2864 #define CM_CCP2CTL_RESET 0000000000
2865 #define CM_CCP2CTL_ENAB_BITS 4:4
2866 #define CM_CCP2CTL_ENAB_SET 0x00000010
2867 #define CM_CCP2CTL_ENAB_CLR 0xffffffef
2868 #define CM_CCP2CTL_ENAB_MSB 4
2869 #define CM_CCP2CTL_ENAB_LSB 4
2870 #define CM_CCP2CTL_SRC_BITS 2:0
2871 #define CM_CCP2CTL_SRC_SET 0x00000007
2872 #define CM_CCP2CTL_SRC_CLR 0xfffffff8
2873 #define CM_CCP2CTL_SRC_MSB 2
2874 #define CM_CCP2CTL_SRC_LSB 0
2875 #define CM_DSI0ECTL HW_REGISTER_RW( 0x7e101058 )
2876 #define CM_DSI0ECTL_MASK 0x000000bf
2877 #define CM_DSI0ECTL_WIDTH 8
2878 #define CM_DSI0ECTL_RESET 0000000000
2879 #define CM_DSI0ECTL_BUSY_BITS 7:7
2880 #define CM_DSI0ECTL_BUSY_SET 0x00000080
2881 #define CM_DSI0ECTL_BUSY_CLR 0xffffff7f
2882 #define CM_DSI0ECTL_BUSY_MSB 7
2883 #define CM_DSI0ECTL_BUSY_LSB 7
2884 #define CM_DSI0ECTL_KILL_BITS 5:5
2885 #define CM_DSI0ECTL_KILL_SET 0x00000020
2886 #define CM_DSI0ECTL_KILL_CLR 0xffffffdf
2887 #define CM_DSI0ECTL_KILL_MSB 5
2888 #define CM_DSI0ECTL_KILL_LSB 5
2889 #define CM_DSI0ECTL_ENAB_BITS 4:4
2890 #define CM_DSI0ECTL_ENAB_SET 0x00000010
2891 #define CM_DSI0ECTL_ENAB_CLR 0xffffffef
2892 #define CM_DSI0ECTL_ENAB_MSB 4
2893 #define CM_DSI0ECTL_ENAB_LSB 4
2894 #define CM_DSI0ECTL_SRC_BITS 3:0
2895 #define CM_DSI0ECTL_SRC_SET 0x0000000f
2896 #define CM_DSI0ECTL_SRC_CLR 0xfffffff0
2897 #define CM_DSI0ECTL_SRC_MSB 3
2898 #define CM_DSI0ECTL_SRC_LSB 0
2899 #define CM_DSI0EDIV HW_REGISTER_RW( 0x7e10105c )
2900 #define CM_DSI0EDIV_MASK 0x0000fff0
2901 #define CM_DSI0EDIV_WIDTH 16
2902 #define CM_DSI0EDIV_RESET 0000000000
2903 #define CM_DSI0EDIV_DIV_BITS 15:4
2904 #define CM_DSI0EDIV_DIV_SET 0x0000fff0
2905 #define CM_DSI0EDIV_DIV_CLR 0xffff000f
2906 #define CM_DSI0EDIV_DIV_MSB 15
2907 #define CM_DSI0EDIV_DIV_LSB 4
2908 #define CM_DSI0PCTL HW_REGISTER_RW( 0x7e101060 )
2909 #define CM_DSI0PCTL_MASK 0x0000001f
2910 #define CM_DSI0PCTL_WIDTH 5
2911 #define CM_DSI0PCTL_RESET 0000000000
2912 #define CM_DSI0PCTL_ENAB_BITS 4:4
2913 #define CM_DSI0PCTL_ENAB_SET 0x00000010
2914 #define CM_DSI0PCTL_ENAB_CLR 0xffffffef
2915 #define CM_DSI0PCTL_ENAB_MSB 4
2916 #define CM_DSI0PCTL_ENAB_LSB 4
2917 #define CM_DSI0PCTL_SRC_BITS 3:0
2918 #define CM_DSI0PCTL_SRC_SET 0x0000000f
2919 #define CM_DSI0PCTL_SRC_CLR 0xfffffff0
2920 #define CM_DSI0PCTL_SRC_MSB 3
2921 #define CM_DSI0PCTL_SRC_LSB 0
2922 #define CM_DSI1ECTL HW_REGISTER_RW( 0x7e101158 )
2923 #define CM_DSI1ECTL_MASK 0x000000bf
2924 #define CM_DSI1ECTL_WIDTH 8
2925 #define CM_DSI1ECTL_RESET 0000000000
2926 #define CM_DSI1ECTL_BUSY_BITS 7:7
2927 #define CM_DSI1ECTL_BUSY_SET 0x00000080
2928 #define CM_DSI1ECTL_BUSY_CLR 0xffffff7f
2929 #define CM_DSI1ECTL_BUSY_MSB 7
2930 #define CM_DSI1ECTL_BUSY_LSB 7
2931 #define CM_DSI1ECTL_KILL_BITS 5:5
2932 #define CM_DSI1ECTL_KILL_SET 0x00000020
2933 #define CM_DSI1ECTL_KILL_CLR 0xffffffdf
2934 #define CM_DSI1ECTL_KILL_MSB 5
2935 #define CM_DSI1ECTL_KILL_LSB 5
2936 #define CM_DSI1ECTL_ENAB_BITS 4:4
2937 #define CM_DSI1ECTL_ENAB_SET 0x00000010
2938 #define CM_DSI1ECTL_ENAB_CLR 0xffffffef
2939 #define CM_DSI1ECTL_ENAB_MSB 4
2940 #define CM_DSI1ECTL_ENAB_LSB 4
2941 #define CM_DSI1ECTL_SRC_BITS 3:0
2942 #define CM_DSI1ECTL_SRC_SET 0x0000000f
2943 #define CM_DSI1ECTL_SRC_CLR 0xfffffff0
2944 #define CM_DSI1ECTL_SRC_MSB 3
2945 #define CM_DSI1ECTL_SRC_LSB 0
2946 #define CM_DSI1EDIV HW_REGISTER_RW( 0x7e10115c )
2947 #define CM_DSI1EDIV_MASK 0x0000fff0
2948 #define CM_DSI1EDIV_WIDTH 16
2949 #define CM_DSI1EDIV_RESET 0000000000
2950 #define CM_DSI1EDIV_DIV_BITS 15:4
2951 #define CM_DSI1EDIV_DIV_SET 0x0000fff0
2952 #define CM_DSI1EDIV_DIV_CLR 0xffff000f
2953 #define CM_DSI1EDIV_DIV_MSB 15
2954 #define CM_DSI1EDIV_DIV_LSB 4
2955 #define CM_DSI1PCTL HW_REGISTER_RW( 0x7e101160 )
2956 #define CM_DSI1PCTL_MASK 0x0000001f
2957 #define CM_DSI1PCTL_WIDTH 5
2958 #define CM_DSI1PCTL_RESET 0000000000
2959 #define CM_DSI1PCTL_ENAB_BITS 4:4
2960 #define CM_DSI1PCTL_ENAB_SET 0x00000010
2961 #define CM_DSI1PCTL_ENAB_CLR 0xffffffef
2962 #define CM_DSI1PCTL_ENAB_MSB 4
2963 #define CM_DSI1PCTL_ENAB_LSB 4
2964 #define CM_DSI1PCTL_SRC_BITS 3:0
2965 #define CM_DSI1PCTL_SRC_SET 0x0000000f
2966 #define CM_DSI1PCTL_SRC_CLR 0xfffffff0
2967 #define CM_DSI1PCTL_SRC_MSB 3
2968 #define CM_DSI1PCTL_SRC_LSB 0
2969 #define CM_DPICTL HW_REGISTER_RW( 0x7e101068 )
2970 #define CM_DPICTL_MASK 0x000000bf
2971 #define CM_DPICTL_WIDTH 8
2972 #define CM_DPICTL_RESET 0000000000
2973 #define CM_DPICTL_BUSY_BITS 7:7
2974 #define CM_DPICTL_BUSY_SET 0x00000080
2975 #define CM_DPICTL_BUSY_CLR 0xffffff7f
2976 #define CM_DPICTL_BUSY_MSB 7
2977 #define CM_DPICTL_BUSY_LSB 7
2978 #define CM_DPICTL_KILL_BITS 5:5
2979 #define CM_DPICTL_KILL_SET 0x00000020
2980 #define CM_DPICTL_KILL_CLR 0xffffffdf
2981 #define CM_DPICTL_KILL_MSB 5
2982 #define CM_DPICTL_KILL_LSB 5
2983 #define CM_DPICTL_ENAB_BITS 4:4
2984 #define CM_DPICTL_ENAB_SET 0x00000010
2985 #define CM_DPICTL_ENAB_CLR 0xffffffef
2986 #define CM_DPICTL_ENAB_MSB 4
2987 #define CM_DPICTL_ENAB_LSB 4
2988 #define CM_DPICTL_SRC_BITS 3:0
2989 #define CM_DPICTL_SRC_SET 0x0000000f
2990 #define CM_DPICTL_SRC_CLR 0xfffffff0
2991 #define CM_DPICTL_SRC_MSB 3
2992 #define CM_DPICTL_SRC_LSB 0
2993 #define CM_DPIDIV HW_REGISTER_RW( 0x7e10106c )
2994 #define CM_DPIDIV_MASK 0x0000fff0
2995 #define CM_DPIDIV_WIDTH 16
2996 #define CM_DPIDIV_RESET 0000000000
2997 #define CM_DPIDIV_DIV_BITS 15:4
2998 #define CM_DPIDIV_DIV_SET 0x0000fff0
2999 #define CM_DPIDIV_DIV_CLR 0xffff000f
3000 #define CM_DPIDIV_DIV_MSB 15
3001 #define CM_DPIDIV_DIV_LSB 4
3002 #define CM_DFTCTL HW_REGISTER_RW( 0x7e101168 )
3003 #define CM_DFTCTL_MASK 0x000000bf
3004 #define CM_DFTCTL_WIDTH 8
3005 #define CM_DFTCTL_RESET 0000000000
3006 #define CM_DFTCTL_BUSY_BITS 7:7
3007 #define CM_DFTCTL_BUSY_SET 0x00000080
3008 #define CM_DFTCTL_BUSY_CLR 0xffffff7f
3009 #define CM_DFTCTL_BUSY_MSB 7
3010 #define CM_DFTCTL_BUSY_LSB 7
3011 #define CM_DFTCTL_KILL_BITS 5:5
3012 #define CM_DFTCTL_KILL_SET 0x00000020
3013 #define CM_DFTCTL_KILL_CLR 0xffffffdf
3014 #define CM_DFTCTL_KILL_MSB 5
3015 #define CM_DFTCTL_KILL_LSB 5
3016 #define CM_DFTCTL_ENAB_BITS 4:4
3017 #define CM_DFTCTL_ENAB_SET 0x00000010
3018 #define CM_DFTCTL_ENAB_CLR 0xffffffef
3019 #define CM_DFTCTL_ENAB_MSB 4
3020 #define CM_DFTCTL_ENAB_LSB 4
3021 #define CM_DFTCTL_SRC_BITS 3:0
3022 #define CM_DFTCTL_SRC_SET 0x0000000f
3023 #define CM_DFTCTL_SRC_CLR 0xfffffff0
3024 #define CM_DFTCTL_SRC_MSB 3
3025 #define CM_DFTCTL_SRC_LSB 0
3026 #define CM_DFTDIV HW_REGISTER_RW( 0x7e10116c )
3027 #define CM_DFTDIV_MASK 0x0001f000
3028 #define CM_DFTDIV_WIDTH 17
3029 #define CM_DFTDIV_RESET 0000000000
3030 #define CM_DFTDIV_DIV_BITS 16:12
3031 #define CM_DFTDIV_DIV_SET 0x0001f000
3032 #define CM_DFTDIV_DIV_CLR 0xfffe0fff
3033 #define CM_DFTDIV_DIV_MSB 16
3034 #define CM_DFTDIV_DIV_LSB 12
3035 #define CM_GP0CTL HW_REGISTER_RW( 0x7e101070 )
3036 #define CM_GP0CTL_MASK 0x000006bf
3037 #define CM_GP0CTL_WIDTH 11
3038 #define CM_GP0CTL_RESET 0x00000200
3039 #define CM_GP0CTL_MASH_BITS 10:9
3040 #define CM_GP0CTL_MASH_SET 0x00000600
3041 #define CM_GP0CTL_MASH_CLR 0xfffff9ff
3042 #define CM_GP0CTL_MASH_MSB 10
3043 #define CM_GP0CTL_MASH_LSB 9
3044 #define CM_GP0CTL_BUSY_BITS 7:7
3045 #define CM_GP0CTL_BUSY_SET 0x00000080
3046 #define CM_GP0CTL_BUSY_CLR 0xffffff7f
3047 #define CM_GP0CTL_BUSY_MSB 7
3048 #define CM_GP0CTL_BUSY_LSB 7
3049 #define CM_GP0CTL_KILL_BITS 5:5
3050 #define CM_GP0CTL_KILL_SET 0x00000020
3051 #define CM_GP0CTL_KILL_CLR 0xffffffdf
3052 #define CM_GP0CTL_KILL_MSB 5
3053 #define CM_GP0CTL_KILL_LSB 5
3054 #define CM_GP0CTL_ENAB_BITS 4:4
3055 #define CM_GP0CTL_ENAB_SET 0x00000010
3056 #define CM_GP0CTL_ENAB_CLR 0xffffffef
3057 #define CM_GP0CTL_ENAB_MSB 4
3058 #define CM_GP0CTL_ENAB_LSB 4
3059 #define CM_GP0CTL_SRC_BITS 3:0
3060 #define CM_GP0CTL_SRC_SET 0x0000000f
3061 #define CM_GP0CTL_SRC_CLR 0xfffffff0
3062 #define CM_GP0CTL_SRC_MSB 3
3063 #define CM_GP0CTL_SRC_LSB 0
3064 #define CM_GP0DIV HW_REGISTER_RW( 0x7e101074 )
3065 #define CM_GP0DIV_MASK 0x00ffffff
3066 #define CM_GP0DIV_WIDTH 24
3067 #define CM_GP0DIV_RESET 0000000000
3068 #define CM_GP0DIV_DIV_BITS 23:0
3069 #define CM_GP0DIV_DIV_SET 0x00ffffff
3070 #define CM_GP0DIV_DIV_CLR 0xff000000
3071 #define CM_GP0DIV_DIV_MSB 23
3072 #define CM_GP0DIV_DIV_LSB 0
3073 #define CM_GP1CTL HW_REGISTER_RW( 0x7e101078 )
3074 #define CM_GP1CTL_MASK 0x000006bf
3075 #define CM_GP1CTL_WIDTH 11
3076 #define CM_GP1CTL_RESET 0x00000200
3077 #define CM_GP1CTL_MASH_BITS 10:9
3078 #define CM_GP1CTL_MASH_SET 0x00000600
3079 #define CM_GP1CTL_MASH_CLR 0xfffff9ff
3080 #define CM_GP1CTL_MASH_MSB 10
3081 #define CM_GP1CTL_MASH_LSB 9
3082 #define CM_GP1CTL_BUSY_BITS 7:7
3083 #define CM_GP1CTL_BUSY_SET 0x00000080
3084 #define CM_GP1CTL_BUSY_CLR 0xffffff7f
3085 #define CM_GP1CTL_BUSY_MSB 7
3086 #define CM_GP1CTL_BUSY_LSB 7
3087 #define CM_GP1CTL_KILL_BITS 5:5
3088 #define CM_GP1CTL_KILL_SET 0x00000020
3089 #define CM_GP1CTL_KILL_CLR 0xffffffdf
3090 #define CM_GP1CTL_KILL_MSB 5
3091 #define CM_GP1CTL_KILL_LSB 5
3092 #define CM_GP1CTL_ENAB_BITS 4:4
3093 #define CM_GP1CTL_ENAB_SET 0x00000010
3094 #define CM_GP1CTL_ENAB_CLR 0xffffffef
3095 #define CM_GP1CTL_ENAB_MSB 4
3096 #define CM_GP1CTL_ENAB_LSB 4
3097 #define CM_GP1CTL_SRC_BITS 3:0
3098 #define CM_GP1CTL_SRC_SET 0x0000000f
3099 #define CM_GP1CTL_SRC_CLR 0xfffffff0
3100 #define CM_GP1CTL_SRC_MSB 3
3101 #define CM_GP1CTL_SRC_LSB 0
3102 #define CM_GP1DIV HW_REGISTER_RW( 0x7e10107c )
3103 #define CM_GP1DIV_MASK 0x00ffffff
3104 #define CM_GP1DIV_WIDTH 24
3105 #define CM_GP1DIV_RESET 0000000000
3106 #define CM_GP1DIV_DIV_BITS 23:0
3107 #define CM_GP1DIV_DIV_SET 0x00ffffff
3108 #define CM_GP1DIV_DIV_CLR 0xff000000
3109 #define CM_GP1DIV_DIV_MSB 23
3110 #define CM_GP1DIV_DIV_LSB 0
3111 #define CM_GP2CTL HW_REGISTER_RW( 0x7e101080 )
3112 #define CM_GP2CTL_MASK 0x000000bf
3113 #define CM_GP2CTL_WIDTH 8
3114 #define CM_GP2CTL_RESET 0000000000
3115 #define CM_GP2CTL_BUSY_BITS 7:7
3116 #define CM_GP2CTL_BUSY_SET 0x00000080
3117 #define CM_GP2CTL_BUSY_CLR 0xffffff7f
3118 #define CM_GP2CTL_BUSY_MSB 7
3119 #define CM_GP2CTL_BUSY_LSB 7
3120 #define CM_GP2CTL_KILL_BITS 5:5
3121 #define CM_GP2CTL_KILL_SET 0x00000020
3122 #define CM_GP2CTL_KILL_CLR 0xffffffdf
3123 #define CM_GP2CTL_KILL_MSB 5
3124 #define CM_GP2CTL_KILL_LSB 5
3125 #define CM_GP2CTL_ENAB_BITS 4:4
3126 #define CM_GP2CTL_ENAB_SET 0x00000010
3127 #define CM_GP2CTL_ENAB_CLR 0xffffffef
3128 #define CM_GP2CTL_ENAB_MSB 4
3129 #define CM_GP2CTL_ENAB_LSB 4
3130 #define CM_GP2CTL_SRC_BITS 3:0
3131 #define CM_GP2CTL_SRC_SET 0x0000000f
3132 #define CM_GP2CTL_SRC_CLR 0xfffffff0
3133 #define CM_GP2CTL_SRC_MSB 3
3134 #define CM_GP2CTL_SRC_LSB 0
3135 #define CM_GP2DIV HW_REGISTER_RW( 0x7e101084 )
3136 #define CM_GP2DIV_MASK 0x00ffffff
3137 #define CM_GP2DIV_WIDTH 24
3138 #define CM_GP2DIV_RESET 0000000000
3139 #define CM_GP2DIV_DIV_BITS 23:0
3140 #define CM_GP2DIV_DIV_SET 0x00ffffff
3141 #define CM_GP2DIV_DIV_CLR 0xff000000
3142 #define CM_GP2DIV_DIV_MSB 23
3143 #define CM_GP2DIV_DIV_LSB 0
3144 #define CM_HSMCTL HW_REGISTER_RW( 0x7e101088 )
3145 #define CM_HSMCTL_MASK 0x000000ff
3146 #define CM_HSMCTL_WIDTH 8
3147 #define CM_HSMCTL_RESET 0000000000
3148 #define CM_HSMCTL_BUSY_BITS 7:7
3149 #define CM_HSMCTL_BUSY_SET 0x00000080
3150 #define CM_HSMCTL_BUSY_CLR 0xffffff7f
3151 #define CM_HSMCTL_BUSY_MSB 7
3152 #define CM_HSMCTL_BUSY_LSB 7
3153 #define CM_HSMCTL_GATE_BITS 6:6
3154 #define CM_HSMCTL_GATE_SET 0x00000040
3155 #define CM_HSMCTL_GATE_CLR 0xffffffbf
3156 #define CM_HSMCTL_GATE_MSB 6
3157 #define CM_HSMCTL_GATE_LSB 6
3158 #define CM_HSMCTL_KILL_BITS 5:5
3159 #define CM_HSMCTL_KILL_SET 0x00000020
3160 #define CM_HSMCTL_KILL_CLR 0xffffffdf
3161 #define CM_HSMCTL_KILL_MSB 5
3162 #define CM_HSMCTL_KILL_LSB 5
3163 #define CM_HSMCTL_ENAB_BITS 4:4
3164 #define CM_HSMCTL_ENAB_SET 0x00000010
3165 #define CM_HSMCTL_ENAB_CLR 0xffffffef
3166 #define CM_HSMCTL_ENAB_MSB 4
3167 #define CM_HSMCTL_ENAB_LSB 4
3168 #define CM_HSMCTL_SRC_BITS 3:0
3169 #define CM_HSMCTL_SRC_SET 0x0000000f
3170 #define CM_HSMCTL_SRC_CLR 0xfffffff0
3171 #define CM_HSMCTL_SRC_MSB 3
3172 #define CM_HSMCTL_SRC_LSB 0
3173 #define CM_HSMDIV HW_REGISTER_RW( 0x7e10108c )
3174 #define CM_HSMDIV_MASK 0x0000fff0
3175 #define CM_HSMDIV_WIDTH 16
3176 #define CM_HSMDIV_RESET 0000000000
3177 #define CM_HSMDIV_DIV_BITS 15:4