6b4981fb1351057a475e0ab44ee41d800a7587f0
[rpi-open-firmware.git] / bcm2708_chip / cpr_powman.h
1 // This file was generated by the create_regs script
2 #define PM_PASSWORD 0x5a000000
3 #define PM_BASE 0x7e100000
4 #define PM_APB_ID 0x0000706d
5 #define PM_GNRIC HW_REGISTER_RW( 0x7e100000 )
6 #define PM_GNRIC_MASK 0x007f1fff
7 #define PM_GNRIC_WIDTH 23
8 #define PM_GNRIC_RESET 0000000000
9 #define PM_GNRIC_CFG_BITS 22:16
10 #define PM_GNRIC_CFG_SET 0x007f0000
11 #define PM_GNRIC_CFG_CLR 0xff80ffff
12 #define PM_GNRIC_CFG_MSB 22
13 #define PM_GNRIC_CFG_LSB 16
14 #define PM_GNRIC_ENAB_BITS 12:12
15 #define PM_GNRIC_ENAB_SET 0x00001000
16 #define PM_GNRIC_ENAB_CLR 0xffffefff
17 #define PM_GNRIC_ENAB_MSB 12
18 #define PM_GNRIC_ENAB_LSB 12
19 #define PM_GNRIC_RSTN_BITS 11:6
20 #define PM_GNRIC_RSTN_SET 0x00000fc0
21 #define PM_GNRIC_RSTN_CLR 0xfffff03f
22 #define PM_GNRIC_RSTN_MSB 11
23 #define PM_GNRIC_RSTN_LSB 6
24 #define PM_GNRIC_ISFUNC_BITS 5:5
25 #define PM_GNRIC_ISFUNC_SET 0x00000020
26 #define PM_GNRIC_ISFUNC_CLR 0xffffffdf
27 #define PM_GNRIC_ISFUNC_MSB 5
28 #define PM_GNRIC_ISFUNC_LSB 5
29 #define PM_GNRIC_MRDONE_BITS 4:4
30 #define PM_GNRIC_MRDONE_SET 0x00000010
31 #define PM_GNRIC_MRDONE_CLR 0xffffffef
32 #define PM_GNRIC_MRDONE_MSB 4
33 #define PM_GNRIC_MRDONE_LSB 4
34 #define PM_GNRIC_MEMREP_BITS 3:3
35 #define PM_GNRIC_MEMREP_SET 0x00000008
36 #define PM_GNRIC_MEMREP_CLR 0xfffffff7
37 #define PM_GNRIC_MEMREP_MSB 3
38 #define PM_GNRIC_MEMREP_LSB 3
39 #define PM_GNRIC_ISPOW_BITS 2:2
40 #define PM_GNRIC_ISPOW_SET 0x00000004
41 #define PM_GNRIC_ISPOW_CLR 0xfffffffb
42 #define PM_GNRIC_ISPOW_MSB 2
43 #define PM_GNRIC_ISPOW_LSB 2
44 #define PM_GNRIC_POWOK_BITS 1:1
45 #define PM_GNRIC_POWOK_SET 0x00000002
46 #define PM_GNRIC_POWOK_CLR 0xfffffffd
47 #define PM_GNRIC_POWOK_MSB 1
48 #define PM_GNRIC_POWOK_LSB 1
49 #define PM_GNRIC_POWUP_BITS 0:0
50 #define PM_GNRIC_POWUP_SET 0x00000001
51 #define PM_GNRIC_POWUP_CLR 0xfffffffe
52 #define PM_GNRIC_POWUP_MSB 0
53 #define PM_GNRIC_POWUP_LSB 0
54 #define PM_AUDIO HW_REGISTER_RW( 0x7e100004 )
55 #define PM_AUDIO_MASK 0x003fffff
56 #define PM_AUDIO_WIDTH 22
57 #define PM_AUDIO_RESET 0x003000ff
58 #define PM_AUDIO_RSTN_BITS 21:21
59 #define PM_AUDIO_RSTN_SET 0x00200000
60 #define PM_AUDIO_RSTN_CLR 0xffdfffff
61 #define PM_AUDIO_RSTN_MSB 21
62 #define PM_AUDIO_RSTN_LSB 21
63 #define PM_AUDIO_CTRLEN_BITS 20:20
64 #define PM_AUDIO_CTRLEN_SET 0x00100000
65 #define PM_AUDIO_CTRLEN_CLR 0xffefffff
66 #define PM_AUDIO_CTRLEN_MSB 20
67 #define PM_AUDIO_CTRLEN_LSB 20
68 #define PM_AUDIO_APSM_BITS 19:0
69 #define PM_AUDIO_APSM_SET 0x000fffff
70 #define PM_AUDIO_APSM_CLR 0xfff00000
71 #define PM_AUDIO_APSM_MSB 19
72 #define PM_AUDIO_APSM_LSB 0
73 #define PM_STATUS HW_REGISTER_RO( 0x7e100018 )
74 #define PM_STATUS_MASK 0x00ffffff
75 #define PM_STATUS_WIDTH 24
76 #define PM_STATUS_RESET 0000000000
77 #define PM_IMAGE HW_REGISTER_RW( 0x7e100108 )
78 #define PM_IMAGE_MASK 0x007f11ff
79 #define PM_IMAGE_WIDTH 23
80 #define PM_IMAGE_RESET 0x00001000
81 #define PM_IMAGE_CFG_BITS 22:16
82 #define PM_IMAGE_CFG_SET 0x007f0000
83 #define PM_IMAGE_CFG_CLR 0xff80ffff
84 #define PM_IMAGE_CFG_MSB 22
85 #define PM_IMAGE_CFG_LSB 16
86 #define PM_IMAGE_ENAB_BITS 12:12
87 #define PM_IMAGE_ENAB_SET 0x00001000
88 #define PM_IMAGE_ENAB_CLR 0xffffefff
89 #define PM_IMAGE_ENAB_MSB 12
90 #define PM_IMAGE_ENAB_LSB 12
91 #define PM_IMAGE_ISPRSTN_BITS 8:8
92 #define PM_IMAGE_ISPRSTN_SET 0x00000100
93 #define PM_IMAGE_ISPRSTN_CLR 0xfffffeff
94 #define PM_IMAGE_ISPRSTN_MSB 8
95 #define PM_IMAGE_ISPRSTN_LSB 8
96 #define PM_IMAGE_H264RSTN_BITS 7:7
97 #define PM_IMAGE_H264RSTN_SET 0x00000080
98 #define PM_IMAGE_H264RSTN_CLR 0xffffff7f
99 #define PM_IMAGE_H264RSTN_MSB 7
100 #define PM_IMAGE_H264RSTN_LSB 7
101 #define PM_IMAGE_PERIRSTN_BITS 6:6
102 #define PM_IMAGE_PERIRSTN_SET 0x00000040
103 #define PM_IMAGE_PERIRSTN_CLR 0xffffffbf
104 #define PM_IMAGE_PERIRSTN_MSB 6
105 #define PM_IMAGE_PERIRSTN_LSB 6
106 #define PM_IMAGE_ISFUNC_BITS 5:5
107 #define PM_IMAGE_ISFUNC_SET 0x00000020
108 #define PM_IMAGE_ISFUNC_CLR 0xffffffdf
109 #define PM_IMAGE_ISFUNC_MSB 5
110 #define PM_IMAGE_ISFUNC_LSB 5
111 #define PM_IMAGE_MRDONE_BITS 4:4
112 #define PM_IMAGE_MRDONE_SET 0x00000010
113 #define PM_IMAGE_MRDONE_CLR 0xffffffef
114 #define PM_IMAGE_MRDONE_MSB 4
115 #define PM_IMAGE_MRDONE_LSB 4
116 #define PM_IMAGE_MEMREP_BITS 3:3
117 #define PM_IMAGE_MEMREP_SET 0x00000008
118 #define PM_IMAGE_MEMREP_CLR 0xfffffff7
119 #define PM_IMAGE_MEMREP_MSB 3
120 #define PM_IMAGE_MEMREP_LSB 3
121 #define PM_IMAGE_ISPOW_BITS 2:2
122 #define PM_IMAGE_ISPOW_SET 0x00000004
123 #define PM_IMAGE_ISPOW_CLR 0xfffffffb
124 #define PM_IMAGE_ISPOW_MSB 2
125 #define PM_IMAGE_ISPOW_LSB 2
126 #define PM_IMAGE_POWOK_BITS 1:1
127 #define PM_IMAGE_POWOK_SET 0x00000002
128 #define PM_IMAGE_POWOK_CLR 0xfffffffd
129 #define PM_IMAGE_POWOK_MSB 1
130 #define PM_IMAGE_POWOK_LSB 1
131 #define PM_IMAGE_POWUP_BITS 0:0
132 #define PM_IMAGE_POWUP_SET 0x00000001
133 #define PM_IMAGE_POWUP_CLR 0xfffffffe
134 #define PM_IMAGE_POWUP_MSB 0
135 #define PM_IMAGE_POWUP_LSB 0
136 #define PM_GRAFX HW_REGISTER_RW( 0x7e10010c )
137 #define PM_GRAFX_MASK 0x007f107f
138 #define PM_GRAFX_WIDTH 23
139 #define PM_GRAFX_RESET 0x00001000
140 #define PM_GRAFX_CFG_BITS 22:16
141 #define PM_GRAFX_CFG_SET 0x007f0000
142 #define PM_GRAFX_CFG_CLR 0xff80ffff
143 #define PM_GRAFX_CFG_MSB 22
144 #define PM_GRAFX_CFG_LSB 16
145 #define PM_GRAFX_ENAB_BITS 12:12
146 #define PM_GRAFX_ENAB_SET 0x00001000
147 #define PM_GRAFX_ENAB_CLR 0xffffefff
148 #define PM_GRAFX_ENAB_MSB 12
149 #define PM_GRAFX_ENAB_LSB 12
150 #define PM_GRAFX_V3DRSTN_BITS 6:6
151 #define PM_GRAFX_V3DRSTN_SET 0x00000040
152 #define PM_GRAFX_V3DRSTN_CLR 0xffffffbf
153 #define PM_GRAFX_V3DRSTN_MSB 6
154 #define PM_GRAFX_V3DRSTN_LSB 6
155 #define PM_GRAFX_ISFUNC_BITS 5:5
156 #define PM_GRAFX_ISFUNC_SET 0x00000020
157 #define PM_GRAFX_ISFUNC_CLR 0xffffffdf
158 #define PM_GRAFX_ISFUNC_MSB 5
159 #define PM_GRAFX_ISFUNC_LSB 5
160 #define PM_GRAFX_MRDONE_BITS 4:4
161 #define PM_GRAFX_MRDONE_SET 0x00000010
162 #define PM_GRAFX_MRDONE_CLR 0xffffffef
163 #define PM_GRAFX_MRDONE_MSB 4
164 #define PM_GRAFX_MRDONE_LSB 4
165 #define PM_GRAFX_MEMREP_BITS 3:3
166 #define PM_GRAFX_MEMREP_SET 0x00000008
167 #define PM_GRAFX_MEMREP_CLR 0xfffffff7
168 #define PM_GRAFX_MEMREP_MSB 3
169 #define PM_GRAFX_MEMREP_LSB 3
170 #define PM_GRAFX_ISPOW_BITS 2:2
171 #define PM_GRAFX_ISPOW_SET 0x00000004
172 #define PM_GRAFX_ISPOW_CLR 0xfffffffb
173 #define PM_GRAFX_ISPOW_MSB 2
174 #define PM_GRAFX_ISPOW_LSB 2
175 #define PM_GRAFX_POWOK_BITS 1:1
176 #define PM_GRAFX_POWOK_SET 0x00000002
177 #define PM_GRAFX_POWOK_CLR 0xfffffffd
178 #define PM_GRAFX_POWOK_MSB 1
179 #define PM_GRAFX_POWOK_LSB 1
180 #define PM_GRAFX_POWUP_BITS 0:0
181 #define PM_GRAFX_POWUP_SET 0x00000001
182 #define PM_GRAFX_POWUP_CLR 0xfffffffe
183 #define PM_GRAFX_POWUP_MSB 0
184 #define PM_GRAFX_POWUP_LSB 0
185 #define PM_PROC HW_REGISTER_RW( 0x7e100110 )
186 #define PM_PROC_MASK 0x007f107f
187 #define PM_PROC_WIDTH 23
188 #define PM_PROC_RESET 0000000000
189 #define PM_PROC_CFG_BITS 22:16
190 #define PM_PROC_CFG_SET 0x007f0000
191 #define PM_PROC_CFG_CLR 0xff80ffff
192 #define PM_PROC_CFG_MSB 22
193 #define PM_PROC_CFG_LSB 16
194 #define PM_PROC_ENAB_BITS 12:12
195 #define PM_PROC_ENAB_SET 0x00001000
196 #define PM_PROC_ENAB_CLR 0xffffefff
197 #define PM_PROC_ENAB_MSB 12
198 #define PM_PROC_ENAB_LSB 12
199 #define PM_PROC_ARMRSTN_BITS 6:6
200 #define PM_PROC_ARMRSTN_SET 0x00000040
201 #define PM_PROC_ARMRSTN_CLR 0xffffffbf
202 #define PM_PROC_ARMRSTN_MSB 6
203 #define PM_PROC_ARMRSTN_LSB 6
204 #define PM_PROC_ISFUNC_BITS 5:5
205 #define PM_PROC_ISFUNC_SET 0x00000020
206 #define PM_PROC_ISFUNC_CLR 0xffffffdf
207 #define PM_PROC_ISFUNC_MSB 5
208 #define PM_PROC_ISFUNC_LSB 5
209 #define PM_PROC_MRDONE_BITS 4:4
210 #define PM_PROC_MRDONE_SET 0x00000010
211 #define PM_PROC_MRDONE_CLR 0xffffffef
212 #define PM_PROC_MRDONE_MSB 4
213 #define PM_PROC_MRDONE_LSB 4
214 #define PM_PROC_MEMREP_BITS 3:3
215 #define PM_PROC_MEMREP_SET 0x00000008
216 #define PM_PROC_MEMREP_CLR 0xfffffff7
217 #define PM_PROC_MEMREP_MSB 3
218 #define PM_PROC_MEMREP_LSB 3
219 #define PM_PROC_ISPOW_BITS 2:2
220 #define PM_PROC_ISPOW_SET 0x00000004
221 #define PM_PROC_ISPOW_CLR 0xfffffffb
222 #define PM_PROC_ISPOW_MSB 2
223 #define PM_PROC_ISPOW_LSB 2
224 #define PM_PROC_POWOK_BITS 1:1
225 #define PM_PROC_POWOK_SET 0x00000002
226 #define PM_PROC_POWOK_CLR 0xfffffffd
227 #define PM_PROC_POWOK_MSB 1
228 #define PM_PROC_POWOK_LSB 1
229 #define PM_PROC_POWUP_BITS 0:0
230 #define PM_PROC_POWUP_SET 0x00000001
231 #define PM_PROC_POWUP_CLR 0xfffffffe
232 #define PM_PROC_POWUP_MSB 0
233 #define PM_PROC_POWUP_LSB 0
234 #define PM_RSTC HW_REGISTER_RW( 0x7e10001c )
235 #define PM_RSTC_MASK 0x00333333
236 #define PM_RSTC_WIDTH 22
237 #define PM_RSTC_RESET 0x00000102
238 #define PM_RSTC_HRCFG_BITS 21:20
239 #define PM_RSTC_HRCFG_SET 0x00300000
240 #define PM_RSTC_HRCFG_CLR 0xffcfffff
241 #define PM_RSTC_HRCFG_MSB 21
242 #define PM_RSTC_HRCFG_LSB 20
243 #define PM_RSTC_FRCFG_BITS 17:16
244 #define PM_RSTC_FRCFG_SET 0x00030000
245 #define PM_RSTC_FRCFG_CLR 0xfffcffff
246 #define PM_RSTC_FRCFG_MSB 17
247 #define PM_RSTC_FRCFG_LSB 16
248 #define PM_RSTC_QRCFG_BITS 13:12
249 #define PM_RSTC_QRCFG_SET 0x00003000
250 #define PM_RSTC_QRCFG_CLR 0xffffcfff
251 #define PM_RSTC_QRCFG_MSB 13
252 #define PM_RSTC_QRCFG_LSB 12
253 #define PM_RSTC_SRCFG_BITS 9:8
254 #define PM_RSTC_SRCFG_SET 0x00000300
255 #define PM_RSTC_SRCFG_CLR 0xfffffcff
256 #define PM_RSTC_SRCFG_MSB 9
257 #define PM_RSTC_SRCFG_LSB 8
258 #define PM_RSTC_WRCFG_BITS 5:4
259 #define PM_RSTC_WRCFG_SET 0x00000030
260 #define PM_RSTC_WRCFG_CLR 0xffffffcf
261 #define PM_RSTC_WRCFG_MSB 5
262 #define PM_RSTC_WRCFG_LSB 4
263 #define PM_RSTC_DRCFG_BITS 1:0
264 #define PM_RSTC_DRCFG_SET 0x00000003
265 #define PM_RSTC_DRCFG_CLR 0xfffffffc
266 #define PM_RSTC_DRCFG_MSB 1
267 #define PM_RSTC_DRCFG_LSB 0
268 #define PM_RSTS HW_REGISTER_RW( 0x7e100020 )
269 #define PM_RSTS_MASK 0x00001777
270 #define PM_RSTS_WIDTH 13
271 #define PM_RSTS_RESET 0x00001000
272 #define PM_RSTS_HADPOR_BITS 12:12
273 #define PM_RSTS_HADPOR_SET 0x00001000
274 #define PM_RSTS_HADPOR_CLR 0xffffefff
275 #define PM_RSTS_HADPOR_MSB 12
276 #define PM_RSTS_HADPOR_LSB 12
277 #define PM_RSTS_HADSRH_BITS 10:10
278 #define PM_RSTS_HADSRH_SET 0x00000400
279 #define PM_RSTS_HADSRH_CLR 0xfffffbff
280 #define PM_RSTS_HADSRH_MSB 10
281 #define PM_RSTS_HADSRH_LSB 10
282 #define PM_RSTS_HADSRF_BITS 9:9
283 #define PM_RSTS_HADSRF_SET 0x00000200
284 #define PM_RSTS_HADSRF_CLR 0xfffffdff
285 #define PM_RSTS_HADSRF_MSB 9
286 #define PM_RSTS_HADSRF_LSB 9
287 #define PM_RSTS_HADSRQ_BITS 8:8
288 #define PM_RSTS_HADSRQ_SET 0x00000100
289 #define PM_RSTS_HADSRQ_CLR 0xfffffeff
290 #define PM_RSTS_HADSRQ_MSB 8
291 #define PM_RSTS_HADSRQ_LSB 8
292 #define PM_RSTS_HADWRH_BITS 6:6
293 #define PM_RSTS_HADWRH_SET 0x00000040
294 #define PM_RSTS_HADWRH_CLR 0xffffffbf
295 #define PM_RSTS_HADWRH_MSB 6
296 #define PM_RSTS_HADWRH_LSB 6
297 #define PM_RSTS_HADWRF_BITS 5:5
298 #define PM_RSTS_HADWRF_SET 0x00000020
299 #define PM_RSTS_HADWRF_CLR 0xffffffdf
300 #define PM_RSTS_HADWRF_MSB 5
301 #define PM_RSTS_HADWRF_LSB 5
302 #define PM_RSTS_HADWRQ_BITS 4:4
303 #define PM_RSTS_HADWRQ_SET 0x00000010
304 #define PM_RSTS_HADWRQ_CLR 0xffffffef
305 #define PM_RSTS_HADWRQ_MSB 4
306 #define PM_RSTS_HADWRQ_LSB 4
307 #define PM_RSTS_HADDRH_BITS 2:2
308 #define PM_RSTS_HADDRH_SET 0x00000004
309 #define PM_RSTS_HADDRH_CLR 0xfffffffb
310 #define PM_RSTS_HADDRH_MSB 2
311 #define PM_RSTS_HADDRH_LSB 2
312 #define PM_RSTS_HADDRF_BITS 1:1
313 #define PM_RSTS_HADDRF_SET 0x00000002
314 #define PM_RSTS_HADDRF_CLR 0xfffffffd
315 #define PM_RSTS_HADDRF_MSB 1
316 #define PM_RSTS_HADDRF_LSB 1
317 #define PM_RSTS_HADDRQ_BITS 0:0
318 #define PM_RSTS_HADDRQ_SET 0x00000001
319 #define PM_RSTS_HADDRQ_CLR 0xfffffffe
320 #define PM_RSTS_HADDRQ_MSB 0
321 #define PM_RSTS_HADDRQ_LSB 0
322 #define PM_WDOG HW_REGISTER_RW( 0x7e100024 )
323 #define PM_WDOG_MASK 0x000fffff
324 #define PM_WDOG_WIDTH 20
325 #define PM_WDOG_RESET 0000000000
326 #define PM_WDOG_TIME_BITS 19:0
327 #define PM_WDOG_TIME_SET 0x000fffff
328 #define PM_WDOG_TIME_CLR 0xfff00000
329 #define PM_WDOG_TIME_MSB 19
330 #define PM_WDOG_TIME_LSB 0
331 #define PM_PADS0 HW_REGISTER_RW( 0x7e100028 )
332 #define PM_PADS0_MASK 0x0000003f
333 #define PM_PADS0_WIDTH 6
334 #define PM_PADS0_RESET 0x0000001b
335 #define PM_PADS0_DRIVE_BITS 2:0
336 #define PM_PADS0_DRIVE_SET 0x00000007
337 #define PM_PADS0_DRIVE_CLR 0xfffffff8
338 #define PM_PADS0_DRIVE_MSB 2
339 #define PM_PADS0_DRIVE_LSB 0
340 #define PM_PADS0_HYST_BITS 3:3
341 #define PM_PADS0_HYST_SET 0x00000008
342 #define PM_PADS0_HYST_CLR 0xfffffff7
343 #define PM_PADS0_HYST_MSB 3
344 #define PM_PADS0_HYST_LSB 3
345 #define PM_PADS0_SLEW_BITS 4:4
346 #define PM_PADS0_SLEW_SET 0x00000010
347 #define PM_PADS0_SLEW_CLR 0xffffffef
348 #define PM_PADS0_SLEW_MSB 4
349 #define PM_PADS0_SLEW_LSB 4
350 #define PM_PADS0_POWOK_BITS 5:5
351 #define PM_PADS0_POWOK_SET 0x00000020
352 #define PM_PADS0_POWOK_CLR 0xffffffdf
353 #define PM_PADS0_POWOK_MSB 5
354 #define PM_PADS0_POWOK_LSB 5
355 #define PM_PADS2 HW_REGISTER_RW( 0x7e10002c )
356 #define PM_PADS2_MASK 0x0000003f
357 #define PM_PADS2_WIDTH 6
358 #define PM_PADS2_RESET 0x0000001b
359 #define PM_PADS2_DRIVE_BITS 2:0
360 #define PM_PADS2_DRIVE_SET 0x00000007
361 #define PM_PADS2_DRIVE_CLR 0xfffffff8
362 #define PM_PADS2_DRIVE_MSB 2
363 #define PM_PADS2_DRIVE_LSB 0
364 #define PM_PADS2_HYST_BITS 3:3
365 #define PM_PADS2_HYST_SET 0x00000008
366 #define PM_PADS2_HYST_CLR 0xfffffff7
367 #define PM_PADS2_HYST_MSB 3
368 #define PM_PADS2_HYST_LSB 3
369 #define PM_PADS2_SLEW_BITS 4:4
370 #define PM_PADS2_SLEW_SET 0x00000010
371 #define PM_PADS2_SLEW_CLR 0xffffffef
372 #define PM_PADS2_SLEW_MSB 4
373 #define PM_PADS2_SLEW_LSB 4
374 #define PM_PADS2_POWOK_BITS 5:5
375 #define PM_PADS2_POWOK_SET 0x00000020
376 #define PM_PADS2_POWOK_CLR 0xffffffdf
377 #define PM_PADS2_POWOK_MSB 5
378 #define PM_PADS2_POWOK_LSB 5
379 #define PM_PADS3 HW_REGISTER_RW( 0x7e100030 )
380 #define PM_PADS3_MASK 0x0000003f
381 #define PM_PADS3_WIDTH 6
382 #define PM_PADS3_RESET 0x0000001b
383 #define PM_PADS3_DRIVE_BITS 2:0
384 #define PM_PADS3_DRIVE_SET 0x00000007
385 #define PM_PADS3_DRIVE_CLR 0xfffffff8
386 #define PM_PADS3_DRIVE_MSB 2
387 #define PM_PADS3_DRIVE_LSB 0
388 #define PM_PADS3_HYST_BITS 3:3
389 #define PM_PADS3_HYST_SET 0x00000008
390 #define PM_PADS3_HYST_CLR 0xfffffff7
391 #define PM_PADS3_HYST_MSB 3
392 #define PM_PADS3_HYST_LSB 3
393 #define PM_PADS3_SLEW_BITS 4:4
394 #define PM_PADS3_SLEW_SET 0x00000010
395 #define PM_PADS3_SLEW_CLR 0xffffffef
396 #define PM_PADS3_SLEW_MSB 4
397 #define PM_PADS3_SLEW_LSB 4
398 #define PM_PADS3_POWOK_BITS 5:5
399 #define PM_PADS3_POWOK_SET 0x00000020
400 #define PM_PADS3_POWOK_CLR 0xffffffdf
401 #define PM_PADS3_POWOK_MSB 5
402 #define PM_PADS3_POWOK_LSB 5
403 #define PM_PADS4 HW_REGISTER_RW( 0x7e100034 )
404 #define PM_PADS4_MASK 0x0000003f
405 #define PM_PADS4_WIDTH 6
406 #define PM_PADS4_RESET 0x0000001b
407 #define PM_PADS4_DRIVE_BITS 2:0
408 #define PM_PADS4_DRIVE_SET 0x00000007
409 #define PM_PADS4_DRIVE_CLR 0xfffffff8
410 #define PM_PADS4_DRIVE_MSB 2
411 #define PM_PADS4_DRIVE_LSB 0
412 #define PM_PADS4_HYST_BITS 3:3
413 #define PM_PADS4_HYST_SET 0x00000008
414 #define PM_PADS4_HYST_CLR 0xfffffff7
415 #define PM_PADS4_HYST_MSB 3
416 #define PM_PADS4_HYST_LSB 3
417 #define PM_PADS4_SPARE_BITS 4:4
418 #define PM_PADS4_SPARE_SET 0x00000010
419 #define PM_PADS4_SPARE_CLR 0xffffffef
420 #define PM_PADS4_SPARE_MSB 4
421 #define PM_PADS4_SPARE_LSB 4
422 #define PM_PADS4_POWOK_BITS 5:5
423 #define PM_PADS4_POWOK_SET 0x00000020
424 #define PM_PADS4_POWOK_CLR 0xffffffdf
425 #define PM_PADS4_POWOK_MSB 5
426 #define PM_PADS4_POWOK_LSB 5
427 #define PM_PADS5 HW_REGISTER_RW( 0x7e100038 )
428 #define PM_PADS5_MASK 0x0000007f
429 #define PM_PADS5_WIDTH 7
430 #define PM_PADS5_RESET 0x0000001b
431 #define PM_PADS5_DRIVE_BITS 2:0
432 #define PM_PADS5_DRIVE_SET 0x00000007
433 #define PM_PADS5_DRIVE_CLR 0xfffffff8
434 #define PM_PADS5_DRIVE_MSB 2
435 #define PM_PADS5_DRIVE_LSB 0
436 #define PM_PADS5_HYST_BITS 3:3
437 #define PM_PADS5_HYST_SET 0x00000008
438 #define PM_PADS5_HYST_CLR 0xfffffff7
439 #define PM_PADS5_HYST_MSB 3
440 #define PM_PADS5_HYST_LSB 3
441 #define PM_PADS5_SLEW_BITS 4:4
442 #define PM_PADS5_SLEW_SET 0x00000010
443 #define PM_PADS5_SLEW_CLR 0xffffffef
444 #define PM_PADS5_SLEW_MSB 4
445 #define PM_PADS5_SLEW_LSB 4
446 #define PM_PADS5_POWOK_BITS 5:5
447 #define PM_PADS5_POWOK_SET 0x00000020
448 #define PM_PADS5_POWOK_CLR 0xffffffdf
449 #define PM_PADS5_POWOK_MSB 5
450 #define PM_PADS5_POWOK_LSB 5
451 #define PM_PADS5_I2CMODE_BITS 6:6
452 #define PM_PADS5_I2CMODE_SET 0x00000040
453 #define PM_PADS5_I2CMODE_CLR 0xffffffbf
454 #define PM_PADS5_I2CMODE_MSB 6
455 #define PM_PADS5_I2CMODE_LSB 6
456 #define PM_PADS6 HW_REGISTER_RW( 0x7e10003c )
457 #define PM_PADS6_MASK 0x00000123
458 #define PM_PADS6_WIDTH 9
459 #define PM_PADS6_RESET 0000000000
460 #define PM_PADS6_DRIVE_BITS 1:0
461 #define PM_PADS6_DRIVE_SET 0x00000003
462 #define PM_PADS6_DRIVE_CLR 0xfffffffc
463 #define PM_PADS6_DRIVE_MSB 1
464 #define PM_PADS6_DRIVE_LSB 0
465 #define PM_PADS6_POWOK_BITS 5:5
466 #define PM_PADS6_POWOK_SET 0x00000020
467 #define PM_PADS6_POWOK_CLR 0xffffffdf
468 #define PM_PADS6_POWOK_MSB 5
469 #define PM_PADS6_POWOK_LSB 5
470 #define PM_PADS6_PD_BITS 8:8
471 #define PM_PADS6_PD_SET 0x00000100
472 #define PM_PADS6_PD_CLR 0xfffffeff
473 #define PM_PADS6_PD_MSB 8
474 #define PM_PADS6_PD_LSB 8
475 #define PM_CAM0 HW_REGISTER_RW( 0x7e100044 )
476 #define PM_CAM0_MASK 0x001fffff
477 #define PM_CAM0_WIDTH 21
478 #define PM_CAM0_RESET 0000000000
479 #define PM_CAM0_CTRLEN_BITS 0:0
480 #define PM_CAM0_CTRLEN_SET 0x00000001
481 #define PM_CAM0_CTRLEN_CLR 0xfffffffe
482 #define PM_CAM0_CTRLEN_MSB 0
483 #define PM_CAM0_CTRLEN_LSB 0
484 #define PM_CAM0_LDOLPEN_BITS 1:1
485 #define PM_CAM0_LDOLPEN_SET 0x00000002
486 #define PM_CAM0_LDOLPEN_CLR 0xfffffffd
487 #define PM_CAM0_LDOLPEN_MSB 1
488 #define PM_CAM0_LDOLPEN_LSB 1
489 #define PM_CAM0_LDOHPEN_BITS 2:2
490 #define PM_CAM0_LDOHPEN_SET 0x00000004
491 #define PM_CAM0_LDOHPEN_CLR 0xfffffffb
492 #define PM_CAM0_LDOHPEN_MSB 2
493 #define PM_CAM0_LDOHPEN_LSB 2
494 #define PM_CAM0_LDOCTRL_BITS 20:3
495 #define PM_CAM0_LDOCTRL_SET 0x001ffff8
496 #define PM_CAM0_LDOCTRL_CLR 0xffe00007
497 #define PM_CAM0_LDOCTRL_MSB 20
498 #define PM_CAM0_LDOCTRL_LSB 3
499 #define PM_CAM1 HW_REGISTER_RW( 0x7e100048 )
500 #define PM_CAM1_MASK 0x001fffff
501 #define PM_CAM1_WIDTH 21
502 #define PM_CAM1_RESET 0000000000
503 #define PM_CAM1_CTRLEN_BITS 0:0
504 #define PM_CAM1_CTRLEN_SET 0x00000001
505 #define PM_CAM1_CTRLEN_CLR 0xfffffffe
506 #define PM_CAM1_CTRLEN_MSB 0
507 #define PM_CAM1_CTRLEN_LSB 0
508 #define PM_CAM1_LDOLPEN_BITS 1:1
509 #define PM_CAM1_LDOLPEN_SET 0x00000002
510 #define PM_CAM1_LDOLPEN_CLR 0xfffffffd
511 #define PM_CAM1_LDOLPEN_MSB 1
512 #define PM_CAM1_LDOLPEN_LSB 1
513 #define PM_CAM1_LDOHPEN_BITS 2:2
514 #define PM_CAM1_LDOHPEN_SET 0x00000004
515 #define PM_CAM1_LDOHPEN_CLR 0xfffffffb
516 #define PM_CAM1_LDOHPEN_MSB 2
517 #define PM_CAM1_LDOHPEN_LSB 2
518 #define PM_CAM1_LDOCTRL_BITS 20:3
519 #define PM_CAM1_LDOCTRL_SET 0x001ffff8
520 #define PM_CAM1_LDOCTRL_CLR 0xffe00007
521 #define PM_CAM1_LDOCTRL_MSB 20
522 #define PM_CAM1_LDOCTRL_LSB 3
523 #define PM_CCP2TX HW_REGISTER_RW( 0x7e10004c )
524 #define PM_CCP2TX_MASK 0x0007ffff
525 #define PM_CCP2TX_WIDTH 19
526 #define PM_CCP2TX_RESET 0000000000
527 #define PM_CCP2TX_CTRLEN_BITS 0:0
528 #define PM_CCP2TX_CTRLEN_SET 0x00000001
529 #define PM_CCP2TX_CTRLEN_CLR 0xfffffffe
530 #define PM_CCP2TX_CTRLEN_MSB 0
531 #define PM_CCP2TX_CTRLEN_LSB 0
532 #define PM_CCP2TX_LDOEN_BITS 1:1
533 #define PM_CCP2TX_LDOEN_SET 0x00000002
534 #define PM_CCP2TX_LDOEN_CLR 0xfffffffd
535 #define PM_CCP2TX_LDOEN_MSB 1
536 #define PM_CCP2TX_LDOEN_LSB 1
537 #define PM_CCP2TX_LDOCTRL_BITS 18:2
538 #define PM_CCP2TX_LDOCTRL_SET 0x0007fffc
539 #define PM_CCP2TX_LDOCTRL_CLR 0xfff80003
540 #define PM_CCP2TX_LDOCTRL_MSB 18
541 #define PM_CCP2TX_LDOCTRL_LSB 2
542 #define PM_DSI0 HW_REGISTER_RW( 0x7e100050 )
543 #define PM_DSI0_MASK 0x001fffff
544 #define PM_DSI0_WIDTH 21
545 #define PM_DSI0_RESET 0000000000
546 #define PM_DSI0_CTRLEN_BITS 0:0
547 #define PM_DSI0_CTRLEN_SET 0x00000001
548 #define PM_DSI0_CTRLEN_CLR 0xfffffffe
549 #define PM_DSI0_CTRLEN_MSB 0
550 #define PM_DSI0_CTRLEN_LSB 0
551 #define PM_DSI0_LDOLPEN_BITS 1:1
552 #define PM_DSI0_LDOLPEN_SET 0x00000002
553 #define PM_DSI0_LDOLPEN_CLR 0xfffffffd
554 #define PM_DSI0_LDOLPEN_MSB 1
555 #define PM_DSI0_LDOLPEN_LSB 1
556 #define PM_DSI0_LDOHPEN_BITS 2:2
557 #define PM_DSI0_LDOHPEN_SET 0x00000004
558 #define PM_DSI0_LDOHPEN_CLR 0xfffffffb
559 #define PM_DSI0_LDOHPEN_MSB 2
560 #define PM_DSI0_LDOHPEN_LSB 2
561 #define PM_DSI0_LDOCTRL_BITS 20:3
562 #define PM_DSI0_LDOCTRL_SET 0x001ffff8
563 #define PM_DSI0_LDOCTRL_CLR 0xffe00007
564 #define PM_DSI0_LDOCTRL_MSB 20
565 #define PM_DSI0_LDOCTRL_LSB 3
566 #define PM_DSI1 HW_REGISTER_RW( 0x7e100054 )
567 #define PM_DSI1_MASK 0x001fffff
568 #define PM_DSI1_WIDTH 21
569 #define PM_DSI1_RESET 0000000000
570 #define PM_DSI1_CTRLEN_BITS 0:0
571 #define PM_DSI1_CTRLEN_SET 0x00000001
572 #define PM_DSI1_CTRLEN_CLR 0xfffffffe
573 #define PM_DSI1_CTRLEN_MSB 0
574 #define PM_DSI1_CTRLEN_LSB 0
575 #define PM_DSI1_LDOLPEN_BITS 1:1
576 #define PM_DSI1_LDOLPEN_SET 0x00000002
577 #define PM_DSI1_LDOLPEN_CLR 0xfffffffd
578 #define PM_DSI1_LDOLPEN_MSB 1
579 #define PM_DSI1_LDOLPEN_LSB 1
580 #define PM_DSI1_LDOHPEN_BITS 2:2
581 #define PM_DSI1_LDOHPEN_SET 0x00000004
582 #define PM_DSI1_LDOHPEN_CLR 0xfffffffb
583 #define PM_DSI1_LDOHPEN_MSB 2
584 #define PM_DSI1_LDOHPEN_LSB 2
585 #define PM_DSI1_LDOCTRL_BITS 20:3
586 #define PM_DSI1_LDOCTRL_SET 0x001ffff8
587 #define PM_DSI1_LDOCTRL_CLR 0xffe00007
588 #define PM_DSI1_LDOCTRL_MSB 20
589 #define PM_DSI1_LDOCTRL_LSB 3
590 #define PM_HDMI HW_REGISTER_RW( 0x7e100058 )
591 #define PM_HDMI_MASK 0x000fffff
592 #define PM_HDMI_WIDTH 20
593 #define PM_HDMI_RESET 0x00080002
594 #define PM_HDMI_CTRLEN_BITS 0:0
595 #define PM_HDMI_CTRLEN_SET 0x00000001
596 #define PM_HDMI_CTRLEN_CLR 0xfffffffe
597 #define PM_HDMI_CTRLEN_MSB 0
598 #define PM_HDMI_CTRLEN_LSB 0
599 #define PM_HDMI_LDOPD_BITS 1:1
600 #define PM_HDMI_LDOPD_SET 0x00000002
601 #define PM_HDMI_LDOPD_CLR 0xfffffffd
602 #define PM_HDMI_LDOPD_MSB 1
603 #define PM_HDMI_LDOPD_LSB 1
604 #define PM_HDMI_LDOCTRL_BITS 18:2
605 #define PM_HDMI_LDOCTRL_SET 0x0007fffc
606 #define PM_HDMI_LDOCTRL_CLR 0xfff80003
607 #define PM_HDMI_LDOCTRL_MSB 18
608 #define PM_HDMI_LDOCTRL_LSB 2
609 #define PM_HDMI_RSTDR_BITS 19:19
610 #define PM_HDMI_RSTDR_SET 0x00080000
611 #define PM_HDMI_RSTDR_CLR 0xfff7ffff
612 #define PM_HDMI_RSTDR_MSB 19
613 #define PM_HDMI_RSTDR_LSB 19
614 #define PM_USB HW_REGISTER_RW( 0x7e10005c )
615 #define PM_USB_MASK 0x00000001
616 #define PM_USB_WIDTH 1
617 #define PM_USB_RESET 0000000000
618 #define PM_USB_CTRLEN_BITS 0:0
619 #define PM_USB_CTRLEN_SET 0x00000001
620 #define PM_USB_CTRLEN_CLR 0xfffffffe
621 #define PM_USB_CTRLEN_MSB 0
622 #define PM_USB_CTRLEN_LSB 0
623 #define PM_PXLDO HW_REGISTER_RW( 0x7e100060 )
624 #define PM_PXLDO_MASK 0x0003ffff
625 #define PM_PXLDO_WIDTH 18
626 #define PM_PXLDO_RESET 0000000000
627 #define PM_PXLDO_CTRL_BITS 15:0
628 #define PM_PXLDO_CTRL_SET 0x0000ffff
629 #define PM_PXLDO_CTRL_CLR 0xffff0000
630 #define PM_PXLDO_CTRL_MSB 15
631 #define PM_PXLDO_CTRL_LSB 0
632 #define PM_PXLDO_RSTOSCDR_BITS 16:16
633 #define PM_PXLDO_RSTOSCDR_SET 0x00010000
634 #define PM_PXLDO_RSTOSCDR_CLR 0xfffeffff
635 #define PM_PXLDO_RSTOSCDR_MSB 16
636 #define PM_PXLDO_RSTOSCDR_LSB 16
637 #define PM_PXLDO_RSTPLLDR_BITS 17:17
638 #define PM_PXLDO_RSTPLLDR_SET 0x00020000
639 #define PM_PXLDO_RSTPLLDR_CLR 0xfffdffff
640 #define PM_PXLDO_RSTPLLDR_MSB 17
641 #define PM_PXLDO_RSTPLLDR_LSB 17
642 #define PM_PXBG HW_REGISTER_RW( 0x7e100064 )
643 #define PM_PXBG_MASK 0x0000ffff
644 #define PM_PXBG_WIDTH 16
645 #define PM_PXBG_RESET 0000000000
646 #define PM_PXBG_CTRL_BITS 15:0
647 #define PM_PXBG_CTRL_SET 0x0000ffff
648 #define PM_PXBG_CTRL_CLR 0xffff0000
649 #define PM_PXBG_CTRL_MSB 15
650 #define PM_PXBG_CTRL_LSB 0
651 #define PM_DFT HW_REGISTER_RW( 0x7e100068 )
652 #define PM_DFT_MASK 0x00000003
653 #define PM_DFT_WIDTH 2
654 #define PM_DFT_RESET 0000000000
655 #define PM_DFT_ALLOWAUDIOCKSTOP_BITS 0:0
656 #define PM_DFT_ALLOWAUDIOCKSTOP_SET 0x00000001
657 #define PM_DFT_ALLOWAUDIOCKSTOP_CLR 0xfffffffe
658 #define PM_DFT_ALLOWAUDIOCKSTOP_MSB 0
659 #define PM_DFT_ALLOWAUDIOCKSTOP_LSB 0
660 #define PM_DFT_STOPALLCLOCKS_BITS 1:1
661 #define PM_DFT_STOPALLCLOCKS_SET 0x00000002
662 #define PM_DFT_STOPALLCLOCKS_CLR 0xfffffffd
663 #define PM_DFT_STOPALLCLOCKS_MSB 1
664 #define PM_DFT_STOPALLCLOCKS_LSB 1
665 #define PM_SMPS HW_REGISTER_RW( 0x7e10006c )
666 #define PM_SMPS_MASK 0x00000007
667 #define PM_SMPS_WIDTH 3
668 #define PM_SMPS_RESET 0000000000
669 #define PM_SMPS_CTRLEN_BITS 0:0
670 #define PM_SMPS_CTRLEN_SET 0x00000001
671 #define PM_SMPS_CTRLEN_CLR 0xfffffffe
672 #define PM_SMPS_CTRLEN_MSB 0
673 #define PM_SMPS_CTRLEN_LSB 0
674 #define PM_SMPS_RSTDR_BITS 1:1
675 #define PM_SMPS_RSTDR_SET 0x00000002
676 #define PM_SMPS_RSTDR_CLR 0xfffffffd
677 #define PM_SMPS_RSTDR_MSB 1
678 #define PM_SMPS_RSTDR_LSB 1
679 #define PM_SMPS_UPEN_BITS 2:2
680 #define PM_SMPS_UPEN_SET 0x00000004
681 #define PM_SMPS_UPEN_CLR 0xfffffffb
682 #define PM_SMPS_UPEN_MSB 2
683 #define PM_SMPS_UPEN_LSB 2
684 #define PM_XOSC HW_REGISTER_RW( 0x7e100070 )
685 #define PM_XOSC_MASK 0x00000001
686 #define PM_XOSC_WIDTH 1
687 #define PM_XOSC_RESET 0000000000
688 #define PM_XOSC_USESEC_BITS 0:0
689 #define PM_XOSC_USESEC_SET 0x00000001
690 #define PM_XOSC_USESEC_CLR 0xfffffffe
691 #define PM_XOSC_USESEC_MSB 0
692 #define PM_XOSC_USESEC_LSB 0
693 #define PM_SPAREW HW_REGISTER_RW( 0x7e100074 )
694 #define PM_SPAREW_MASK 0x00ffffff
695 #define PM_SPAREW_WIDTH 24
696 #define PM_SPAREW_RESET 0000000000
697 #define PM_SPAREW_SPARE_BITS 23:0
698 #define PM_SPAREW_SPARE_SET 0x00ffffff
699 #define PM_SPAREW_SPARE_CLR 0xff000000
700 #define PM_SPAREW_SPARE_MSB 23
701 #define PM_SPAREW_SPARE_LSB 0
702 #define PM_SPARER HW_REGISTER_RO( 0x7e100078 )
703 #define PM_SPARER_MASK 0x00ffffff
704 #define PM_SPARER_WIDTH 24
705 #define PM_SPARER_RESET 0000000000
706 #define PM_SPARER_SPARE_BITS 23:0
707 #define PM_SPARER_SPARE_SET 0x00ffffff
708 #define PM_SPARER_SPARE_CLR 0xff000000
709 #define PM_SPARER_SPARE_MSB 23
710 #define PM_SPARER_SPARE_LSB 0
711 #define PM_AVS_RSTDR HW_REGISTER_RW( 0x7e10007c )
712 #define PM_AVS_RSTDR_MASK 0x0000003f
713 #define PM_AVS_RSTDR_WIDTH 6
714 #define PM_AVS_RSTDR_RESET 0000000000
715 #define PM_AVS_RSTDR_PERI_A_BITS 0:0
716 #define PM_AVS_RSTDR_PERI_A_SET 0x00000001
717 #define PM_AVS_RSTDR_PERI_A_CLR 0xfffffffe
718 #define PM_AVS_RSTDR_PERI_A_MSB 0
719 #define PM_AVS_RSTDR_PERI_A_LSB 0
720 #define PM_AVS_RSTDR_SYSTEM_A_BITS 1:1
721 #define PM_AVS_RSTDR_SYSTEM_A_SET 0x00000002
722 #define PM_AVS_RSTDR_SYSTEM_A_CLR 0xfffffffd
723 #define PM_AVS_RSTDR_SYSTEM_A_MSB 1
724 #define PM_AVS_RSTDR_SYSTEM_A_LSB 1
725 #define PM_AVS_RSTDR_H264_I_BITS 2:2
726 #define PM_AVS_RSTDR_H264_I_SET 0x00000004
727 #define PM_AVS_RSTDR_H264_I_CLR 0xfffffffb
728 #define PM_AVS_RSTDR_H264_I_MSB 2
729 #define PM_AVS_RSTDR_H264_I_LSB 2
730 #define PM_AVS_RSTDR_V3D_G_BITS 3:3
731 #define PM_AVS_RSTDR_V3D_G_SET 0x00000008
732 #define PM_AVS_RSTDR_V3D_G_CLR 0xfffffff7
733 #define PM_AVS_RSTDR_V3D_G_MSB 3
734 #define PM_AVS_RSTDR_V3D_G_LSB 3
735 #define PM_AVS_RSTDR_ARM_P_BITS 4:4
736 #define PM_AVS_RSTDR_ARM_P_SET 0x00000010
737 #define PM_AVS_RSTDR_ARM_P_CLR 0xffffffef
738 #define PM_AVS_RSTDR_ARM_P_MSB 4
739 #define PM_AVS_RSTDR_ARM_P_LSB 4
740 #define PM_AVS_RSTDR_ROSC_BITS 5:5
741 #define PM_AVS_RSTDR_ROSC_SET 0x00000020
742 #define PM_AVS_RSTDR_ROSC_CLR 0xffffffdf
743 #define PM_AVS_RSTDR_ROSC_MSB 5
744 #define PM_AVS_RSTDR_ROSC_LSB 5
745 #define PM_AVS_STAT HW_REGISTER_RW( 0x7e100080 )
746 #define PM_AVS_STAT_MASK 0x0000001f
747 #define PM_AVS_STAT_WIDTH 5
748 #define PM_AVS_STAT_RESET 0000000000
749 #define PM_AVS_STAT_ALERT_PERI_A_BITS 0:0
750 #define PM_AVS_STAT_ALERT_PERI_A_SET 0x00000001
751 #define PM_AVS_STAT_ALERT_PERI_A_CLR 0xfffffffe
752 #define PM_AVS_STAT_ALERT_PERI_A_MSB 0
753 #define PM_AVS_STAT_ALERT_PERI_A_LSB 0
754 #define PM_AVS_STAT_ALERT_SYSTEM_A_BITS 1:1
755 #define PM_AVS_STAT_ALERT_SYSTEM_A_SET 0x00000002
756 #define PM_AVS_STAT_ALERT_SYSTEM_A_CLR 0xfffffffd
757 #define PM_AVS_STAT_ALERT_SYSTEM_A_MSB 1
758 #define PM_AVS_STAT_ALERT_SYSTEM_A_LSB 1
759 #define PM_AVS_STAT_ALERT_H264_I_BITS 2:2
760 #define PM_AVS_STAT_ALERT_H264_I_SET 0x00000004
761 #define PM_AVS_STAT_ALERT_H264_I_CLR 0xfffffffb
762 #define PM_AVS_STAT_ALERT_H264_I_MSB 2
763 #define PM_AVS_STAT_ALERT_H264_I_LSB 2
764 #define PM_AVS_STAT_ALERT_V3D_G_BITS 3:3
765 #define PM_AVS_STAT_ALERT_V3D_G_SET 0x00000008
766 #define PM_AVS_STAT_ALERT_V3D_G_CLR 0xfffffff7
767 #define PM_AVS_STAT_ALERT_V3D_G_MSB 3
768 #define PM_AVS_STAT_ALERT_V3D_G_LSB 3
769 #define PM_AVS_STAT_ALERT_ARM_P_BITS 4:4
770 #define PM_AVS_STAT_ALERT_ARM_P_SET 0x00000010
771 #define PM_AVS_STAT_ALERT_ARM_P_CLR 0xffffffef
772 #define PM_AVS_STAT_ALERT_ARM_P_MSB 4
773 #define PM_AVS_STAT_ALERT_ARM_P_LSB 4
774 #define PM_AVS_EVENT HW_REGISTER_RW( 0x7e100084 )
775 #define PM_AVS_EVENT_MASK 0x0000001f
776 #define PM_AVS_EVENT_WIDTH 5
777 #define PM_AVS_EVENT_RESET 0000000000
778 #define PM_AVS_EVENT_ALERT_PERI_A_BITS 0:0
779 #define PM_AVS_EVENT_ALERT_PERI_A_SET 0x00000001
780 #define PM_AVS_EVENT_ALERT_PERI_A_CLR 0xfffffffe
781 #define PM_AVS_EVENT_ALERT_PERI_A_MSB 0
782 #define PM_AVS_EVENT_ALERT_PERI_A_LSB 0
783 #define PM_AVS_EVENT_ALERT_SYSTEM_A_BITS 1:1
784 #define PM_AVS_EVENT_ALERT_SYSTEM_A_SET 0x00000002
785 #define PM_AVS_EVENT_ALERT_SYSTEM_A_CLR 0xfffffffd
786 #define PM_AVS_EVENT_ALERT_SYSTEM_A_MSB 1
787 #define PM_AVS_EVENT_ALERT_SYSTEM_A_LSB 1
788 #define PM_AVS_EVENT_ALERT_H264_I_BITS 2:2
789 #define PM_AVS_EVENT_ALERT_H264_I_SET 0x00000004
790 #define PM_AVS_EVENT_ALERT_H264_I_CLR 0xfffffffb
791 #define PM_AVS_EVENT_ALERT_H264_I_MSB 2
792 #define PM_AVS_EVENT_ALERT_H264_I_LSB 2
793 #define PM_AVS_EVENT_ALERT_V3D_G_BITS 3:3
794 #define PM_AVS_EVENT_ALERT_V3D_G_SET 0x00000008
795 #define PM_AVS_EVENT_ALERT_V3D_G_CLR 0xfffffff7
796 #define PM_AVS_EVENT_ALERT_V3D_G_MSB 3
797 #define PM_AVS_EVENT_ALERT_V3D_G_LSB 3
798 #define PM_AVS_EVENT_ALERT_ARM_P_BITS 4:4
799 #define PM_AVS_EVENT_ALERT_ARM_P_SET 0x00000010
800 #define PM_AVS_EVENT_ALERT_ARM_P_CLR 0xffffffef
801 #define PM_AVS_EVENT_ALERT_ARM_P_MSB 4
802 #define PM_AVS_EVENT_ALERT_ARM_P_LSB 4
803 #define PM_AVS_INTEN HW_REGISTER_RW( 0x7e100088 )
804 #define PM_AVS_INTEN_MASK 0x0000001f
805 #define PM_AVS_INTEN_WIDTH 5
806 #define PM_AVS_INTEN_RESET 0000000000
807 #define PM_AVS_INTEN_ALERT_PERI_A_BITS 0:0
808 #define PM_AVS_INTEN_ALERT_PERI_A_SET 0x00000001
809 #define PM_AVS_INTEN_ALERT_PERI_A_CLR 0xfffffffe
810 #define PM_AVS_INTEN_ALERT_PERI_A_MSB 0
811 #define PM_AVS_INTEN_ALERT_PERI_A_LSB 0
812 #define PM_AVS_INTEN_ALERT_SYSTEM_A_BITS 1:1
813 #define PM_AVS_INTEN_ALERT_SYSTEM_A_SET 0x00000002
814 #define PM_AVS_INTEN_ALERT_SYSTEM_A_CLR 0xfffffffd
815 #define PM_AVS_INTEN_ALERT_SYSTEM_A_MSB 1
816 #define PM_AVS_INTEN_ALERT_SYSTEM_A_LSB 1
817 #define PM_AVS_INTEN_ALERT_H264_I_BITS 2:2
818 #define PM_AVS_INTEN_ALERT_H264_I_SET 0x00000004
819 #define PM_AVS_INTEN_ALERT_H264_I_CLR 0xfffffffb
820 #define PM_AVS_INTEN_ALERT_H264_I_MSB 2
821 #define PM_AVS_INTEN_ALERT_H264_I_LSB 2
822 #define PM_AVS_INTEN_ALERT_V3D_G_BITS 3:3
823 #define PM_AVS_INTEN_ALERT_V3D_G_SET 0x00000008
824 #define PM_AVS_INTEN_ALERT_V3D_G_CLR 0xfffffff7
825 #define PM_AVS_INTEN_ALERT_V3D_G_MSB 3
826 #define PM_AVS_INTEN_ALERT_V3D_G_LSB 3
827 #define PM_AVS_INTEN_ALERT_ARM_P_BITS 4:4
828 #define PM_AVS_INTEN_ALERT_ARM_P_SET 0x00000010
829 #define PM_AVS_INTEN_ALERT_ARM_P_CLR 0xffffffef
830 #define PM_AVS_INTEN_ALERT_ARM_P_MSB 4
831 #define PM_AVS_INTEN_ALERT_ARM_P_LSB 4
832 #define PM_DUMMY HW_REGISTER_RO( 0x7e1000fc )
833 #define PM_DUMMY_MASK 0x00000001
834 #define PM_DUMMY_WIDTH 1
835 #define PM_DUMMY_RESET 0x00000001
836 #define PM_DUMMY_ONE_BITS 0:0
837 #define PM_DUMMY_ONE_SET 0x00000001
838 #define PM_DUMMY_ONE_CLR 0xfffffffe
839 #define PM_DUMMY_ONE_MSB 0
840 #define PM_DUMMY_ONE_LSB 0
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