c52af0be0ce1db29d85acba199a0acef2808d9b6
[rpi-open-firmware.git] / bcm2708_chip / cpr_powman_a0.h
1 // This file was generated by the create_regs script
2 #define PM_PASSWORD 0x5a000000
3 #define PM_BASE 0x7e100000
4 #define PM_APB_ID 0x0000706d
5 #define PM_GNRIC HW_REGISTER_RW( 0x7e100000 )
6 #define PM_GNRIC_MASK 0x007f0fff
7 #define PM_GNRIC_WIDTH 23
8 #define PM_GNRIC_RESET 0000000000
9 #define PM_GNRIC_CFG_BITS 22:16
10 #define PM_GNRIC_CFG_SET 0x007f0000
11 #define PM_GNRIC_CFG_CLR 0xff80ffff
12 #define PM_GNRIC_CFG_MSB 22
13 #define PM_GNRIC_CFG_LSB 16
14 #define PM_GNRIC_RSTN_BITS 11:6
15 #define PM_GNRIC_RSTN_SET 0x00000fc0
16 #define PM_GNRIC_RSTN_CLR 0xfffff03f
17 #define PM_GNRIC_RSTN_MSB 11
18 #define PM_GNRIC_RSTN_LSB 6
19 #define PM_GNRIC_ISFUNC_BITS 5:5
20 #define PM_GNRIC_ISFUNC_SET 0x00000020
21 #define PM_GNRIC_ISFUNC_CLR 0xffffffdf
22 #define PM_GNRIC_ISFUNC_MSB 5
23 #define PM_GNRIC_ISFUNC_LSB 5
24 #define PM_GNRIC_MRDONE_BITS 4:4
25 #define PM_GNRIC_MRDONE_SET 0x00000010
26 #define PM_GNRIC_MRDONE_CLR 0xffffffef
27 #define PM_GNRIC_MRDONE_MSB 4
28 #define PM_GNRIC_MRDONE_LSB 4
29 #define PM_GNRIC_MEMREP_BITS 3:3
30 #define PM_GNRIC_MEMREP_SET 0x00000008
31 #define PM_GNRIC_MEMREP_CLR 0xfffffff7
32 #define PM_GNRIC_MEMREP_MSB 3
33 #define PM_GNRIC_MEMREP_LSB 3
34 #define PM_GNRIC_ISPOW_BITS 2:2
35 #define PM_GNRIC_ISPOW_SET 0x00000004
36 #define PM_GNRIC_ISPOW_CLR 0xfffffffb
37 #define PM_GNRIC_ISPOW_MSB 2
38 #define PM_GNRIC_ISPOW_LSB 2
39 #define PM_GNRIC_POWOK_BITS 1:1
40 #define PM_GNRIC_POWOK_SET 0x00000002
41 #define PM_GNRIC_POWOK_CLR 0xfffffffd
42 #define PM_GNRIC_POWOK_MSB 1
43 #define PM_GNRIC_POWOK_LSB 1
44 #define PM_GNRIC_POWUP_BITS 0:0
45 #define PM_GNRIC_POWUP_SET 0x00000001
46 #define PM_GNRIC_POWUP_CLR 0xfffffffe
47 #define PM_GNRIC_POWUP_MSB 0
48 #define PM_GNRIC_POWUP_LSB 0
49 #define PM_AUDIO HW_REGISTER_RW( 0x7e100004 )
50 #define PM_AUDIO_MASK 0x000101ff
51 #define PM_AUDIO_WIDTH 17
52 #define PM_AUDIO_RESET 0x00010000
53 #define PM_AUDIO_RSTN_BITS 16:16
54 #define PM_AUDIO_RSTN_SET 0x00010000
55 #define PM_AUDIO_RSTN_CLR 0xfffeffff
56 #define PM_AUDIO_RSTN_MSB 16
57 #define PM_AUDIO_RSTN_LSB 16
58 #define PM_AUDIO_CTRLEN_BITS 8:8
59 #define PM_AUDIO_CTRLEN_SET 0x00000100
60 #define PM_AUDIO_CTRLEN_CLR 0xfffffeff
61 #define PM_AUDIO_CTRLEN_MSB 8
62 #define PM_AUDIO_CTRLEN_LSB 8
63 #define PM_AUDIO_APSM_BITS 7:0
64 #define PM_AUDIO_APSM_SET 0x000000ff
65 #define PM_AUDIO_APSM_CLR 0xffffff00
66 #define PM_AUDIO_APSM_MSB 7
67 #define PM_AUDIO_APSM_LSB 0
68 #define PM_OLDIMAGE HW_REGISTER_RW( 0x7e100008 )
69 #define PM_OLDIMAGE_MASK 0x007f007f
70 #define PM_OLDIMAGE_WIDTH 23
71 #define PM_OLDIMAGE_RESET 0000000000
72 #define PM_OLDIMAGE_CFG_BITS 22:16
73 #define PM_OLDIMAGE_CFG_SET 0x007f0000
74 #define PM_OLDIMAGE_CFG_CLR 0xff80ffff
75 #define PM_OLDIMAGE_CFG_MSB 22
76 #define PM_OLDIMAGE_CFG_LSB 16
77 #define PM_OLDIMAGE_ISPRSTN_BITS 6:6
78 #define PM_OLDIMAGE_ISPRSTN_SET 0x00000040
79 #define PM_OLDIMAGE_ISPRSTN_CLR 0xffffffbf
80 #define PM_OLDIMAGE_ISPRSTN_MSB 6
81 #define PM_OLDIMAGE_ISPRSTN_LSB 6
82 #define PM_OLDIMAGE_H264RSTN_BITS 5:5
83 #define PM_OLDIMAGE_H264RSTN_SET 0x00000020
84 #define PM_OLDIMAGE_H264RSTN_CLR 0xffffffdf
85 #define PM_OLDIMAGE_H264RSTN_MSB 5
86 #define PM_OLDIMAGE_H264RSTN_LSB 5
87 #define PM_OLDIMAGE_PERIRSTN_BITS 4:4
88 #define PM_OLDIMAGE_PERIRSTN_SET 0x00000010
89 #define PM_OLDIMAGE_PERIRSTN_CLR 0xffffffef
90 #define PM_OLDIMAGE_PERIRSTN_MSB 4
91 #define PM_OLDIMAGE_PERIRSTN_LSB 4
92 #define PM_OLDIMAGE_ISFUNC_BITS 3:3
93 #define PM_OLDIMAGE_ISFUNC_SET 0x00000008
94 #define PM_OLDIMAGE_ISFUNC_CLR 0xfffffff7
95 #define PM_OLDIMAGE_ISFUNC_MSB 3
96 #define PM_OLDIMAGE_ISFUNC_LSB 3
97 #define PM_OLDIMAGE_ISPOW_BITS 2:2
98 #define PM_OLDIMAGE_ISPOW_SET 0x00000004
99 #define PM_OLDIMAGE_ISPOW_CLR 0xfffffffb
100 #define PM_OLDIMAGE_ISPOW_MSB 2
101 #define PM_OLDIMAGE_ISPOW_LSB 2
102 #define PM_OLDIMAGE_POWOK_BITS 1:1
103 #define PM_OLDIMAGE_POWOK_SET 0x00000002
104 #define PM_OLDIMAGE_POWOK_CLR 0xfffffffd
105 #define PM_OLDIMAGE_POWOK_MSB 1
106 #define PM_OLDIMAGE_POWOK_LSB 1
107 #define PM_OLDIMAGE_POWUP_BITS 0:0
108 #define PM_OLDIMAGE_POWUP_SET 0x00000001
109 #define PM_OLDIMAGE_POWUP_CLR 0xfffffffe
110 #define PM_OLDIMAGE_POWUP_MSB 0
111 #define PM_OLDIMAGE_POWUP_LSB 0
112 #define PM_OLDGRAFX HW_REGISTER_RW( 0x7e10000c )
113 #define PM_OLDGRAFX_MASK 0x007f008f
114 #define PM_OLDGRAFX_WIDTH 23
115 #define PM_OLDGRAFX_RESET 0000000000
116 #define PM_OLDGRAFX_CFG_BITS 22:16
117 #define PM_OLDGRAFX_CFG_SET 0x007f0000
118 #define PM_OLDGRAFX_CFG_CLR 0xff80ffff
119 #define PM_OLDGRAFX_CFG_MSB 22
120 #define PM_OLDGRAFX_CFG_LSB 16
121 #define PM_OLDGRAFX_V3DRSTN_BITS 7:7
122 #define PM_OLDGRAFX_V3DRSTN_SET 0x00000080
123 #define PM_OLDGRAFX_V3DRSTN_CLR 0xffffff7f
124 #define PM_OLDGRAFX_V3DRSTN_MSB 7
125 #define PM_OLDGRAFX_V3DRSTN_LSB 7
126 #define PM_OLDGRAFX_ISFUNC_BITS 3:3
127 #define PM_OLDGRAFX_ISFUNC_SET 0x00000008
128 #define PM_OLDGRAFX_ISFUNC_CLR 0xfffffff7
129 #define PM_OLDGRAFX_ISFUNC_MSB 3
130 #define PM_OLDGRAFX_ISFUNC_LSB 3
131 #define PM_OLDGRAFX_ISPOW_BITS 2:2
132 #define PM_OLDGRAFX_ISPOW_SET 0x00000004
133 #define PM_OLDGRAFX_ISPOW_CLR 0xfffffffb
134 #define PM_OLDGRAFX_ISPOW_MSB 2
135 #define PM_OLDGRAFX_ISPOW_LSB 2
136 #define PM_OLDGRAFX_POWOK_BITS 1:1
137 #define PM_OLDGRAFX_POWOK_SET 0x00000002
138 #define PM_OLDGRAFX_POWOK_CLR 0xfffffffd
139 #define PM_OLDGRAFX_POWOK_MSB 1
140 #define PM_OLDGRAFX_POWOK_LSB 1
141 #define PM_OLDGRAFX_POWUP_BITS 0:0
142 #define PM_OLDGRAFX_POWUP_SET 0x00000001
143 #define PM_OLDGRAFX_POWUP_CLR 0xfffffffe
144 #define PM_OLDGRAFX_POWUP_MSB 0
145 #define PM_OLDGRAFX_POWUP_LSB 0
146 #define PM_IMAGE HW_REGISTER_RW( 0x7e100108 )
147 #define PM_IMAGE_MASK 0x007f01ff
148 #define PM_IMAGE_WIDTH 23
149 #define PM_IMAGE_RESET 0000000000
150 #define PM_IMAGE_CFG_BITS 22:16
151 #define PM_IMAGE_CFG_SET 0x007f0000
152 #define PM_IMAGE_CFG_CLR 0xff80ffff
153 #define PM_IMAGE_CFG_MSB 22
154 #define PM_IMAGE_CFG_LSB 16
155 #define PM_IMAGE_ISPRSTN_BITS 8:8
156 #define PM_IMAGE_ISPRSTN_SET 0x00000100
157 #define PM_IMAGE_ISPRSTN_CLR 0xfffffeff
158 #define PM_IMAGE_ISPRSTN_MSB 8
159 #define PM_IMAGE_ISPRSTN_LSB 8
160 #define PM_IMAGE_H264RSTN_BITS 7:7
161 #define PM_IMAGE_H264RSTN_SET 0x00000080
162 #define PM_IMAGE_H264RSTN_CLR 0xffffff7f
163 #define PM_IMAGE_H264RSTN_MSB 7
164 #define PM_IMAGE_H264RSTN_LSB 7
165 #define PM_IMAGE_PERIRSTN_BITS 6:6
166 #define PM_IMAGE_PERIRSTN_SET 0x00000040
167 #define PM_IMAGE_PERIRSTN_CLR 0xffffffbf
168 #define PM_IMAGE_PERIRSTN_MSB 6
169 #define PM_IMAGE_PERIRSTN_LSB 6
170 #define PM_IMAGE_ISFUNC_BITS 5:5
171 #define PM_IMAGE_ISFUNC_SET 0x00000020
172 #define PM_IMAGE_ISFUNC_CLR 0xffffffdf
173 #define PM_IMAGE_ISFUNC_MSB 5
174 #define PM_IMAGE_ISFUNC_LSB 5
175 #define PM_IMAGE_MRDONE_BITS 4:4
176 #define PM_IMAGE_MRDONE_SET 0x00000010
177 #define PM_IMAGE_MRDONE_CLR 0xffffffef
178 #define PM_IMAGE_MRDONE_MSB 4
179 #define PM_IMAGE_MRDONE_LSB 4
180 #define PM_IMAGE_MEMREP_BITS 3:3
181 #define PM_IMAGE_MEMREP_SET 0x00000008
182 #define PM_IMAGE_MEMREP_CLR 0xfffffff7
183 #define PM_IMAGE_MEMREP_MSB 3
184 #define PM_IMAGE_MEMREP_LSB 3
185 #define PM_IMAGE_ISPOW_BITS 2:2
186 #define PM_IMAGE_ISPOW_SET 0x00000004
187 #define PM_IMAGE_ISPOW_CLR 0xfffffffb
188 #define PM_IMAGE_ISPOW_MSB 2
189 #define PM_IMAGE_ISPOW_LSB 2
190 #define PM_IMAGE_POWOK_BITS 1:1
191 #define PM_IMAGE_POWOK_SET 0x00000002
192 #define PM_IMAGE_POWOK_CLR 0xfffffffd
193 #define PM_IMAGE_POWOK_MSB 1
194 #define PM_IMAGE_POWOK_LSB 1
195 #define PM_IMAGE_POWUP_BITS 0:0
196 #define PM_IMAGE_POWUP_SET 0x00000001
197 #define PM_IMAGE_POWUP_CLR 0xfffffffe
198 #define PM_IMAGE_POWUP_MSB 0
199 #define PM_IMAGE_POWUP_LSB 0
200 #define PM_GRAFX HW_REGISTER_RW( 0x7e10010c )
201 #define PM_GRAFX_MASK 0x007f007f
202 #define PM_GRAFX_WIDTH 23
203 #define PM_GRAFX_RESET 0000000000
204 #define PM_GRAFX_CFG_BITS 22:16
205 #define PM_GRAFX_CFG_SET 0x007f0000
206 #define PM_GRAFX_CFG_CLR 0xff80ffff
207 #define PM_GRAFX_CFG_MSB 22
208 #define PM_GRAFX_CFG_LSB 16
209 #define PM_GRAFX_V3DRSTN_BITS 6:6
210 #define PM_GRAFX_V3DRSTN_SET 0x00000040
211 #define PM_GRAFX_V3DRSTN_CLR 0xffffffbf
212 #define PM_GRAFX_V3DRSTN_MSB 6
213 #define PM_GRAFX_V3DRSTN_LSB 6
214 #define PM_GRAFX_ISFUNC_BITS 5:5
215 #define PM_GRAFX_ISFUNC_SET 0x00000020
216 #define PM_GRAFX_ISFUNC_CLR 0xffffffdf
217 #define PM_GRAFX_ISFUNC_MSB 5
218 #define PM_GRAFX_ISFUNC_LSB 5
219 #define PM_GRAFX_MRDONE_BITS 4:4
220 #define PM_GRAFX_MRDONE_SET 0x00000010
221 #define PM_GRAFX_MRDONE_CLR 0xffffffef
222 #define PM_GRAFX_MRDONE_MSB 4
223 #define PM_GRAFX_MRDONE_LSB 4
224 #define PM_GRAFX_MEMREP_BITS 3:3
225 #define PM_GRAFX_MEMREP_SET 0x00000008
226 #define PM_GRAFX_MEMREP_CLR 0xfffffff7
227 #define PM_GRAFX_MEMREP_MSB 3
228 #define PM_GRAFX_MEMREP_LSB 3
229 #define PM_GRAFX_ISPOW_BITS 2:2
230 #define PM_GRAFX_ISPOW_SET 0x00000004
231 #define PM_GRAFX_ISPOW_CLR 0xfffffffb
232 #define PM_GRAFX_ISPOW_MSB 2
233 #define PM_GRAFX_ISPOW_LSB 2
234 #define PM_GRAFX_POWOK_BITS 1:1
235 #define PM_GRAFX_POWOK_SET 0x00000002
236 #define PM_GRAFX_POWOK_CLR 0xfffffffd
237 #define PM_GRAFX_POWOK_MSB 1
238 #define PM_GRAFX_POWOK_LSB 1
239 #define PM_GRAFX_POWUP_BITS 0:0
240 #define PM_GRAFX_POWUP_SET 0x00000001
241 #define PM_GRAFX_POWUP_CLR 0xfffffffe
242 #define PM_GRAFX_POWUP_MSB 0
243 #define PM_GRAFX_POWUP_LSB 0
244 #define PM_PROC HW_REGISTER_RW( 0x7e100110 )
245 #define PM_PROC_MASK 0x007f107f
246 #define PM_PROC_WIDTH 23
247 #define PM_PROC_RESET 0000000000
248 #define PM_PROC_CFG_BITS 22:16
249 #define PM_PROC_CFG_SET 0x007f0000
250 #define PM_PROC_CFG_CLR 0xff80ffff
251 #define PM_PROC_CFG_MSB 22
252 #define PM_PROC_CFG_LSB 16
253 #define PM_PROC_ENAB_BITS 12:12
254 #define PM_PROC_ENAB_SET 0x00001000
255 #define PM_PROC_ENAB_CLR 0xffffefff
256 #define PM_PROC_ENAB_MSB 12
257 #define PM_PROC_ENAB_LSB 12
258 #define PM_PROC_ARMRSTN_BITS 6:6
259 #define PM_PROC_ARMRSTN_SET 0x00000040
260 #define PM_PROC_ARMRSTN_CLR 0xffffffbf
261 #define PM_PROC_ARMRSTN_MSB 6
262 #define PM_PROC_ARMRSTN_LSB 6
263 #define PM_PROC_ISFUNC_BITS 5:5
264 #define PM_PROC_ISFUNC_SET 0x00000020
265 #define PM_PROC_ISFUNC_CLR 0xffffffdf
266 #define PM_PROC_ISFUNC_MSB 5
267 #define PM_PROC_ISFUNC_LSB 5
268 #define PM_PROC_MRDONE_BITS 4:4
269 #define PM_PROC_MRDONE_SET 0x00000010
270 #define PM_PROC_MRDONE_CLR 0xffffffef
271 #define PM_PROC_MRDONE_MSB 4
272 #define PM_PROC_MRDONE_LSB 4
273 #define PM_PROC_MEMREP_BITS 3:3
274 #define PM_PROC_MEMREP_SET 0x00000008
275 #define PM_PROC_MEMREP_CLR 0xfffffff7
276 #define PM_PROC_MEMREP_MSB 3
277 #define PM_PROC_MEMREP_LSB 3
278 #define PM_PROC_ISPOW_BITS 2:2
279 #define PM_PROC_ISPOW_SET 0x00000004
280 #define PM_PROC_ISPOW_CLR 0xfffffffb
281 #define PM_PROC_ISPOW_MSB 2
282 #define PM_PROC_ISPOW_LSB 2
283 #define PM_PROC_POWOK_BITS 1:1
284 #define PM_PROC_POWOK_SET 0x00000002
285 #define PM_PROC_POWOK_CLR 0xfffffffd
286 #define PM_PROC_POWOK_MSB 1
287 #define PM_PROC_POWOK_LSB 1
288 #define PM_PROC_POWUP_BITS 0:0
289 #define PM_PROC_POWUP_SET 0x00000001
290 #define PM_PROC_POWUP_CLR 0xfffffffe
291 #define PM_PROC_POWUP_MSB 0
292 #define PM_PROC_POWUP_LSB 0
293 #define PM_OTPPOR HW_REGISTER_RW( 0x7e100010 )
294 #define PM_OTPPOR_MASK 0x00ffffff
295 #define PM_OTPPOR_WIDTH 24
296 #define PM_OTPPOR_RESET 0000000000
297 #define PM_OTPPOR_KEY_BITS 23:0
298 #define PM_OTPPOR_KEY_SET 0x00ffffff
299 #define PM_OTPPOR_KEY_CLR 0xff000000
300 #define PM_OTPPOR_KEY_MSB 23
301 #define PM_OTPPOR_KEY_LSB 0
302 #define PM_AUDIOPOR HW_REGISTER_RW( 0x7e100014 )
303 #define PM_AUDIOPOR_MASK 0x00ffffff
304 #define PM_AUDIOPOR_WIDTH 24
305 #define PM_AUDIOPOR_RESET 0000000000
306 #define PM_AUDIOPOR_KEY_BITS 23:0
307 #define PM_AUDIOPOR_KEY_SET 0x00ffffff
308 #define PM_AUDIOPOR_KEY_CLR 0xff000000
309 #define PM_AUDIOPOR_KEY_MSB 23
310 #define PM_AUDIOPOR_KEY_LSB 0
311 #define PM_POR HW_REGISTER_RO( 0x7e100018 )
312 #define PM_POR_MASK 0x000007ff
313 #define PM_POR_WIDTH 11
314 #define PM_POR_RESET 0000000000
315 #define PM_POR_STATUS_BITS 10:0
316 #define PM_POR_STATUS_SET 0x000007ff
317 #define PM_POR_STATUS_CLR 0xfffff800
318 #define PM_POR_STATUS_MSB 10
319 #define PM_POR_STATUS_LSB 0
320 #define PM_RSTC HW_REGISTER_RW( 0x7e10001c )
321 #define PM_RSTC_MASK 0x00333333
322 #define PM_RSTC_WIDTH 22
323 #define PM_RSTC_RESET 0x00000102
324 #define PM_RSTC_HRCFG_BITS 21:20
325 #define PM_RSTC_HRCFG_SET 0x00300000
326 #define PM_RSTC_HRCFG_CLR 0xffcfffff
327 #define PM_RSTC_HRCFG_MSB 21
328 #define PM_RSTC_HRCFG_LSB 20
329 #define PM_RSTC_FRCFG_BITS 17:16
330 #define PM_RSTC_FRCFG_SET 0x00030000
331 #define PM_RSTC_FRCFG_CLR 0xfffcffff
332 #define PM_RSTC_FRCFG_MSB 17
333 #define PM_RSTC_FRCFG_LSB 16
334 #define PM_RSTC_QRCFG_BITS 13:12
335 #define PM_RSTC_QRCFG_SET 0x00003000
336 #define PM_RSTC_QRCFG_CLR 0xffffcfff
337 #define PM_RSTC_QRCFG_MSB 13
338 #define PM_RSTC_QRCFG_LSB 12
339 #define PM_RSTC_SRCFG_BITS 9:8
340 #define PM_RSTC_SRCFG_SET 0x00000300
341 #define PM_RSTC_SRCFG_CLR 0xfffffcff
342 #define PM_RSTC_SRCFG_MSB 9
343 #define PM_RSTC_SRCFG_LSB 8
344 #define PM_RSTC_WRCFG_BITS 5:4
345 #define PM_RSTC_WRCFG_SET 0x00000030
346 #define PM_RSTC_WRCFG_CLR 0xffffffcf
347 #define PM_RSTC_WRCFG_MSB 5
348 #define PM_RSTC_WRCFG_LSB 4
349 #define PM_RSTC_DRCFG_BITS 1:0
350 #define PM_RSTC_DRCFG_SET 0x00000003
351 #define PM_RSTC_DRCFG_CLR 0xfffffffc
352 #define PM_RSTC_DRCFG_MSB 1
353 #define PM_RSTC_DRCFG_LSB 0
354 #define PM_RSTS HW_REGISTER_RW( 0x7e100020 )
355 #define PM_RSTS_MASK 0x00001777
356 #define PM_RSTS_WIDTH 13
357 #define PM_RSTS_RESET 0x00001000
358 #define PM_RSTS_HADPOR_BITS 12:12
359 #define PM_RSTS_HADPOR_SET 0x00001000
360 #define PM_RSTS_HADPOR_CLR 0xffffefff
361 #define PM_RSTS_HADPOR_MSB 12
362 #define PM_RSTS_HADPOR_LSB 12
363 #define PM_RSTS_HADSRH_BITS 10:10
364 #define PM_RSTS_HADSRH_SET 0x00000400
365 #define PM_RSTS_HADSRH_CLR 0xfffffbff
366 #define PM_RSTS_HADSRH_MSB 10
367 #define PM_RSTS_HADSRH_LSB 10
368 #define PM_RSTS_HADSRF_BITS 9:9
369 #define PM_RSTS_HADSRF_SET 0x00000200
370 #define PM_RSTS_HADSRF_CLR 0xfffffdff
371 #define PM_RSTS_HADSRF_MSB 9
372 #define PM_RSTS_HADSRF_LSB 9
373 #define PM_RSTS_HADSRQ_BITS 8:8
374 #define PM_RSTS_HADSRQ_SET 0x00000100
375 #define PM_RSTS_HADSRQ_CLR 0xfffffeff
376 #define PM_RSTS_HADSRQ_MSB 8
377 #define PM_RSTS_HADSRQ_LSB 8
378 #define PM_RSTS_HADWRH_BITS 6:6
379 #define PM_RSTS_HADWRH_SET 0x00000040
380 #define PM_RSTS_HADWRH_CLR 0xffffffbf
381 #define PM_RSTS_HADWRH_MSB 6
382 #define PM_RSTS_HADWRH_LSB 6
383 #define PM_RSTS_HADWRF_BITS 5:5
384 #define PM_RSTS_HADWRF_SET 0x00000020
385 #define PM_RSTS_HADWRF_CLR 0xffffffdf
386 #define PM_RSTS_HADWRF_MSB 5
387 #define PM_RSTS_HADWRF_LSB 5
388 #define PM_RSTS_HADWRQ_BITS 4:4
389 #define PM_RSTS_HADWRQ_SET 0x00000010
390 #define PM_RSTS_HADWRQ_CLR 0xffffffef
391 #define PM_RSTS_HADWRQ_MSB 4
392 #define PM_RSTS_HADWRQ_LSB 4
393 #define PM_RSTS_HADDRH_BITS 2:2
394 #define PM_RSTS_HADDRH_SET 0x00000004
395 #define PM_RSTS_HADDRH_CLR 0xfffffffb
396 #define PM_RSTS_HADDRH_MSB 2
397 #define PM_RSTS_HADDRH_LSB 2
398 #define PM_RSTS_HADDRF_BITS 1:1
399 #define PM_RSTS_HADDRF_SET 0x00000002
400 #define PM_RSTS_HADDRF_CLR 0xfffffffd
401 #define PM_RSTS_HADDRF_MSB 1
402 #define PM_RSTS_HADDRF_LSB 1
403 #define PM_RSTS_HADDRQ_BITS 0:0
404 #define PM_RSTS_HADDRQ_SET 0x00000001
405 #define PM_RSTS_HADDRQ_CLR 0xfffffffe
406 #define PM_RSTS_HADDRQ_MSB 0
407 #define PM_RSTS_HADDRQ_LSB 0
408 #define PM_WDOG HW_REGISTER_RW( 0x7e100024 )
409 #define PM_WDOG_MASK 0x00000fff
410 #define PM_WDOG_WIDTH 12
411 #define PM_WDOG_RESET 0000000000
412 #define PM_WDOG_TIME_BITS 11:0
413 #define PM_WDOG_TIME_SET 0x00000fff
414 #define PM_WDOG_TIME_CLR 0xfffff000
415 #define PM_WDOG_TIME_MSB 11
416 #define PM_WDOG_TIME_LSB 0
417 #define PM_PADS0 HW_REGISTER_RW( 0x7e100028 )
418 #define PM_PADS0_MASK 0x0000003f
419 #define PM_PADS0_WIDTH 6
420 #define PM_PADS0_RESET 0x0000001b
421 #define PM_PADS0_DRIVE_BITS 2:0
422 #define PM_PADS0_DRIVE_SET 0x00000007
423 #define PM_PADS0_DRIVE_CLR 0xfffffff8
424 #define PM_PADS0_DRIVE_MSB 2
425 #define PM_PADS0_DRIVE_LSB 0
426 #define PM_PADS0_HYST_BITS 3:3
427 #define PM_PADS0_HYST_SET 0x00000008
428 #define PM_PADS0_HYST_CLR 0xfffffff7
429 #define PM_PADS0_HYST_MSB 3
430 #define PM_PADS0_HYST_LSB 3
431 #define PM_PADS0_SLEW_BITS 4:4
432 #define PM_PADS0_SLEW_SET 0x00000010
433 #define PM_PADS0_SLEW_CLR 0xffffffef
434 #define PM_PADS0_SLEW_MSB 4
435 #define PM_PADS0_SLEW_LSB 4
436 #define PM_PADS0_POWOK_BITS 5:5
437 #define PM_PADS0_POWOK_SET 0x00000020
438 #define PM_PADS0_POWOK_CLR 0xffffffdf
439 #define PM_PADS0_POWOK_MSB 5
440 #define PM_PADS0_POWOK_LSB 5
441 #define PM_PADS2 HW_REGISTER_RW( 0x7e10002c )
442 #define PM_PADS2_MASK 0x0000003f
443 #define PM_PADS2_WIDTH 6
444 #define PM_PADS2_RESET 0x0000001b
445 #define PM_PADS2_DRIVE_BITS 2:0
446 #define PM_PADS2_DRIVE_SET 0x00000007
447 #define PM_PADS2_DRIVE_CLR 0xfffffff8
448 #define PM_PADS2_DRIVE_MSB 2
449 #define PM_PADS2_DRIVE_LSB 0
450 #define PM_PADS2_HYST_BITS 3:3
451 #define PM_PADS2_HYST_SET 0x00000008
452 #define PM_PADS2_HYST_CLR 0xfffffff7
453 #define PM_PADS2_HYST_MSB 3
454 #define PM_PADS2_HYST_LSB 3
455 #define PM_PADS2_SLEW_BITS 4:4
456 #define PM_PADS2_SLEW_SET 0x00000010
457 #define PM_PADS2_SLEW_CLR 0xffffffef
458 #define PM_PADS2_SLEW_MSB 4
459 #define PM_PADS2_SLEW_LSB 4
460 #define PM_PADS2_POWOK_BITS 5:5
461 #define PM_PADS2_POWOK_SET 0x00000020
462 #define PM_PADS2_POWOK_CLR 0xffffffdf
463 #define PM_PADS2_POWOK_MSB 5
464 #define PM_PADS2_POWOK_LSB 5
465 #define PM_PADS3 HW_REGISTER_RW( 0x7e100030 )
466 #define PM_PADS3_MASK 0x0000003f
467 #define PM_PADS3_WIDTH 6
468 #define PM_PADS3_RESET 0x0000001b
469 #define PM_PADS3_DRIVE_BITS 2:0
470 #define PM_PADS3_DRIVE_SET 0x00000007
471 #define PM_PADS3_DRIVE_CLR 0xfffffff8
472 #define PM_PADS3_DRIVE_MSB 2
473 #define PM_PADS3_DRIVE_LSB 0
474 #define PM_PADS3_HYST_BITS 3:3
475 #define PM_PADS3_HYST_SET 0x00000008
476 #define PM_PADS3_HYST_CLR 0xfffffff7
477 #define PM_PADS3_HYST_MSB 3
478 #define PM_PADS3_HYST_LSB 3
479 #define PM_PADS3_SLEW_BITS 4:4
480 #define PM_PADS3_SLEW_SET 0x00000010
481 #define PM_PADS3_SLEW_CLR 0xffffffef
482 #define PM_PADS3_SLEW_MSB 4
483 #define PM_PADS3_SLEW_LSB 4
484 #define PM_PADS3_POWOK_BITS 5:5
485 #define PM_PADS3_POWOK_SET 0x00000020
486 #define PM_PADS3_POWOK_CLR 0xffffffdf
487 #define PM_PADS3_POWOK_MSB 5
488 #define PM_PADS3_POWOK_LSB 5
489 #define PM_PADS4 HW_REGISTER_RW( 0x7e100034 )
490 #define PM_PADS4_MASK 0x0000003f
491 #define PM_PADS4_WIDTH 6
492 #define PM_PADS4_RESET 0x0000001b
493 #define PM_PADS4_DRIVE_BITS 2:0
494 #define PM_PADS4_DRIVE_SET 0x00000007
495 #define PM_PADS4_DRIVE_CLR 0xfffffff8
496 #define PM_PADS4_DRIVE_MSB 2
497 #define PM_PADS4_DRIVE_LSB 0
498 #define PM_PADS4_HYST_BITS 3:3
499 #define PM_PADS4_HYST_SET 0x00000008
500 #define PM_PADS4_HYST_CLR 0xfffffff7
501 #define PM_PADS4_HYST_MSB 3
502 #define PM_PADS4_HYST_LSB 3
503 #define PM_PADS4_SLEW_BITS 4:4
504 #define PM_PADS4_SLEW_SET 0x00000010
505 #define PM_PADS4_SLEW_CLR 0xffffffef
506 #define PM_PADS4_SLEW_MSB 4
507 #define PM_PADS4_SLEW_LSB 4
508 #define PM_PADS4_POWOK_BITS 5:5
509 #define PM_PADS4_POWOK_SET 0x00000020
510 #define PM_PADS4_POWOK_CLR 0xffffffdf
511 #define PM_PADS4_POWOK_MSB 5
512 #define PM_PADS4_POWOK_LSB 5
513 #define PM_PADS5 HW_REGISTER_RW( 0x7e100038 )
514 #define PM_PADS5_MASK 0x0000007f
515 #define PM_PADS5_WIDTH 7
516 #define PM_PADS5_RESET 0x0000001b
517 #define PM_PADS5_DRIVE_BITS 2:0
518 #define PM_PADS5_DRIVE_SET 0x00000007
519 #define PM_PADS5_DRIVE_CLR 0xfffffff8
520 #define PM_PADS5_DRIVE_MSB 2
521 #define PM_PADS5_DRIVE_LSB 0
522 #define PM_PADS5_HYST_BITS 3:3
523 #define PM_PADS5_HYST_SET 0x00000008
524 #define PM_PADS5_HYST_CLR 0xfffffff7
525 #define PM_PADS5_HYST_MSB 3
526 #define PM_PADS5_HYST_LSB 3
527 #define PM_PADS5_SLEW_BITS 4:4
528 #define PM_PADS5_SLEW_SET 0x00000010
529 #define PM_PADS5_SLEW_CLR 0xffffffef
530 #define PM_PADS5_SLEW_MSB 4
531 #define PM_PADS5_SLEW_LSB 4
532 #define PM_PADS5_POWOK_BITS 5:5
533 #define PM_PADS5_POWOK_SET 0x00000020
534 #define PM_PADS5_POWOK_CLR 0xffffffdf
535 #define PM_PADS5_POWOK_MSB 5
536 #define PM_PADS5_POWOK_LSB 5
537 #define PM_PADS5_I2CMODE_BITS 6:6
538 #define PM_PADS5_I2CMODE_SET 0x00000040
539 #define PM_PADS5_I2CMODE_CLR 0xffffffbf
540 #define PM_PADS5_I2CMODE_MSB 6
541 #define PM_PADS5_I2CMODE_LSB 6
542 #define PM_PADS6 HW_REGISTER_RW( 0x7e10003c )
543 #define PM_PADS6_MASK 0x00000023
544 #define PM_PADS6_WIDTH 6
545 #define PM_PADS6_RESET 0000000000
546 #define PM_PADS6_DRIVE_BITS 1:0
547 #define PM_PADS6_DRIVE_SET 0x00000003
548 #define PM_PADS6_DRIVE_CLR 0xfffffffc
549 #define PM_PADS6_DRIVE_MSB 1
550 #define PM_PADS6_DRIVE_LSB 0
551 #define PM_PADS6_POWOK_BITS 5:5
552 #define PM_PADS6_POWOK_SET 0x00000020
553 #define PM_PADS6_POWOK_CLR 0xffffffdf
554 #define PM_PADS6_POWOK_MSB 5
555 #define PM_PADS6_POWOK_LSB 5
556 #define PM_MEMS HW_REGISTER_RW( 0x7e100040 )
557 #define PM_MEMS_MASK 0x00000001
558 #define PM_MEMS_WIDTH 1
559 #define PM_MEMS_RESET 0000000000
560 #define PM_MEMS_LOWVOLT_BITS 0:0
561 #define PM_MEMS_LOWVOLT_SET 0x00000001
562 #define PM_MEMS_LOWVOLT_CLR 0xfffffffe
563 #define PM_MEMS_LOWVOLT_MSB 0
564 #define PM_MEMS_LOWVOLT_LSB 0
565 #define PM_CAM0 HW_REGISTER_RW( 0x7e100044 )
566 #define PM_CAM0_MASK 0x001fffff
567 #define PM_CAM0_WIDTH 21
568 #define PM_CAM0_RESET 0000000000
569 #define PM_CAM0_CTRLEN_BITS 0:0
570 #define PM_CAM0_CTRLEN_SET 0x00000001
571 #define PM_CAM0_CTRLEN_CLR 0xfffffffe
572 #define PM_CAM0_CTRLEN_MSB 0
573 #define PM_CAM0_CTRLEN_LSB 0
574 #define PM_CAM0_LDOLPEN_BITS 1:1
575 #define PM_CAM0_LDOLPEN_SET 0x00000002
576 #define PM_CAM0_LDOLPEN_CLR 0xfffffffd
577 #define PM_CAM0_LDOLPEN_MSB 1
578 #define PM_CAM0_LDOLPEN_LSB 1
579 #define PM_CAM0_LDOHPEN_BITS 2:2
580 #define PM_CAM0_LDOHPEN_SET 0x00000004
581 #define PM_CAM0_LDOHPEN_CLR 0xfffffffb
582 #define PM_CAM0_LDOHPEN_MSB 2
583 #define PM_CAM0_LDOHPEN_LSB 2
584 #define PM_CAM0_LDOCTRL_BITS 20:3
585 #define PM_CAM0_LDOCTRL_SET 0x001ffff8
586 #define PM_CAM0_LDOCTRL_CLR 0xffe00007
587 #define PM_CAM0_LDOCTRL_MSB 20
588 #define PM_CAM0_LDOCTRL_LSB 3
589 #define PM_CAM1 HW_REGISTER_RW( 0x7e100048 )
590 #define PM_CAM1_MASK 0x001fffff
591 #define PM_CAM1_WIDTH 21
592 #define PM_CAM1_RESET 0000000000
593 #define PM_CAM1_CTRLEN_BITS 0:0
594 #define PM_CAM1_CTRLEN_SET 0x00000001
595 #define PM_CAM1_CTRLEN_CLR 0xfffffffe
596 #define PM_CAM1_CTRLEN_MSB 0
597 #define PM_CAM1_CTRLEN_LSB 0
598 #define PM_CAM1_LDOLPEN_BITS 1:1
599 #define PM_CAM1_LDOLPEN_SET 0x00000002
600 #define PM_CAM1_LDOLPEN_CLR 0xfffffffd
601 #define PM_CAM1_LDOLPEN_MSB 1
602 #define PM_CAM1_LDOLPEN_LSB 1
603 #define PM_CAM1_LDOHPEN_BITS 2:2
604 #define PM_CAM1_LDOHPEN_SET 0x00000004
605 #define PM_CAM1_LDOHPEN_CLR 0xfffffffb
606 #define PM_CAM1_LDOHPEN_MSB 2
607 #define PM_CAM1_LDOHPEN_LSB 2
608 #define PM_CAM1_LDOCTRL_BITS 20:3
609 #define PM_CAM1_LDOCTRL_SET 0x001ffff8
610 #define PM_CAM1_LDOCTRL_CLR 0xffe00007
611 #define PM_CAM1_LDOCTRL_MSB 20
612 #define PM_CAM1_LDOCTRL_LSB 3
613 #define PM_CCP2TX HW_REGISTER_RW( 0x7e10004c )
614 #define PM_CCP2TX_MASK 0x0007ffff
615 #define PM_CCP2TX_WIDTH 19
616 #define PM_CCP2TX_RESET 0000000000
617 #define PM_CCP2TX_CTRLEN_BITS 0:0
618 #define PM_CCP2TX_CTRLEN_SET 0x00000001
619 #define PM_CCP2TX_CTRLEN_CLR 0xfffffffe
620 #define PM_CCP2TX_CTRLEN_MSB 0
621 #define PM_CCP2TX_CTRLEN_LSB 0
622 #define PM_CCP2TX_LDOEN_BITS 1:1
623 #define PM_CCP2TX_LDOEN_SET 0x00000002
624 #define PM_CCP2TX_LDOEN_CLR 0xfffffffd
625 #define PM_CCP2TX_LDOEN_MSB 1
626 #define PM_CCP2TX_LDOEN_LSB 1
627 #define PM_CCP2TX_LDOCTRL_BITS 18:2
628 #define PM_CCP2TX_LDOCTRL_SET 0x0007fffc
629 #define PM_CCP2TX_LDOCTRL_CLR 0xfff80003
630 #define PM_CCP2TX_LDOCTRL_MSB 18
631 #define PM_CCP2TX_LDOCTRL_LSB 2
632 #define PM_DSI0 HW_REGISTER_RW( 0x7e100050 )
633 #define PM_DSI0_MASK 0x001fffff
634 #define PM_DSI0_WIDTH 21
635 #define PM_DSI0_RESET 0000000000
636 #define PM_DSI0_CTRLEN_BITS 0:0
637 #define PM_DSI0_CTRLEN_SET 0x00000001
638 #define PM_DSI0_CTRLEN_CLR 0xfffffffe
639 #define PM_DSI0_CTRLEN_MSB 0
640 #define PM_DSI0_CTRLEN_LSB 0
641 #define PM_DSI0_LDOLPEN_BITS 1:1
642 #define PM_DSI0_LDOLPEN_SET 0x00000002
643 #define PM_DSI0_LDOLPEN_CLR 0xfffffffd
644 #define PM_DSI0_LDOLPEN_MSB 1
645 #define PM_DSI0_LDOLPEN_LSB 1
646 #define PM_DSI0_LDOHPEN_BITS 2:2
647 #define PM_DSI0_LDOHPEN_SET 0x00000004
648 #define PM_DSI0_LDOHPEN_CLR 0xfffffffb
649 #define PM_DSI0_LDOHPEN_MSB 2
650 #define PM_DSI0_LDOHPEN_LSB 2
651 #define PM_DSI0_LDOCTRL_BITS 20:3
652 #define PM_DSI0_LDOCTRL_SET 0x001ffff8
653 #define PM_DSI0_LDOCTRL_CLR 0xffe00007
654 #define PM_DSI0_LDOCTRL_MSB 20
655 #define PM_DSI0_LDOCTRL_LSB 3
656 #define PM_DSI1 HW_REGISTER_RW( 0x7e100054 )
657 #define PM_DSI1_MASK 0x001fffff
658 #define PM_DSI1_WIDTH 21
659 #define PM_DSI1_RESET 0000000000
660 #define PM_DSI1_CTRLEN_BITS 0:0
661 #define PM_DSI1_CTRLEN_SET 0x00000001
662 #define PM_DSI1_CTRLEN_CLR 0xfffffffe
663 #define PM_DSI1_CTRLEN_MSB 0
664 #define PM_DSI1_CTRLEN_LSB 0
665 #define PM_DSI1_LDOLPEN_BITS 1:1
666 #define PM_DSI1_LDOLPEN_SET 0x00000002
667 #define PM_DSI1_LDOLPEN_CLR 0xfffffffd
668 #define PM_DSI1_LDOLPEN_MSB 1
669 #define PM_DSI1_LDOLPEN_LSB 1
670 #define PM_DSI1_LDOHPEN_BITS 2:2
671 #define PM_DSI1_LDOHPEN_SET 0x00000004
672 #define PM_DSI1_LDOHPEN_CLR 0xfffffffb
673 #define PM_DSI1_LDOHPEN_MSB 2
674 #define PM_DSI1_LDOHPEN_LSB 2
675 #define PM_DSI1_LDOCTRL_BITS 20:3
676 #define PM_DSI1_LDOCTRL_SET 0x001ffff8
677 #define PM_DSI1_LDOCTRL_CLR 0xffe00007
678 #define PM_DSI1_LDOCTRL_MSB 20
679 #define PM_DSI1_LDOCTRL_LSB 3
680 #define PM_HDMI HW_REGISTER_RW( 0x7e100058 )
681 #define PM_HDMI_MASK 0x000fffff
682 #define PM_HDMI_WIDTH 20
683 #define PM_HDMI_RESET 0x00000002
684 #define PM_HDMI_CTRLEN_BITS 0:0
685 #define PM_HDMI_CTRLEN_SET 0x00000001
686 #define PM_HDMI_CTRLEN_CLR 0xfffffffe
687 #define PM_HDMI_CTRLEN_MSB 0
688 #define PM_HDMI_CTRLEN_LSB 0
689 #define PM_HDMI_LDOPD_BITS 1:1
690 #define PM_HDMI_LDOPD_SET 0x00000002
691 #define PM_HDMI_LDOPD_CLR 0xfffffffd
692 #define PM_HDMI_LDOPD_MSB 1
693 #define PM_HDMI_LDOPD_LSB 1
694 #define PM_HDMI_LDOCTRL_BITS 18:2
695 #define PM_HDMI_LDOCTRL_SET 0x0007fffc
696 #define PM_HDMI_LDOCTRL_CLR 0xfff80003
697 #define PM_HDMI_LDOCTRL_MSB 18
698 #define PM_HDMI_LDOCTRL_LSB 2
699 #define PM_HDMI_RSTDR_BITS 19:19
700 #define PM_HDMI_RSTDR_SET 0x00080000
701 #define PM_HDMI_RSTDR_CLR 0xfff7ffff
702 #define PM_HDMI_RSTDR_MSB 19
703 #define PM_HDMI_RSTDR_LSB 19
704 #define PM_USB HW_REGISTER_RW( 0x7e10005c )
705 #define PM_USB_MASK 0x00000001
706 #define PM_USB_WIDTH 1
707 #define PM_USB_RESET 0000000000
708 #define PM_USB_CTRLEN_BITS 0:0
709 #define PM_USB_CTRLEN_SET 0x00000001
710 #define PM_USB_CTRLEN_CLR 0xfffffffe
711 #define PM_USB_CTRLEN_MSB 0
712 #define PM_USB_CTRLEN_LSB 0
713 #define PM_PXLDO HW_REGISTER_RW( 0x7e100060 )
714 #define PM_PXLDO_MASK 0x0003ffff
715 #define PM_PXLDO_WIDTH 18
716 #define PM_PXLDO_RESET 0000000000
717 #define PM_PXLDO_CTRL_BITS 15:0
718 #define PM_PXLDO_CTRL_SET 0x0000ffff
719 #define PM_PXLDO_CTRL_CLR 0xffff0000
720 #define PM_PXLDO_CTRL_MSB 15
721 #define PM_PXLDO_CTRL_LSB 0
722 #define PM_PXLDO_RSTOSCDR_BITS 16:16
723 #define PM_PXLDO_RSTOSCDR_SET 0x00010000
724 #define PM_PXLDO_RSTOSCDR_CLR 0xfffeffff
725 #define PM_PXLDO_RSTOSCDR_MSB 16
726 #define PM_PXLDO_RSTOSCDR_LSB 16
727 #define PM_PXLDO_RSTPLLDR_BITS 17:17
728 #define PM_PXLDO_RSTPLLDR_SET 0x00020000
729 #define PM_PXLDO_RSTPLLDR_CLR 0xfffdffff
730 #define PM_PXLDO_RSTPLLDR_MSB 17
731 #define PM_PXLDO_RSTPLLDR_LSB 17
732 #define PM_PXBG HW_REGISTER_RW( 0x7e100064 )
733 #define PM_PXBG_MASK 0x0000ffff
734 #define PM_PXBG_WIDTH 16
735 #define PM_PXBG_RESET 0000000000
736 #define PM_PXBG_CTRL_BITS 15:0
737 #define PM_PXBG_CTRL_SET 0x0000ffff
738 #define PM_PXBG_CTRL_CLR 0xffff0000
739 #define PM_PXBG_CTRL_MSB 15
740 #define PM_PXBG_CTRL_LSB 0
741 #define PM_DFT HW_REGISTER_RW( 0x7e100068 )
742 #define PM_DFT_MASK 0x00000003
743 #define PM_DFT_WIDTH 2
744 #define PM_DFT_RESET 0000000000
745 #define PM_DFT_ALLOWAUDIOCKSTOP_BITS 0:0
746 #define PM_DFT_ALLOWAUDIOCKSTOP_SET 0x00000001
747 #define PM_DFT_ALLOWAUDIOCKSTOP_CLR 0xfffffffe
748 #define PM_DFT_ALLOWAUDIOCKSTOP_MSB 0
749 #define PM_DFT_ALLOWAUDIOCKSTOP_LSB 0
750 #define PM_DFT_STOPALLCLOCKS_BITS 1:1
751 #define PM_DFT_STOPALLCLOCKS_SET 0x00000002
752 #define PM_DFT_STOPALLCLOCKS_CLR 0xfffffffd
753 #define PM_DFT_STOPALLCLOCKS_MSB 1
754 #define PM_DFT_STOPALLCLOCKS_LSB 1
755 #define PM_SMPS HW_REGISTER_RW( 0x7e10006c )
756 #define PM_SMPS_MASK 0x00000007
757 #define PM_SMPS_WIDTH 3
758 #define PM_SMPS_RESET 0000000000
759 #define PM_SMPS_CTRLEN_BITS 0:0
760 #define PM_SMPS_CTRLEN_SET 0x00000001
761 #define PM_SMPS_CTRLEN_CLR 0xfffffffe
762 #define PM_SMPS_CTRLEN_MSB 0
763 #define PM_SMPS_CTRLEN_LSB 0
764 #define PM_SMPS_RSTDR_BITS 1:1
765 #define PM_SMPS_RSTDR_SET 0x00000002
766 #define PM_SMPS_RSTDR_CLR 0xfffffffd
767 #define PM_SMPS_RSTDR_MSB 1
768 #define PM_SMPS_RSTDR_LSB 1
769 #define PM_SMPS_UPEN_BITS 2:2
770 #define PM_SMPS_UPEN_SET 0x00000004
771 #define PM_SMPS_UPEN_CLR 0xfffffffb
772 #define PM_SMPS_UPEN_MSB 2
773 #define PM_SMPS_UPEN_LSB 2
774 #define PM_XOSC HW_REGISTER_RW( 0x7e100070 )
775 #define PM_XOSC_MASK 0x00000001
776 #define PM_XOSC_WIDTH 1
777 #define PM_XOSC_RESET 0000000000
778 #define PM_XOSC_USESEC_BITS 0:0
779 #define PM_XOSC_USESEC_SET 0x00000001
780 #define PM_XOSC_USESEC_CLR 0xfffffffe
781 #define PM_XOSC_USESEC_MSB 0
782 #define PM_XOSC_USESEC_LSB 0
783 #define PM_SPAREW HW_REGISTER_RW( 0x7e100074 )
784 #define PM_SPAREW_MASK 0x00ffffff
785 #define PM_SPAREW_WIDTH 24
786 #define PM_SPAREW_RESET 0000000000
787 #define PM_SPAREW_SPARE_BITS 23:0
788 #define PM_SPAREW_SPARE_SET 0x00ffffff
789 #define PM_SPAREW_SPARE_CLR 0xff000000
790 #define PM_SPAREW_SPARE_MSB 23
791 #define PM_SPAREW_SPARE_LSB 0
792 #define PM_SPARER HW_REGISTER_RO( 0x7e100078 )
793 #define PM_SPARER_MASK 0x00ffffff
794 #define PM_SPARER_WIDTH 24
795 #define PM_SPARER_RESET 0000000000
796 #define PM_SPARER_SPARE_BITS 23:0
797 #define PM_SPARER_SPARE_SET 0x00ffffff
798 #define PM_SPARER_SPARE_CLR 0xff000000
799 #define PM_SPARER_SPARE_MSB 23
800 #define PM_SPARER_SPARE_LSB 0
801 #define PM_DUMMY HW_REGISTER_RO( 0x7e1000fc )
802 #define PM_DUMMY_MASK 0x00000001
803 #define PM_DUMMY_WIDTH 1
804 #define PM_DUMMY_RESET 0x00000001
805 #define PM_DUMMY_ONE_BITS 0:0
806 #define PM_DUMMY_ONE_SET 0x00000001
807 #define PM_DUMMY_ONE_CLR 0xfffffffe
808 #define PM_DUMMY_ONE_MSB 0
809 #define PM_DUMMY_ONE_LSB 0
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