1dfb17879e254a5b66e82c8412c0a09521db46db
[rpi-open-firmware.git] / bcm2708_chip / dsi.h
1 // This file was generated by the create_regs script
2 #define DSI0_BASE 0x7e209000
3 #define DSI0_APB_ID 0x00647369
4 #define DSI0_CTRL HW_REGISTER_RW( 0x7e209000 )
5 #define DSI0_CTRL_MASK 0x00000007
6 #define DSI0_CTRL_WIDTH 3
7 #define DSI0_CTRL_RESET 0000000000
8 #define DSI0_CTRL_CTRL2_BITS 2:2
9 #define DSI0_CTRL_CTRL2_SET 0x00000004
10 #define DSI0_CTRL_CTRL2_CLR 0xfffffffb
11 #define DSI0_CTRL_CTRL2_MSB 2
12 #define DSI0_CTRL_CTRL2_LSB 2
13 #define DSI0_CTRL_CTRL1_BITS 1:1
14 #define DSI0_CTRL_CTRL1_SET 0x00000002
15 #define DSI0_CTRL_CTRL1_CLR 0xfffffffd
16 #define DSI0_CTRL_CTRL1_MSB 1
17 #define DSI0_CTRL_CTRL1_LSB 1
18 #define DSI0_CTRL_CTRL0_BITS 0:0
19 #define DSI0_CTRL_CTRL0_SET 0x00000001
20 #define DSI0_CTRL_CTRL0_CLR 0xfffffffe
21 #define DSI0_CTRL_CTRL0_MSB 0
22 #define DSI0_CTRL_CTRL0_LSB 0
23 #define DSI0_CMD_PKTC HW_REGISTER_RW( 0x7e209004 )
24 #define DSI0_CMD_PKTC_MASK 0xffffffff
25 #define DSI0_CMD_PKTC_WIDTH 32
26 #define DSI0_CMD_PKTC_RESET 0000000000
27 #define DSI0_CMD_PKTH HW_REGISTER_RW( 0x7e209008 )
28 #define DSI0_CMD_PKTH_MASK 0xffffffff
29 #define DSI0_CMD_PKTH_WIDTH 32
30 #define DSI0_CMD_PKTH_RESET 0000000000
31 #define DSI0_RX1_PKTH HW_REGISTER_RO( 0x7e20900c )
32 #define DSI0_RX1_PKTH_MASK 0xffffffff
33 #define DSI0_RX1_PKTH_WIDTH 32
34 #define DSI0_RX2_PKTH HW_REGISTER_RO( 0x7e209010 )
35 #define DSI0_RX2_PKTH_MASK 0xffffffff
36 #define DSI0_RX2_PKTH_WIDTH 32
37 #define DSI0_CMD_DATAF HW_REGISTER_RW( 0x7e209014 )
38 #define DSI0_CMD_DATAF_MASK 0x000000ff
39 #define DSI0_CMD_DATAF_WIDTH 8
40 #define DSI0_DISP0_CTR HW_REGISTER_RW( 0x7e209018 )
41 #define DSI0_DISP0_CTR_MASK 0xffffffff
42 #define DSI0_DISP0_CTR_WIDTH 32
43 #define DSI0_DISP0_CTR_RESET 0000000000
44 #define DSI0_DISP1_CTR HW_REGISTER_RW( 0x7e20901c )
45 #define DSI0_DISP1_CTR_MASK 0xffffffff
46 #define DSI0_DISP1_CTR_WIDTH 32
47 #define DSI0_DISP1_CTR_RESET 0000000000
48 #define DSI0_PIX_FIFO HW_REGISTER_RW( 0x7e209020 )
49 #define DSI0_PIX_FIFO_MASK 0xffffffff
50 #define DSI0_PIX_FIFO_WIDTH 32
51 #define DSI0_INT_STAT HW_REGISTER_RW( 0x7e209024 )
52 #define DSI0_INT_STAT_MASK 0xffffffff
53 #define DSI0_INT_STAT_WIDTH 32
54 #define DSI0_INT_EN HW_REGISTER_RW( 0x7e209028 )
55 #define DSI0_INT_EN_MASK 0x0fffffff
56 #define DSI0_INT_EN_WIDTH 28
57 #define DSI0_INT_EN_RESET 0000000000
58 #define DSI0_STAT HW_REGISTER_RW( 0x7e20902c )
59 #define DSI0_STAT_MASK 0xffffffff
60 #define DSI0_STAT_WIDTH 32
61 #define DSI0_HSTX_TO_C HW_REGISTER_RW( 0x7e209030 )
62 #define DSI0_HSTX_TO_C_MASK 0x00ffffff
63 #define DSI0_HSTX_TO_C_WIDTH 24
64 #define DSI0_HSTX_TO_C_RESET 0000000000
65 #define DSI0_LPRX_TO_C HW_REGISTER_RW( 0x7e209034 )
66 #define DSI0_LPRX_TO_C_MASK 0xffffffff
67 #define DSI0_LPRX_TO_C_WIDTH 32
68 #define DSI0_LPRX_TO_C_RESET 0000000000
69 #define DSI0_TA_TO_CNT HW_REGISTER_RW( 0x7e209038 )
70 #define DSI0_TA_TO_CNT_MASK 0xffffffff
71 #define DSI0_TA_TO_CNT_WIDTH 32
72 #define DSI0_TA_TO_CNT_RESET 0000000000
73 #define DSI0_PR_TO_CNT HW_REGISTER_RW( 0x7e20903c )
74 #define DSI0_PR_TO_CNT_MASK 0xffffffff
75 #define DSI0_PR_TO_CNT_WIDTH 32
76 #define DSI0_PR_TO_CNT_RESET 0000000000
77 #define DSI0_PHYC HW_REGISTER_RW( 0x7e209040 )
78 #define DSI0_PHYC_MASK 0x0003f777
79 #define DSI0_PHYC_WIDTH 18
80 #define DSI0_PHYC_RESET 0000000000
81 #define DSI0_PHYC_dsi_esc_lpdt_BITS 17:12
82 #define DSI0_PHYC_dsi_esc_lpdt_SET 0x0003f000
83 #define DSI0_PHYC_dsi_esc_lpdt_CLR 0xfffc0fff
84 #define DSI0_PHYC_dsi_esc_lpdt_MSB 17
85 #define DSI0_PHYC_dsi_esc_lpdt_LSB 12
86 #define DSI0_PHYC_txhsclk_cont_sync_BITS 10:10
87 #define DSI0_PHYC_txhsclk_cont_sync_SET 0x00000400
88 #define DSI0_PHYC_txhsclk_cont_sync_CLR 0xfffffbff
89 #define DSI0_PHYC_txhsclk_cont_sync_MSB 10
90 #define DSI0_PHYC_txhsclk_cont_sync_LSB 10
91 #define DSI0_PHYC_txulps_clk_sync_BITS 9:9
92 #define DSI0_PHYC_txulps_clk_sync_SET 0x00000200
93 #define DSI0_PHYC_txulps_clk_sync_CLR 0xfffffdff
94 #define DSI0_PHYC_txulps_clk_sync_MSB 9
95 #define DSI0_PHYC_txulps_clk_sync_LSB 9
96 #define DSI0_PHYC_clane_hsen_sync_BITS 8:8
97 #define DSI0_PHYC_clane_hsen_sync_SET 0x00000100
98 #define DSI0_PHYC_clane_hsen_sync_CLR 0xfffffeff
99 #define DSI0_PHYC_clane_hsen_sync_MSB 8
100 #define DSI0_PHYC_clane_hsen_sync_LSB 8
101 #define DSI0_PHYC_txulpshs_1_sync_BITS 6:6
102 #define DSI0_PHYC_txulpshs_1_sync_SET 0x00000040
103 #define DSI0_PHYC_txulpshs_1_sync_CLR 0xffffffbf
104 #define DSI0_PHYC_txulpshs_1_sync_MSB 6
105 #define DSI0_PHYC_txulpshs_1_sync_LSB 6
106 #define DSI0_PHYC_dlane_hsen_1_sync_BITS 5:5
107 #define DSI0_PHYC_dlane_hsen_1_sync_SET 0x00000020
108 #define DSI0_PHYC_dlane_hsen_1_sync_CLR 0xffffffdf
109 #define DSI0_PHYC_dlane_hsen_1_sync_MSB 5
110 #define DSI0_PHYC_dlane_hsen_1_sync_LSB 5
111 #define DSI0_PHYC_unused_BITS 4:4
112 #define DSI0_PHYC_unused_SET 0x00000010
113 #define DSI0_PHYC_unused_CLR 0xffffffef
114 #define DSI0_PHYC_unused_MSB 4
115 #define DSI0_PHYC_unused_LSB 4
116 #define DSI0_PHYC_forcehsstop_sync_BITS 2:2
117 #define DSI0_PHYC_forcehsstop_sync_SET 0x00000004
118 #define DSI0_PHYC_forcehsstop_sync_CLR 0xfffffffb
119 #define DSI0_PHYC_forcehsstop_sync_MSB 2
120 #define DSI0_PHYC_forcehsstop_sync_LSB 2
121 #define DSI0_PHYC_txulpshs_0_sync_BITS 1:1
122 #define DSI0_PHYC_txulpshs_0_sync_SET 0x00000002
123 #define DSI0_PHYC_txulpshs_0_sync_CLR 0xfffffffd
124 #define DSI0_PHYC_txulpshs_0_sync_MSB 1
125 #define DSI0_PHYC_txulpshs_0_sync_LSB 1
126 #define DSI0_PHYC_dlane_hsen_0_sync_BITS 0:0
127 #define DSI0_PHYC_dlane_hsen_0_sync_SET 0x00000001
128 #define DSI0_PHYC_dlane_hsen_0_sync_CLR 0xfffffffe
129 #define DSI0_PHYC_dlane_hsen_0_sync_MSB 0
130 #define DSI0_PHYC_dlane_hsen_0_sync_LSB 0
131 #define DSI0_HS_CLT0 HW_REGISTER_RW( 0x7e209044 )
132 #define DSI0_HS_CLT0_MASK 0xfffffffc
133 #define DSI0_HS_CLT0_WIDTH 32
134 #define DSI0_HS_CLT0_RESET 0000000000
135 #define DSI0_HS_CLT1 HW_REGISTER_RW( 0x7e209048 )
136 #define DSI0_HS_CLT1_MASK 0x000003fc
137 #define DSI0_HS_CLT1_WIDTH 10
138 #define DSI0_HS_CLT1_RESET 0000000000
139 #define DSI0_HS_CLT2 HW_REGISTER_RW( 0x7e20904c )
140 #define DSI0_HS_CLT2_MASK 0x000003fc
141 #define DSI0_HS_CLT2_WIDTH 10
142 #define DSI0_HS_CLT2_RESET 0000000000
143 #define DSI0_HS_DLT3 HW_REGISTER_RW( 0x7e209050 )
144 #define DSI0_HS_DLT3_MASK 0x000003fc
145 #define DSI0_HS_DLT3_WIDTH 10
146 #define DSI0_HS_DLT3_RESET 0000000000
147 #define DSI0_HS_DLT4 HW_REGISTER_RW( 0x7e209054 )
148 #define DSI0_HS_DLT4_MASK 0x000003fc
149 #define DSI0_HS_DLT4_WIDTH 10
150 #define DSI0_HS_DLT4_RESET 0000000000
151 #define DSI0_HS_DLT5 HW_REGISTER_RW( 0x7e209058 )
152 #define DSI0_HS_DLT5_MASK 0x000003fc
153 #define DSI0_HS_DLT5_WIDTH 10
154 #define DSI0_HS_DLT5_RESET 0000000000
155 #define DSI0_LP_DLT6 HW_REGISTER_RW( 0x7e20905c )
156 #define DSI0_LP_DLT6_MASK 0x000003fc
157 #define DSI0_LP_DLT6_WIDTH 10
158 #define DSI0_LP_DLT6_RESET 0000000000
159 #define DSI0_LP_DLT7 HW_REGISTER_RW( 0x7e209060 )
160 #define DSI0_LP_DLT7_MASK 0x000003fc
161 #define DSI0_LP_DLT7_WIDTH 10
162 #define DSI0_LP_DLT7_RESET 0000000000
163 #define DSI0_PHY_AFEC0 HW_REGISTER_RW( 0x7e209064 )
164 #define DSI0_PHY_AFEC0_MASK 0x000000ff
165 #define DSI0_PHY_AFEC0_WIDTH 8
166 #define DSI0_PHY_AFEC0_RESET 0000000000
167 #define DSI0_PHY_AFEC1 HW_REGISTER_RW( 0x7e209068 )
168 #define DSI0_PHY_AFEC1_MASK 0xffffffff
169 #define DSI0_PHY_AFEC1_WIDTH 32
170 #define DSI0_PHY_AFEC1_RESET 0000000000
171 #define DSI0_TST_SEL HW_REGISTER_RW( 0x7e20906c )
172 #define DSI0_TST_SEL_MASK 0x000000ff
173 #define DSI0_TST_SEL_WIDTH 8
174 #define DSI0_TST_SEL_RESET 0000000000
175 #define DSI0_TST_MON HW_REGISTER_RW( 0x7e209070 )
176 #define DSI0_TST_MON_MASK 0x000000ff
177 #define DSI0_TST_MON_WIDTH 8
178 #define DSI0_TST_MON_RESET 0000000000
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