a326f50d1e9cefcf761c90b99d65cc6bef1ef62e
[rpi-open-firmware.git] / bcm2708_chip / dsi4.h
1 // This file was generated by the create_regs script
2 #define DSI1_BASE 0x7e700000
3 #define DSI1_APB_ID 0x64736934
4 #define DSI1_CTRL HW_REGISTER_RW( 0x7e700000 )
5 #define DSI1_CTRL_MASK 0xffffffff
6 #define DSI1_CTRL_WIDTH 32
7 #define DSI1_CTRL_RESET 0000000000
8 #define DSI1_TXPKT1_C HW_REGISTER_RW( 0x7e700004 )
9 #define DSI1_TXPKT1_C_MASK 0xffffffff
10 #define DSI1_TXPKT1_C_WIDTH 32
11 #define DSI1_TXPKT1_C_RESET 0000000000
12 #define DSI1_TXPKT1_H HW_REGISTER_RW( 0x7e700008 )
13 #define DSI1_TXPKT1_H_MASK 0xffffffff
14 #define DSI1_TXPKT1_H_WIDTH 32
15 #define DSI1_TXPKT1_H_RESET 0000000000
16 #define DSI1_TXPKT2_C HW_REGISTER_RW( 0x7e70000c )
17 #define DSI1_TXPKT2_C_MASK 0xffffffff
18 #define DSI1_TXPKT2_C_WIDTH 32
19 #define DSI1_TXPKT2_C_RESET 0000000000
20 #define DSI1_TXPKT2_H HW_REGISTER_RW( 0x7e700010 )
21 #define DSI1_TXPKT2_H_MASK 0xffffffff
22 #define DSI1_TXPKT2_H_WIDTH 32
23 #define DSI1_TXPKT2_H_RESET 0000000000
24 #define DSI1_RXPKT1_H HW_REGISTER_RO( 0x7e700014 )
25 #define DSI1_RXPKT1_H_MASK 0xffffffff
26 #define DSI1_RXPKT1_H_WIDTH 32
27 #define DSI1_RXPKT2_H HW_REGISTER_RO( 0x7e700018 )
28 #define DSI1_RXPKT2_H_MASK 0xffffffff
29 #define DSI1_RXPKT2_H_WIDTH 32
30 #define DSI1_TXPKT_CMD_FIFO HW_REGISTER_RW( 0x7e70001c )
31 #define DSI1_TXPKT_CMD_FIFO_MASK 0x000000ff
32 #define DSI1_TXPKT_CMD_FIFO_WIDTH 8
33 #define DSI1_TXPKT_PIXD_FIFO HW_REGISTER_RW( 0x7e700020 )
34 #define DSI1_TXPKT_PIXD_FIFO_MASK 0xffffffff
35 #define DSI1_TXPKT_PIXD_FIFO_WIDTH 32
36 #define DSI1_TXPKT_PIXD_FIFO_RESET 0000000000
37 #define DSI1_RXPKT_FIFO HW_REGISTER_RW( 0x7e700024 )
38 #define DSI1_RXPKT_FIFO_MASK 0xffffffff
39 #define DSI1_RXPKT_FIFO_WIDTH 32
40 #define DSI1_RXPKT_FIFO_RESET 0000000000
41 #define DSI1_DISP0_CTRL HW_REGISTER_RW( 0x7e700028 )
42 #define DSI1_DISP0_CTRL_MASK 0xffffffff
43 #define DSI1_DISP0_CTRL_WIDTH 32
44 #define DSI1_DISP1_CTRL HW_REGISTER_RW( 0x7e70002c )
45 #define DSI1_DISP1_CTRL_MASK 0xffffffff
46 #define DSI1_DISP1_CTRL_WIDTH 32
47 #define DSI1_INT_STAT HW_REGISTER_RW( 0x7e700030 )
48 #define DSI1_INT_STAT_MASK 0xffffffff
49 #define DSI1_INT_STAT_WIDTH 32
50 #define DSI1_INT_EN HW_REGISTER_RW( 0x7e700034 )
51 #define DSI1_INT_EN_MASK 0x0fffffff
52 #define DSI1_INT_EN_WIDTH 28
53 #define DSI1_INT_EN_RESET 0000000000
54 #define DSI1_STAT HW_REGISTER_RW( 0x7e700038 )
55 #define DSI1_STAT_MASK 0xffffffff
56 #define DSI1_STAT_WIDTH 32
57 #define DSI1_HSTX_TO_CNT HW_REGISTER_RW( 0x7e70003c )
58 #define DSI1_HSTX_TO_CNT_MASK 0x00ffffff
59 #define DSI1_HSTX_TO_CNT_WIDTH 24
60 #define DSI1_HSTX_TO_CNT_RESET 0000000000
61 #define DSI1_LPRX_TO_CNT HW_REGISTER_RW( 0x7e700040 )
62 #define DSI1_LPRX_TO_CNT_MASK 0xffffffff
63 #define DSI1_LPRX_TO_CNT_WIDTH 32
64 #define DSI1_LPRX_TO_CNT_RESET 0000000000
65 #define DSI1_TA_TO_CNT HW_REGISTER_RW( 0x7e700044 )
66 #define DSI1_TA_TO_CNT_MASK 0xffffffff
67 #define DSI1_TA_TO_CNT_WIDTH 32
68 #define DSI1_TA_TO_CNT_RESET 0000000000
69 #define DSI1_PR_TO_CNT HW_REGISTER_RW( 0x7e700048 )
70 #define DSI1_PR_TO_CNT_MASK 0xffffffff
71 #define DSI1_PR_TO_CNT_WIDTH 32
72 #define DSI1_PR_TO_CNT_RESET 0000000000
73 #define DSI1_PHYC HW_REGISTER_RW( 0x7e70004c )
74 #define DSI1_PHYC_MASK 0xffffffff
75 #define DSI1_PHYC_WIDTH 32
76 #define DSI1_PHYC_RESET 0000000000
77 #define DSI1_HS_CLT0 HW_REGISTER_RW( 0x7e700050 )
78 #define DSI1_HS_CLT0_MASK 0xffffffff
79 #define DSI1_HS_CLT0_WIDTH 32
80 #define DSI1_HS_CLT0_RESET 0000000000
81 #define DSI1_HS_CLT1 HW_REGISTER_RW( 0x7e700054 )
82 #define DSI1_HS_CLT1_MASK 0xffffffff
83 #define DSI1_HS_CLT1_WIDTH 32
84 #define DSI1_HS_CLT1_RESET 0000000000
85 #define DSI1_HS_CLT2 HW_REGISTER_RW( 0x7e700058 )
86 #define DSI1_HS_CLT2_MASK 0xffffffff
87 #define DSI1_HS_CLT2_WIDTH 32
88 #define DSI1_HS_CLT2_RESET 0000000000
89 #define DSI1_HS_DLT3 HW_REGISTER_RW( 0x7e70005c )
90 #define DSI1_HS_DLT3_MASK 0xffffffff
91 #define DSI1_HS_DLT3_WIDTH 32
92 #define DSI1_HS_DLT3_RESET 0000000000
93 #define DSI1_HS_DLT4 HW_REGISTER_RW( 0x7e700060 )
94 #define DSI1_HS_DLT4_MASK 0xffffffff
95 #define DSI1_HS_DLT4_WIDTH 32
96 #define DSI1_HS_DLT4_RESET 0000000000
97 #define DSI1_HS_DLT5 HW_REGISTER_RW( 0x7e700064 )
98 #define DSI1_HS_DLT5_MASK 0xffffffff
99 #define DSI1_HS_DLT5_WIDTH 32
100 #define DSI1_HS_DLT5_RESET 0000000000
101 #define DSI1_LP_DLT6 HW_REGISTER_RW( 0x7e700068 )
102 #define DSI1_LP_DLT6_MASK 0xffffffff
103 #define DSI1_LP_DLT6_WIDTH 32
104 #define DSI1_LP_DLT6_RESET 0000000000
105 #define DSI1_LP_DLT7 HW_REGISTER_RW( 0x7e70006c )
106 #define DSI1_LP_DLT7_MASK 0xffffffff
107 #define DSI1_LP_DLT7_WIDTH 32
108 #define DSI1_LP_DLT7_RESET 0000000000
109 #define DSI1_PHY_AFEC0 HW_REGISTER_RW( 0x7e700070 )
110 #define DSI1_PHY_AFEC0_MASK 0xffffffff
111 #define DSI1_PHY_AFEC0_WIDTH 32
112 #define DSI1_PHY_AFEC0_RESET 0000000000
113 #define DSI1_PHY_AFEC1 HW_REGISTER_RW( 0x7e700074 )
114 #define DSI1_PHY_AFEC1_MASK 0xffffffff
115 #define DSI1_PHY_AFEC1_WIDTH 32
116 #define DSI1_PHY_AFEC1_RESET 0000000000
117 #define DSI1_TST_SEL HW_REGISTER_RW( 0x7e700078 )
118 #define DSI1_TST_SEL_MASK 0xffffffff
119 #define DSI1_TST_SEL_WIDTH 32
120 #define DSI1_TST_SEL_RESET 0000000000
121 #define DSI1_TST_MON HW_REGISTER_RW( 0x7e70007c )
122 #define DSI1_TST_MON_MASK 0xffffffff
123 #define DSI1_TST_MON_WIDTH 32
124 #define DSI1_TST_MON_RESET 0000000000
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