54b433684dd009ae64f5bc47c585db5912e1d481
[rpi-open-firmware.git] / bcm2708_chip / emmc.h
1 // This file was generated by the create_regs script
2 #define EMMC_BASE 0x7e300000
3 #define EMMC_ARG2 HW_REGISTER_RW( 0x7e300000 )
4 #define EMMC_ARG2_MASK 0xffffffff
5 #define EMMC_ARG2_WIDTH 32
6 #define EMMC_ARG2_RESET 0000000000
7 #define EMMC_BLKSIZECNT HW_REGISTER_RW( 0x7e300004 )
8 #define EMMC_BLKSIZECNT_MASK 0xffffffff
9 #define EMMC_BLKSIZECNT_WIDTH 32
10 #define EMMC_BLKSIZECNT_RESET 0000000000
11 #define EMMC_BLKSIZECNT_BLKCNT_BITS 31:16
12 #define EMMC_BLKSIZECNT_BLKCNT_SET 0xffff0000
13 #define EMMC_BLKSIZECNT_BLKCNT_CLR 0x0000ffff
14 #define EMMC_BLKSIZECNT_BLKCNT_MSB 31
15 #define EMMC_BLKSIZECNT_BLKCNT_LSB 16
16 #define EMMC_BLKSIZECNT_BLKSIZE_MS1_BITS 15:15
17 #define EMMC_BLKSIZECNT_BLKSIZE_MS1_SET 0x00008000
18 #define EMMC_BLKSIZECNT_BLKSIZE_MS1_CLR 0xffff7fff
19 #define EMMC_BLKSIZECNT_BLKSIZE_MS1_MSB 15
20 #define EMMC_BLKSIZECNT_BLKSIZE_MS1_LSB 15
21 #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_BITS 14:12
22 #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_SET 0x00007000
23 #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_CLR 0xffff8fff
24 #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_MSB 14
25 #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_LSB 12
26 #define EMMC_BLKSIZECNT_BLKSIZE_BITS 11:0
27 #define EMMC_BLKSIZECNT_BLKSIZE_SET 0x00000fff
28 #define EMMC_BLKSIZECNT_BLKSIZE_CLR 0xfffff000
29 #define EMMC_BLKSIZECNT_BLKSIZE_MSB 11
30 #define EMMC_BLKSIZECNT_BLKSIZE_LSB 0
31 #define EMMC_ARG1 HW_REGISTER_RW( 0x7e300008 )
32 #define EMMC_ARG1_MASK 0xffffffff
33 #define EMMC_ARG1_WIDTH 32
34 #define EMMC_ARG1_RESET 0000000000
35 #define EMMC_CMDTM HW_REGISTER_RW( 0x7e30000c )
36 #define EMMC_CMDTM_MASK 0x3ffb003f
37 #define EMMC_CMDTM_WIDTH 30
38 #define EMMC_CMDTM_RESET 0000000000
39 #define EMMC_CMDTM_CMD_INDEX_BITS 29:24
40 #define EMMC_CMDTM_CMD_INDEX_SET 0x3f000000
41 #define EMMC_CMDTM_CMD_INDEX_CLR 0xc0ffffff
42 #define EMMC_CMDTM_CMD_INDEX_MSB 29
43 #define EMMC_CMDTM_CMD_INDEX_LSB 24
44 #define EMMC_CMDTM_CMD_TYPE_BITS 23:22
45 #define EMMC_CMDTM_CMD_TYPE_SET 0x00c00000
46 #define EMMC_CMDTM_CMD_TYPE_CLR 0xff3fffff
47 #define EMMC_CMDTM_CMD_TYPE_MSB 23
48 #define EMMC_CMDTM_CMD_TYPE_LSB 22
49 #define EMMC_CMDTM_CMD_ISDATA_BITS 21:21
50 #define EMMC_CMDTM_CMD_ISDATA_SET 0x00200000
51 #define EMMC_CMDTM_CMD_ISDATA_CLR 0xffdfffff
52 #define EMMC_CMDTM_CMD_ISDATA_MSB 21
53 #define EMMC_CMDTM_CMD_ISDATA_LSB 21
54 #define EMMC_CMDTM_CMD_IXCHK_EN_BITS 20:20
55 #define EMMC_CMDTM_CMD_IXCHK_EN_SET 0x00100000
56 #define EMMC_CMDTM_CMD_IXCHK_EN_CLR 0xffefffff
57 #define EMMC_CMDTM_CMD_IXCHK_EN_MSB 20
58 #define EMMC_CMDTM_CMD_IXCHK_EN_LSB 20
59 #define EMMC_CMDTM_CMD_CRCCHK_EN_BITS 19:19
60 #define EMMC_CMDTM_CMD_CRCCHK_EN_SET 0x00080000
61 #define EMMC_CMDTM_CMD_CRCCHK_EN_CLR 0xfff7ffff
62 #define EMMC_CMDTM_CMD_CRCCHK_EN_MSB 19
63 #define EMMC_CMDTM_CMD_CRCCHK_EN_LSB 19
64 #define EMMC_CMDTM_CMD_RSPNS_TYPE_BITS 17:16
65 #define EMMC_CMDTM_CMD_RSPNS_TYPE_SET 0x00030000
66 #define EMMC_CMDTM_CMD_RSPNS_TYPE_CLR 0xfffcffff
67 #define EMMC_CMDTM_CMD_RSPNS_TYPE_MSB 17
68 #define EMMC_CMDTM_CMD_RSPNS_TYPE_LSB 16
69 #define EMMC_CMDTM_TM_MULTI_BLOCK_BITS 5:5
70 #define EMMC_CMDTM_TM_MULTI_BLOCK_SET 0x00000020
71 #define EMMC_CMDTM_TM_MULTI_BLOCK_CLR 0xffffffdf
72 #define EMMC_CMDTM_TM_MULTI_BLOCK_MSB 5
73 #define EMMC_CMDTM_TM_MULTI_BLOCK_LSB 5
74 #define EMMC_CMDTM_TM_DAT_DIR_BITS 4:4
75 #define EMMC_CMDTM_TM_DAT_DIR_SET 0x00000010
76 #define EMMC_CMDTM_TM_DAT_DIR_CLR 0xffffffef
77 #define EMMC_CMDTM_TM_DAT_DIR_MSB 4
78 #define EMMC_CMDTM_TM_DAT_DIR_LSB 4
79 #define EMMC_CMDTM_TM_AUTO_CMD_EN_BITS 3:2
80 #define EMMC_CMDTM_TM_AUTO_CMD_EN_SET 0x0000000c
81 #define EMMC_CMDTM_TM_AUTO_CMD_EN_CLR 0xfffffff3
82 #define EMMC_CMDTM_TM_AUTO_CMD_EN_MSB 3
83 #define EMMC_CMDTM_TM_AUTO_CMD_EN_LSB 2
84 #define EMMC_CMDTM_TM_BLKCNT_EN_BITS 1:1
85 #define EMMC_CMDTM_TM_BLKCNT_EN_SET 0x00000002
86 #define EMMC_CMDTM_TM_BLKCNT_EN_CLR 0xfffffffd
87 #define EMMC_CMDTM_TM_BLKCNT_EN_MSB 1
88 #define EMMC_CMDTM_TM_BLKCNT_EN_LSB 1
89 #define EMMC_CMDTM_TM_DMA_EN_BITS 0:0
90 #define EMMC_CMDTM_TM_DMA_EN_SET 0x00000001
91 #define EMMC_CMDTM_TM_DMA_EN_CLR 0xfffffffe
92 #define EMMC_CMDTM_TM_DMA_EN_MSB 0
93 #define EMMC_CMDTM_TM_DMA_EN_LSB 0
94 #define EMMC_RESP0 HW_REGISTER_RW( 0x7e300010 )
95 #define EMMC_RESP0_MASK 0xffffffff
96 #define EMMC_RESP0_WIDTH 32
97 #define EMMC_RESP0_RESET 0000000000
98 #define EMMC_RESP1 HW_REGISTER_RW( 0x7e300014 )
99 #define EMMC_RESP1_MASK 0xffffffff
100 #define EMMC_RESP1_WIDTH 32
101 #define EMMC_RESP1_RESET 0000000000
102 #define EMMC_RESP2 HW_REGISTER_RW( 0x7e300018 )
103 #define EMMC_RESP2_MASK 0xffffffff
104 #define EMMC_RESP2_WIDTH 32
105 #define EMMC_RESP2_RESET 0000000000
106 #define EMMC_RESP3 HW_REGISTER_RW( 0x7e30001c )
107 #define EMMC_RESP3_MASK 0xffffffff
108 #define EMMC_RESP3_WIDTH 32
109 #define EMMC_RESP3_RESET 0000000000
110 #define EMMC_DATA HW_REGISTER_RW( 0x7e300020 )
111 #define EMMC_DATA_MASK 0xffffffff
112 #define EMMC_DATA_WIDTH 32
113 #define EMMC_DATA_RESET 0000000000
114 #define EMMC_STATUS HW_REGISTER_RW( 0x7e300024 )
115 #define EMMC_STATUS_MASK 0x1fff0f0f
116 #define EMMC_STATUS_WIDTH 29
117 #define EMMC_STATUS_RESET 0x1ff00000
118 #define EMMC_STATUS_DAT_LEVEL1_BITS 28:25
119 #define EMMC_STATUS_DAT_LEVEL1_SET 0x1e000000
120 #define EMMC_STATUS_DAT_LEVEL1_CLR 0xe1ffffff
121 #define EMMC_STATUS_DAT_LEVEL1_MSB 28
122 #define EMMC_STATUS_DAT_LEVEL1_LSB 25
123 #define EMMC_STATUS_CMD_LEVEL_BITS 24:24
124 #define EMMC_STATUS_CMD_LEVEL_SET 0x01000000
125 #define EMMC_STATUS_CMD_LEVEL_CLR 0xfeffffff
126 #define EMMC_STATUS_CMD_LEVEL_MSB 24
127 #define EMMC_STATUS_CMD_LEVEL_LSB 24
128 #define EMMC_STATUS_DAT_LEVEL0_BITS 23:20
129 #define EMMC_STATUS_DAT_LEVEL0_SET 0x00f00000
130 #define EMMC_STATUS_DAT_LEVEL0_CLR 0xff0fffff
131 #define EMMC_STATUS_DAT_LEVEL0_MSB 23
132 #define EMMC_STATUS_DAT_LEVEL0_LSB 20
133 #define EMMC_STATUS_WRT_PROTECT_BITS 19:19
134 #define EMMC_STATUS_WRT_PROTECT_SET 0x00080000
135 #define EMMC_STATUS_WRT_PROTECT_CLR 0xfff7ffff
136 #define EMMC_STATUS_WRT_PROTECT_MSB 19
137 #define EMMC_STATUS_WRT_PROTECT_LSB 19
138 #define EMMC_STATUS_CARD_DETECT_BITS 18:18
139 #define EMMC_STATUS_CARD_DETECT_SET 0x00040000
140 #define EMMC_STATUS_CARD_DETECT_CLR 0xfffbffff
141 #define EMMC_STATUS_CARD_DETECT_MSB 18
142 #define EMMC_STATUS_CARD_DETECT_LSB 18
143 #define EMMC_STATUS_CARD_STABLE_BITS 17:17
144 #define EMMC_STATUS_CARD_STABLE_SET 0x00020000
145 #define EMMC_STATUS_CARD_STABLE_CLR 0xfffdffff
146 #define EMMC_STATUS_CARD_STABLE_MSB 17
147 #define EMMC_STATUS_CARD_STABLE_LSB 17
148 #define EMMC_STATUS_CARD_INSERT_BITS 16:16
149 #define EMMC_STATUS_CARD_INSERT_SET 0x00010000
150 #define EMMC_STATUS_CARD_INSERT_CLR 0xfffeffff
151 #define EMMC_STATUS_CARD_INSERT_MSB 16
152 #define EMMC_STATUS_CARD_INSERT_LSB 16
153 #define EMMC_STATUS_NEW_READ_DATA_BITS 11:11
154 #define EMMC_STATUS_NEW_READ_DATA_SET 0x00000800
155 #define EMMC_STATUS_NEW_READ_DATA_CLR 0xfffff7ff
156 #define EMMC_STATUS_NEW_READ_DATA_MSB 11
157 #define EMMC_STATUS_NEW_READ_DATA_LSB 11
158 #define EMMC_STATUS_NEW_WRITE_DATA_BITS 10:10
159 #define EMMC_STATUS_NEW_WRITE_DATA_SET 0x00000400
160 #define EMMC_STATUS_NEW_WRITE_DATA_CLR 0xfffffbff
161 #define EMMC_STATUS_NEW_WRITE_DATA_MSB 10
162 #define EMMC_STATUS_NEW_WRITE_DATA_LSB 10
163 #define EMMC_STATUS_READ_TRANSFER_BITS 9:9
164 #define EMMC_STATUS_READ_TRANSFER_SET 0x00000200
165 #define EMMC_STATUS_READ_TRANSFER_CLR 0xfffffdff
166 #define EMMC_STATUS_READ_TRANSFER_MSB 9
167 #define EMMC_STATUS_READ_TRANSFER_LSB 9
168 #define EMMC_STATUS_WRITE_TRANSFER_BITS 8:8
169 #define EMMC_STATUS_WRITE_TRANSFER_SET 0x00000100
170 #define EMMC_STATUS_WRITE_TRANSFER_CLR 0xfffffeff
171 #define EMMC_STATUS_WRITE_TRANSFER_MSB 8
172 #define EMMC_STATUS_WRITE_TRANSFER_LSB 8
173 #define EMMC_STATUS_RETUNING_REQ_BITS 3:3
174 #define EMMC_STATUS_RETUNING_REQ_SET 0x00000008
175 #define EMMC_STATUS_RETUNING_REQ_CLR 0xfffffff7
176 #define EMMC_STATUS_RETUNING_REQ_MSB 3
177 #define EMMC_STATUS_RETUNING_REQ_LSB 3
178 #define EMMC_STATUS_DAT_ACTIVE_BITS 2:2
179 #define EMMC_STATUS_DAT_ACTIVE_SET 0x00000004
180 #define EMMC_STATUS_DAT_ACTIVE_CLR 0xfffffffb
181 #define EMMC_STATUS_DAT_ACTIVE_MSB 2
182 #define EMMC_STATUS_DAT_ACTIVE_LSB 2
183 #define EMMC_STATUS_DAT_INHIBIT_BITS 1:1
184 #define EMMC_STATUS_DAT_INHIBIT_SET 0x00000002
185 #define EMMC_STATUS_DAT_INHIBIT_CLR 0xfffffffd
186 #define EMMC_STATUS_DAT_INHIBIT_MSB 1
187 #define EMMC_STATUS_DAT_INHIBIT_LSB 1
188 #define EMMC_STATUS_CMD_INHIBIT_BITS 0:0
189 #define EMMC_STATUS_CMD_INHIBIT_SET 0x00000001
190 #define EMMC_STATUS_CMD_INHIBIT_CLR 0xfffffffe
191 #define EMMC_STATUS_CMD_INHIBIT_MSB 0
192 #define EMMC_STATUS_CMD_INHIBIT_LSB 0
193 #define EMMC_CONTROL0 HW_REGISTER_RW( 0x7e300028 )
194 #define EMMC_CONTROL0_MASK 0x07ff1fff
195 #define EMMC_CONTROL0_WIDTH 27
196 #define EMMC_CONTROL0_RESET 0000000000
197 #define EMMC_CONTROL0_WAKE_ONREM_EN_BITS 26:26
198 #define EMMC_CONTROL0_WAKE_ONREM_EN_SET 0x04000000
199 #define EMMC_CONTROL0_WAKE_ONREM_EN_CLR 0xfbffffff
200 #define EMMC_CONTROL0_WAKE_ONREM_EN_MSB 26
201 #define EMMC_CONTROL0_WAKE_ONREM_EN_LSB 26
202 #define EMMC_CONTROL0_WAKE_ONINS_EN_BITS 25:25
203 #define EMMC_CONTROL0_WAKE_ONINS_EN_SET 0x02000000
204 #define EMMC_CONTROL0_WAKE_ONINS_EN_CLR 0xfdffffff
205 #define EMMC_CONTROL0_WAKE_ONINS_EN_MSB 25
206 #define EMMC_CONTROL0_WAKE_ONINS_EN_LSB 25
207 #define EMMC_CONTROL0_WAKE_ONINT_EN_BITS 24:24
208 #define EMMC_CONTROL0_WAKE_ONINT_EN_SET 0x01000000
209 #define EMMC_CONTROL0_WAKE_ONINT_EN_CLR 0xfeffffff
210 #define EMMC_CONTROL0_WAKE_ONINT_EN_MSB 24
211 #define EMMC_CONTROL0_WAKE_ONINT_EN_LSB 24
212 #define EMMC_CONTROL0_ALT_BOOT_EN_BITS 22:22
213 #define EMMC_CONTROL0_ALT_BOOT_EN_SET 0x00400000
214 #define EMMC_CONTROL0_ALT_BOOT_EN_CLR 0xffbfffff
215 #define EMMC_CONTROL0_ALT_BOOT_EN_MSB 22
216 #define EMMC_CONTROL0_ALT_BOOT_EN_LSB 22
217 #define EMMC_CONTROL0_BOOT_EN_BITS 21:21
218 #define EMMC_CONTROL0_BOOT_EN_SET 0x00200000
219 #define EMMC_CONTROL0_BOOT_EN_CLR 0xffdfffff
220 #define EMMC_CONTROL0_BOOT_EN_MSB 21
221 #define EMMC_CONTROL0_BOOT_EN_LSB 21
222 #define EMMC_CONTROL0_SPI_MODE_BITS 20:20
223 #define EMMC_CONTROL0_SPI_MODE_SET 0x00100000
224 #define EMMC_CONTROL0_SPI_MODE_CLR 0xffefffff
225 #define EMMC_CONTROL0_SPI_MODE_MSB 20
226 #define EMMC_CONTROL0_SPI_MODE_LSB 20
227 #define EMMC_CONTROL0_GAP_IEN_BITS 19:19
228 #define EMMC_CONTROL0_GAP_IEN_SET 0x00080000
229 #define EMMC_CONTROL0_GAP_IEN_CLR 0xfff7ffff
230 #define EMMC_CONTROL0_GAP_IEN_MSB 19
231 #define EMMC_CONTROL0_GAP_IEN_LSB 19
232 #define EMMC_CONTROL0_READWAIT_EN_BITS 18:18
233 #define EMMC_CONTROL0_READWAIT_EN_SET 0x00040000
234 #define EMMC_CONTROL0_READWAIT_EN_CLR 0xfffbffff
235 #define EMMC_CONTROL0_READWAIT_EN_MSB 18
236 #define EMMC_CONTROL0_READWAIT_EN_LSB 18
237 #define EMMC_CONTROL0_GAP_RESTART_BITS 17:17
238 #define EMMC_CONTROL0_GAP_RESTART_SET 0x00020000
239 #define EMMC_CONTROL0_GAP_RESTART_CLR 0xfffdffff
240 #define EMMC_CONTROL0_GAP_RESTART_MSB 17
241 #define EMMC_CONTROL0_GAP_RESTART_LSB 17
242 #define EMMC_CONTROL0_GAP_STOP_BITS 16:16
243 #define EMMC_CONTROL0_GAP_STOP_SET 0x00010000
244 #define EMMC_CONTROL0_GAP_STOP_CLR 0xfffeffff
245 #define EMMC_CONTROL0_GAP_STOP_MSB 16
246 #define EMMC_CONTROL0_GAP_STOP_LSB 16
247 #define EMMC_CONTROL0_PWCTL_HWRST_BITS 12:12
248 #define EMMC_CONTROL0_PWCTL_HWRST_SET 0x00001000
249 #define EMMC_CONTROL0_PWCTL_HWRST_CLR 0xffffefff
250 #define EMMC_CONTROL0_PWCTL_HWRST_MSB 12
251 #define EMMC_CONTROL0_PWCTL_HWRST_LSB 12
252 #define EMMC_CONTROL0_PWCTL_SDVOLTS_BITS 11:9
253 #define EMMC_CONTROL0_PWCTL_SDVOLTS_SET 0x00000e00
254 #define EMMC_CONTROL0_PWCTL_SDVOLTS_CLR 0xfffff1ff
255 #define EMMC_CONTROL0_PWCTL_SDVOLTS_MSB 11
256 #define EMMC_CONTROL0_PWCTL_SDVOLTS_LSB 9
257 #define EMMC_CONTROL0_PWCTL_ON_BITS 8:8
258 #define EMMC_CONTROL0_PWCTL_ON_SET 0x00000100
259 #define EMMC_CONTROL0_PWCTL_ON_CLR 0xfffffeff
260 #define EMMC_CONTROL0_PWCTL_ON_MSB 8
261 #define EMMC_CONTROL0_PWCTL_ON_LSB 8
262 #define EMMC_CONTROL0_HCTL_CRDDET_S_BITS 7:7
263 #define EMMC_CONTROL0_HCTL_CRDDET_S_SET 0x00000080
264 #define EMMC_CONTROL0_HCTL_CRDDET_S_CLR 0xffffff7f
265 #define EMMC_CONTROL0_HCTL_CRDDET_S_MSB 7
266 #define EMMC_CONTROL0_HCTL_CRDDET_S_LSB 7
267 #define EMMC_CONTROL0_HCTL_CRDDET_BITS 6:6
268 #define EMMC_CONTROL0_HCTL_CRDDET_SET 0x00000040
269 #define EMMC_CONTROL0_HCTL_CRDDET_CLR 0xffffffbf
270 #define EMMC_CONTROL0_HCTL_CRDDET_MSB 6
271 #define EMMC_CONTROL0_HCTL_CRDDET_LSB 6
272 #define EMMC_CONTROL0_HCTL_8BIT_BITS 5:5
273 #define EMMC_CONTROL0_HCTL_8BIT_SET 0x00000020
274 #define EMMC_CONTROL0_HCTL_8BIT_CLR 0xffffffdf
275 #define EMMC_CONTROL0_HCTL_8BIT_MSB 5
276 #define EMMC_CONTROL0_HCTL_8BIT_LSB 5
277 #define EMMC_CONTROL0_HCTL_DMA_BITS 4:3
278 #define EMMC_CONTROL0_HCTL_DMA_SET 0x00000018
279 #define EMMC_CONTROL0_HCTL_DMA_CLR 0xffffffe7
280 #define EMMC_CONTROL0_HCTL_DMA_MSB 4
281 #define EMMC_CONTROL0_HCTL_DMA_LSB 3
282 #define EMMC_CONTROL0_HCTL_HS_EN_BITS 2:2
283 #define EMMC_CONTROL0_HCTL_HS_EN_SET 0x00000004
284 #define EMMC_CONTROL0_HCTL_HS_EN_CLR 0xfffffffb
285 #define EMMC_CONTROL0_HCTL_HS_EN_MSB 2
286 #define EMMC_CONTROL0_HCTL_HS_EN_LSB 2
287 #define EMMC_CONTROL0_HCTL_DWIDTH_BITS 1:1
288 #define EMMC_CONTROL0_HCTL_DWIDTH_SET 0x00000002
289 #define EMMC_CONTROL0_HCTL_DWIDTH_CLR 0xfffffffd
290 #define EMMC_CONTROL0_HCTL_DWIDTH_MSB 1
291 #define EMMC_CONTROL0_HCTL_DWIDTH_LSB 1
292 #define EMMC_CONTROL0_HCTL_LED_BITS 0:0
293 #define EMMC_CONTROL0_HCTL_LED_SET 0x00000001
294 #define EMMC_CONTROL0_HCTL_LED_CLR 0xfffffffe
295 #define EMMC_CONTROL0_HCTL_LED_MSB 0
296 #define EMMC_CONTROL0_HCTL_LED_LSB 0
297 #define EMMC_CONTROL1 HW_REGISTER_RW( 0x7e30002c )
298 #define EMMC_CONTROL1_MASK 0x070fffe7
299 #define EMMC_CONTROL1_WIDTH 27
300 #define EMMC_CONTROL1_RESET 0000000000
301 #define EMMC_CONTROL1_SRST_DATA_BITS 26:26
302 #define EMMC_CONTROL1_SRST_DATA_SET 0x04000000
303 #define EMMC_CONTROL1_SRST_DATA_CLR 0xfbffffff
304 #define EMMC_CONTROL1_SRST_DATA_MSB 26
305 #define EMMC_CONTROL1_SRST_DATA_LSB 26
306 #define EMMC_CONTROL1_SRST_CMD_BITS 25:25
307 #define EMMC_CONTROL1_SRST_CMD_SET 0x02000000
308 #define EMMC_CONTROL1_SRST_CMD_CLR 0xfdffffff
309 #define EMMC_CONTROL1_SRST_CMD_MSB 25
310 #define EMMC_CONTROL1_SRST_CMD_LSB 25
311 #define EMMC_CONTROL1_SRST_HC_BITS 24:24
312 #define EMMC_CONTROL1_SRST_HC_SET 0x01000000
313 #define EMMC_CONTROL1_SRST_HC_CLR 0xfeffffff
314 #define EMMC_CONTROL1_SRST_HC_MSB 24
315 #define EMMC_CONTROL1_SRST_HC_LSB 24
316 #define EMMC_CONTROL1_DATA_TOUNIT_BITS 19:16
317 #define EMMC_CONTROL1_DATA_TOUNIT_SET 0x000f0000
318 #define EMMC_CONTROL1_DATA_TOUNIT_CLR 0xfff0ffff
319 #define EMMC_CONTROL1_DATA_TOUNIT_MSB 19
320 #define EMMC_CONTROL1_DATA_TOUNIT_LSB 16
321 #define EMMC_CONTROL1_CLK_FREQ8_BITS 15:8
322 #define EMMC_CONTROL1_CLK_FREQ8_SET 0x0000ff00
323 #define EMMC_CONTROL1_CLK_FREQ8_CLR 0xffff00ff
324 #define EMMC_CONTROL1_CLK_FREQ8_MSB 15
325 #define EMMC_CONTROL1_CLK_FREQ8_LSB 8
326 #define EMMC_CONTROL1_CLK_FREQ_MS2_BITS 7:6
327 #define EMMC_CONTROL1_CLK_FREQ_MS2_SET 0x000000c0
328 #define EMMC_CONTROL1_CLK_FREQ_MS2_CLR 0xffffff3f
329 #define EMMC_CONTROL1_CLK_FREQ_MS2_MSB 7
330 #define EMMC_CONTROL1_CLK_FREQ_MS2_LSB 6
331 #define EMMC_CONTROL1_CLK_GENSEL_BITS 5:5
332 #define EMMC_CONTROL1_CLK_GENSEL_SET 0x00000020
333 #define EMMC_CONTROL1_CLK_GENSEL_CLR 0xffffffdf
334 #define EMMC_CONTROL1_CLK_GENSEL_MSB 5
335 #define EMMC_CONTROL1_CLK_GENSEL_LSB 5
336 #define EMMC_CONTROL1_CLK_EN_BITS 2:2
337 #define EMMC_CONTROL1_CLK_EN_SET 0x00000004
338 #define EMMC_CONTROL1_CLK_EN_CLR 0xfffffffb
339 #define EMMC_CONTROL1_CLK_EN_MSB 2
340 #define EMMC_CONTROL1_CLK_EN_LSB 2
341 #define EMMC_CONTROL1_CLK_STABLE_BITS 1:1
342 #define EMMC_CONTROL1_CLK_STABLE_SET 0x00000002
343 #define EMMC_CONTROL1_CLK_STABLE_CLR 0xfffffffd
344 #define EMMC_CONTROL1_CLK_STABLE_MSB 1
345 #define EMMC_CONTROL1_CLK_STABLE_LSB 1
346 #define EMMC_CONTROL1_CLK_INTLEN_BITS 0:0
347 #define EMMC_CONTROL1_CLK_INTLEN_SET 0x00000001
348 #define EMMC_CONTROL1_CLK_INTLEN_CLR 0xfffffffe
349 #define EMMC_CONTROL1_CLK_INTLEN_MSB 0
350 #define EMMC_CONTROL1_CLK_INTLEN_LSB 0
351 #define EMMC_INTERRUPT HW_REGISTER_RW( 0x7e300030 )
352 #define EMMC_INTERRUPT_MASK 0xffffffff
353 #define EMMC_INTERRUPT_WIDTH 32
354 #define EMMC_INTERRUPT_RESET 0000000000
355 #define EMMC_INTERRUPT_OEM_ERR_BITS 31:30
356 #define EMMC_INTERRUPT_OEM_ERR_SET 0xc0000000
357 #define EMMC_INTERRUPT_OEM_ERR_CLR 0x3fffffff
358 #define EMMC_INTERRUPT_OEM_ERR_MSB 31
359 #define EMMC_INTERRUPT_OEM_ERR_LSB 30
360 #define EMMC_INTERRUPT_ATA_ERR_BITS 29:29
361 #define EMMC_INTERRUPT_ATA_ERR_SET 0x20000000
362 #define EMMC_INTERRUPT_ATA_ERR_CLR 0xdfffffff
363 #define EMMC_INTERRUPT_ATA_ERR_MSB 29
364 #define EMMC_INTERRUPT_ATA_ERR_LSB 29
365 #define EMMC_INTERRUPT_DMA_ERR_BITS 28:28
366 #define EMMC_INTERRUPT_DMA_ERR_SET 0x10000000
367 #define EMMC_INTERRUPT_DMA_ERR_CLR 0xefffffff
368 #define EMMC_INTERRUPT_DMA_ERR_MSB 28
369 #define EMMC_INTERRUPT_DMA_ERR_LSB 28
370 #define EMMC_INTERRUPT_TUNE_ERR_BITS 26:26
371 #define EMMC_INTERRUPT_TUNE_ERR_SET 0x04000000
372 #define EMMC_INTERRUPT_TUNE_ERR_CLR 0xfbffffff
373 #define EMMC_INTERRUPT_TUNE_ERR_MSB 26
374 #define EMMC_INTERRUPT_TUNE_ERR_LSB 26
375 #define EMMC_INTERRUPT_ADMA_ERR_BITS 25:25
376 #define EMMC_INTERRUPT_ADMA_ERR_SET 0x02000000
377 #define EMMC_INTERRUPT_ADMA_ERR_CLR 0xfdffffff
378 #define EMMC_INTERRUPT_ADMA_ERR_MSB 25
379 #define EMMC_INTERRUPT_ADMA_ERR_LSB 25
380 #define EMMC_INTERRUPT_ACMD_ERR_BITS 24:24
381 #define EMMC_INTERRUPT_ACMD_ERR_SET 0x01000000
382 #define EMMC_INTERRUPT_ACMD_ERR_CLR 0xfeffffff
383 #define EMMC_INTERRUPT_ACMD_ERR_MSB 24
384 #define EMMC_INTERRUPT_ACMD_ERR_LSB 24
385 #define EMMC_INTERRUPT_SDOFF_ERR_BITS 23:23
386 #define EMMC_INTERRUPT_SDOFF_ERR_SET 0x00800000
387 #define EMMC_INTERRUPT_SDOFF_ERR_CLR 0xff7fffff
388 #define EMMC_INTERRUPT_SDOFF_ERR_MSB 23
389 #define EMMC_INTERRUPT_SDOFF_ERR_LSB 23
390 #define EMMC_INTERRUPT_DEND_ERR_BITS 22:22
391 #define EMMC_INTERRUPT_DEND_ERR_SET 0x00400000
392 #define EMMC_INTERRUPT_DEND_ERR_CLR 0xffbfffff
393 #define EMMC_INTERRUPT_DEND_ERR_MSB 22
394 #define EMMC_INTERRUPT_DEND_ERR_LSB 22
395 #define EMMC_INTERRUPT_DCRC_ERR_BITS 21:21
396 #define EMMC_INTERRUPT_DCRC_ERR_SET 0x00200000
397 #define EMMC_INTERRUPT_DCRC_ERR_CLR 0xffdfffff
398 #define EMMC_INTERRUPT_DCRC_ERR_MSB 21
399 #define EMMC_INTERRUPT_DCRC_ERR_LSB 21
400 #define EMMC_INTERRUPT_DTO_ERR_BITS 20:20
401 #define EMMC_INTERRUPT_DTO_ERR_SET 0x00100000
402 #define EMMC_INTERRUPT_DTO_ERR_CLR 0xffefffff
403 #define EMMC_INTERRUPT_DTO_ERR_MSB 20
404 #define EMMC_INTERRUPT_DTO_ERR_LSB 20
405 #define EMMC_INTERRUPT_CBAD_ERR_BITS 19:19
406 #define EMMC_INTERRUPT_CBAD_ERR_SET 0x00080000
407 #define EMMC_INTERRUPT_CBAD_ERR_CLR 0xfff7ffff
408 #define EMMC_INTERRUPT_CBAD_ERR_MSB 19
409 #define EMMC_INTERRUPT_CBAD_ERR_LSB 19
410 #define EMMC_INTERRUPT_CEND_ERR_BITS 18:18
411 #define EMMC_INTERRUPT_CEND_ERR_SET 0x00040000
412 #define EMMC_INTERRUPT_CEND_ERR_CLR 0xfffbffff
413 #define EMMC_INTERRUPT_CEND_ERR_MSB 18
414 #define EMMC_INTERRUPT_CEND_ERR_LSB 18
415 #define EMMC_INTERRUPT_CCRC_ERR_BITS 17:17
416 #define EMMC_INTERRUPT_CCRC_ERR_SET 0x00020000
417 #define EMMC_INTERRUPT_CCRC_ERR_CLR 0xfffdffff
418 #define EMMC_INTERRUPT_CCRC_ERR_MSB 17
419 #define EMMC_INTERRUPT_CCRC_ERR_LSB 17
420 #define EMMC_INTERRUPT_CTO_ERR_BITS 16:16
421 #define EMMC_INTERRUPT_CTO_ERR_SET 0x00010000
422 #define EMMC_INTERRUPT_CTO_ERR_CLR 0xfffeffff
423 #define EMMC_INTERRUPT_CTO_ERR_MSB 16
424 #define EMMC_INTERRUPT_CTO_ERR_LSB 16
425 #define EMMC_INTERRUPT_ERR_BITS 15:15
426 #define EMMC_INTERRUPT_ERR_SET 0x00008000
427 #define EMMC_INTERRUPT_ERR_CLR 0xffff7fff
428 #define EMMC_INTERRUPT_ERR_MSB 15
429 #define EMMC_INTERRUPT_ERR_LSB 15
430 #define EMMC_INTERRUPT_ENDBOOT_BITS 14:14
431 #define EMMC_INTERRUPT_ENDBOOT_SET 0x00004000
432 #define EMMC_INTERRUPT_ENDBOOT_CLR 0xffffbfff
433 #define EMMC_INTERRUPT_ENDBOOT_MSB 14
434 #define EMMC_INTERRUPT_ENDBOOT_LSB 14
435 #define EMMC_INTERRUPT_BOOTACK_BITS 13:13
436 #define EMMC_INTERRUPT_BOOTACK_SET 0x00002000
437 #define EMMC_INTERRUPT_BOOTACK_CLR 0xffffdfff
438 #define EMMC_INTERRUPT_BOOTACK_MSB 13
439 #define EMMC_INTERRUPT_BOOTACK_LSB 13
440 #define EMMC_INTERRUPT_RETUNE_BITS 12:12
441 #define EMMC_INTERRUPT_RETUNE_SET 0x00001000
442 #define EMMC_INTERRUPT_RETUNE_CLR 0xffffefff
443 #define EMMC_INTERRUPT_RETUNE_MSB 12
444 #define EMMC_INTERRUPT_RETUNE_LSB 12
445 #define EMMC_INTERRUPT_INT_C_BITS 11:11
446 #define EMMC_INTERRUPT_INT_C_SET 0x00000800
447 #define EMMC_INTERRUPT_INT_C_CLR 0xfffff7ff
448 #define EMMC_INTERRUPT_INT_C_MSB 11
449 #define EMMC_INTERRUPT_INT_C_LSB 11
450 #define EMMC_INTERRUPT_INT_B_BITS 10:10
451 #define EMMC_INTERRUPT_INT_B_SET 0x00000400
452 #define EMMC_INTERRUPT_INT_B_CLR 0xfffffbff
453 #define EMMC_INTERRUPT_INT_B_MSB 10
454 #define EMMC_INTERRUPT_INT_B_LSB 10
455 #define EMMC_INTERRUPT_INT_A_BITS 9:9
456 #define EMMC_INTERRUPT_INT_A_SET 0x00000200
457 #define EMMC_INTERRUPT_INT_A_CLR 0xfffffdff
458 #define EMMC_INTERRUPT_INT_A_MSB 9
459 #define EMMC_INTERRUPT_INT_A_LSB 9
460 #define EMMC_INTERRUPT_CARD_BITS 8:8
461 #define EMMC_INTERRUPT_CARD_SET 0x00000100
462 #define EMMC_INTERRUPT_CARD_CLR 0xfffffeff
463 #define EMMC_INTERRUPT_CARD_MSB 8
464 #define EMMC_INTERRUPT_CARD_LSB 8
465 #define EMMC_INTERRUPT_CARD_OUT_BITS 7:7
466 #define EMMC_INTERRUPT_CARD_OUT_SET 0x00000080
467 #define EMMC_INTERRUPT_CARD_OUT_CLR 0xffffff7f
468 #define EMMC_INTERRUPT_CARD_OUT_MSB 7
469 #define EMMC_INTERRUPT_CARD_OUT_LSB 7
470 #define EMMC_INTERRUPT_CARD_IN_BITS 6:6
471 #define EMMC_INTERRUPT_CARD_IN_SET 0x00000040
472 #define EMMC_INTERRUPT_CARD_IN_CLR 0xffffffbf
473 #define EMMC_INTERRUPT_CARD_IN_MSB 6
474 #define EMMC_INTERRUPT_CARD_IN_LSB 6
475 #define EMMC_INTERRUPT_READ_RDY_BITS 5:5
476 #define EMMC_INTERRUPT_READ_RDY_SET 0x00000020
477 #define EMMC_INTERRUPT_READ_RDY_CLR 0xffffffdf
478 #define EMMC_INTERRUPT_READ_RDY_MSB 5
479 #define EMMC_INTERRUPT_READ_RDY_LSB 5
480 #define EMMC_INTERRUPT_WRITE_RDY_BITS 4:4
481 #define EMMC_INTERRUPT_WRITE_RDY_SET 0x00000010
482 #define EMMC_INTERRUPT_WRITE_RDY_CLR 0xffffffef
483 #define EMMC_INTERRUPT_WRITE_RDY_MSB 4
484 #define EMMC_INTERRUPT_WRITE_RDY_LSB 4
485 #define EMMC_INTERRUPT_DMA_BITS 3:3
486 #define EMMC_INTERRUPT_DMA_SET 0x00000008
487 #define EMMC_INTERRUPT_DMA_CLR 0xfffffff7
488 #define EMMC_INTERRUPT_DMA_MSB 3
489 #define EMMC_INTERRUPT_DMA_LSB 3
490 #define EMMC_INTERRUPT_BLOCK_GAP_BITS 2:2
491 #define EMMC_INTERRUPT_BLOCK_GAP_SET 0x00000004
492 #define EMMC_INTERRUPT_BLOCK_GAP_CLR 0xfffffffb
493 #define EMMC_INTERRUPT_BLOCK_GAP_MSB 2
494 #define EMMC_INTERRUPT_BLOCK_GAP_LSB 2
495 #define EMMC_INTERRUPT_DATA_DONE_BITS 1:1
496 #define EMMC_INTERRUPT_DATA_DONE_SET 0x00000002
497 #define EMMC_INTERRUPT_DATA_DONE_CLR 0xfffffffd
498 #define EMMC_INTERRUPT_DATA_DONE_MSB 1
499 #define EMMC_INTERRUPT_DATA_DONE_LSB 1
500 #define EMMC_INTERRUPT_CMD_DONE_BITS 0:0
501 #define EMMC_INTERRUPT_CMD_DONE_SET 0x00000001
502 #define EMMC_INTERRUPT_CMD_DONE_CLR 0xfffffffe
503 #define EMMC_INTERRUPT_CMD_DONE_MSB 0
504 #define EMMC_INTERRUPT_CMD_DONE_LSB 0
505 #define EMMC_IRPT_MASK HW_REGISTER_RW( 0x7e300034 )
506 #define EMMC_IRPT_MASK_MASK 0xffffffff
507 #define EMMC_IRPT_MASK_WIDTH 32
508 #define EMMC_IRPT_MASK_RESET 0000000000
509 #define EMMC_IRPT_MASK_OEM_ERR_BITS 31:30
510 #define EMMC_IRPT_MASK_OEM_ERR_SET 0xc0000000
511 #define EMMC_IRPT_MASK_OEM_ERR_CLR 0x3fffffff
512 #define EMMC_IRPT_MASK_OEM_ERR_MSB 31
513 #define EMMC_IRPT_MASK_OEM_ERR_LSB 30
514 #define EMMC_IRPT_MASK_ATA_ERR_BITS 29:29
515 #define EMMC_IRPT_MASK_ATA_ERR_SET 0x20000000
516 #define EMMC_IRPT_MASK_ATA_ERR_CLR 0xdfffffff
517 #define EMMC_IRPT_MASK_ATA_ERR_MSB 29
518 #define EMMC_IRPT_MASK_ATA_ERR_LSB 29
519 #define EMMC_IRPT_MASK_DMA_ERR_BITS 28:28
520 #define EMMC_IRPT_MASK_DMA_ERR_SET 0x10000000
521 #define EMMC_IRPT_MASK_DMA_ERR_CLR 0xefffffff
522 #define EMMC_IRPT_MASK_DMA_ERR_MSB 28
523 #define EMMC_IRPT_MASK_DMA_ERR_LSB 28
524 #define EMMC_IRPT_MASK_ADMA_ERR_BITS 25:25
525 #define EMMC_IRPT_MASK_ADMA_ERR_SET 0x02000000
526 #define EMMC_IRPT_MASK_ADMA_ERR_CLR 0xfdffffff
527 #define EMMC_IRPT_MASK_ADMA_ERR_MSB 25
528 #define EMMC_IRPT_MASK_ADMA_ERR_LSB 25
529 #define EMMC_IRPT_MASK_ACMD_ERR_BITS 24:24
530 #define EMMC_IRPT_MASK_ACMD_ERR_SET 0x01000000
531 #define EMMC_IRPT_MASK_ACMD_ERR_CLR 0xfeffffff
532 #define EMMC_IRPT_MASK_ACMD_ERR_MSB 24
533 #define EMMC_IRPT_MASK_ACMD_ERR_LSB 24
534 #define EMMC_IRPT_MASK_SDOFF_ERR_BITS 23:23
535 #define EMMC_IRPT_MASK_SDOFF_ERR_SET 0x00800000
536 #define EMMC_IRPT_MASK_SDOFF_ERR_CLR 0xff7fffff
537 #define EMMC_IRPT_MASK_SDOFF_ERR_MSB 23
538 #define EMMC_IRPT_MASK_SDOFF_ERR_LSB 23
539 #define EMMC_IRPT_MASK_DEND_ERR_BITS 22:22
540 #define EMMC_IRPT_MASK_DEND_ERR_SET 0x00400000
541 #define EMMC_IRPT_MASK_DEND_ERR_CLR 0xffbfffff
542 #define EMMC_IRPT_MASK_DEND_ERR_MSB 22
543 #define EMMC_IRPT_MASK_DEND_ERR_LSB 22
544 #define EMMC_IRPT_MASK_DCRC_ERR_BITS 21:21
545 #define EMMC_IRPT_MASK_DCRC_ERR_SET 0x00200000
546 #define EMMC_IRPT_MASK_DCRC_ERR_CLR 0xffdfffff
547 #define EMMC_IRPT_MASK_DCRC_ERR_MSB 21
548 #define EMMC_IRPT_MASK_DCRC_ERR_LSB 21
549 #define EMMC_IRPT_MASK_DTO_ERR_BITS 20:20
550 #define EMMC_IRPT_MASK_DTO_ERR_SET 0x00100000
551 #define EMMC_IRPT_MASK_DTO_ERR_CLR 0xffefffff
552 #define EMMC_IRPT_MASK_DTO_ERR_MSB 20
553 #define EMMC_IRPT_MASK_DTO_ERR_LSB 20
554 #define EMMC_IRPT_MASK_CBAD_ERR_BITS 19:19
555 #define EMMC_IRPT_MASK_CBAD_ERR_SET 0x00080000
556 #define EMMC_IRPT_MASK_CBAD_ERR_CLR 0xfff7ffff
557 #define EMMC_IRPT_MASK_CBAD_ERR_MSB 19
558 #define EMMC_IRPT_MASK_CBAD_ERR_LSB 19
559 #define EMMC_IRPT_MASK_CEND_ERR_BITS 18:18
560 #define EMMC_IRPT_MASK_CEND_ERR_SET 0x00040000
561 #define EMMC_IRPT_MASK_CEND_ERR_CLR 0xfffbffff
562 #define EMMC_IRPT_MASK_CEND_ERR_MSB 18
563 #define EMMC_IRPT_MASK_CEND_ERR_LSB 18
564 #define EMMC_IRPT_MASK_CCRC_ERR_BITS 17:17
565 #define EMMC_IRPT_MASK_CCRC_ERR_SET 0x00020000
566 #define EMMC_IRPT_MASK_CCRC_ERR_CLR 0xfffdffff
567 #define EMMC_IRPT_MASK_CCRC_ERR_MSB 17
568 #define EMMC_IRPT_MASK_CCRC_ERR_LSB 17
569 #define EMMC_IRPT_MASK_CTO_ERR_BITS 16:16
570 #define EMMC_IRPT_MASK_CTO_ERR_SET 0x00010000
571 #define EMMC_IRPT_MASK_CTO_ERR_CLR 0xfffeffff
572 #define EMMC_IRPT_MASK_CTO_ERR_MSB 16
573 #define EMMC_IRPT_MASK_CTO_ERR_LSB 16
574 #define EMMC_IRPT_MASK_ENDBOOT_BITS 14:14
575 #define EMMC_IRPT_MASK_ENDBOOT_SET 0x00004000
576 #define EMMC_IRPT_MASK_ENDBOOT_CLR 0xffffbfff
577 #define EMMC_IRPT_MASK_ENDBOOT_MSB 14
578 #define EMMC_IRPT_MASK_ENDBOOT_LSB 14
579 #define EMMC_IRPT_MASK_BOOTACK_BITS 13:13
580 #define EMMC_IRPT_MASK_BOOTACK_SET 0x00002000
581 #define EMMC_IRPT_MASK_BOOTACK_CLR 0xffffdfff
582 #define EMMC_IRPT_MASK_BOOTACK_MSB 13
583 #define EMMC_IRPT_MASK_BOOTACK_LSB 13
584 #define EMMC_IRPT_MASK_RETUNE_BITS 12:12
585 #define EMMC_IRPT_MASK_RETUNE_SET 0x00001000
586 #define EMMC_IRPT_MASK_RETUNE_CLR 0xffffefff
587 #define EMMC_IRPT_MASK_RETUNE_MSB 12
588 #define EMMC_IRPT_MASK_RETUNE_LSB 12
589 #define EMMC_IRPT_MASK_INT_C_BITS 11:11
590 #define EMMC_IRPT_MASK_INT_C_SET 0x00000800
591 #define EMMC_IRPT_MASK_INT_C_CLR 0xfffff7ff
592 #define EMMC_IRPT_MASK_INT_C_MSB 11
593 #define EMMC_IRPT_MASK_INT_C_LSB 11
594 #define EMMC_IRPT_MASK_INT_B_BITS 10:10
595 #define EMMC_IRPT_MASK_INT_B_SET 0x00000400
596 #define EMMC_IRPT_MASK_INT_B_CLR 0xfffffbff
597 #define EMMC_IRPT_MASK_INT_B_MSB 10
598 #define EMMC_IRPT_MASK_INT_B_LSB 10
599 #define EMMC_IRPT_MASK_INT_A_BITS 9:9
600 #define EMMC_IRPT_MASK_INT_A_SET 0x00000200
601 #define EMMC_IRPT_MASK_INT_A_CLR 0xfffffdff
602 #define EMMC_IRPT_MASK_INT_A_MSB 9
603 #define EMMC_IRPT_MASK_INT_A_LSB 9
604 #define EMMC_IRPT_MASK_CARD_BITS 8:8
605 #define EMMC_IRPT_MASK_CARD_SET 0x00000100
606 #define EMMC_IRPT_MASK_CARD_CLR 0xfffffeff
607 #define EMMC_IRPT_MASK_CARD_MSB 8
608 #define EMMC_IRPT_MASK_CARD_LSB 8
609 #define EMMC_IRPT_MASK_CARD_OUT_BITS 7:7
610 #define EMMC_IRPT_MASK_CARD_OUT_SET 0x00000080
611 #define EMMC_IRPT_MASK_CARD_OUT_CLR 0xffffff7f
612 #define EMMC_IRPT_MASK_CARD_OUT_MSB 7
613 #define EMMC_IRPT_MASK_CARD_OUT_LSB 7
614 #define EMMC_IRPT_MASK_CARD_IN_BITS 6:6
615 #define EMMC_IRPT_MASK_CARD_IN_SET 0x00000040
616 #define EMMC_IRPT_MASK_CARD_IN_CLR 0xffffffbf
617 #define EMMC_IRPT_MASK_CARD_IN_MSB 6
618 #define EMMC_IRPT_MASK_CARD_IN_LSB 6
619 #define EMMC_IRPT_MASK_READ_RDY_BITS 5:5
620 #define EMMC_IRPT_MASK_READ_RDY_SET 0x00000020
621 #define EMMC_IRPT_MASK_READ_RDY_CLR 0xffffffdf
622 #define EMMC_IRPT_MASK_READ_RDY_MSB 5
623 #define EMMC_IRPT_MASK_READ_RDY_LSB 5
624 #define EMMC_IRPT_MASK_WRITE_RDY_BITS 4:4
625 #define EMMC_IRPT_MASK_WRITE_RDY_SET 0x00000010
626 #define EMMC_IRPT_MASK_WRITE_RDY_CLR 0xffffffef
627 #define EMMC_IRPT_MASK_WRITE_RDY_MSB 4
628 #define EMMC_IRPT_MASK_WRITE_RDY_LSB 4
629 #define EMMC_IRPT_MASK_DMA_BITS 3:3
630 #define EMMC_IRPT_MASK_DMA_SET 0x00000008
631 #define EMMC_IRPT_MASK_DMA_CLR 0xfffffff7
632 #define EMMC_IRPT_MASK_DMA_MSB 3
633 #define EMMC_IRPT_MASK_DMA_LSB 3
634 #define EMMC_IRPT_MASK_BLOCK_GAP_BITS 2:2
635 #define EMMC_IRPT_MASK_BLOCK_GAP_SET 0x00000004
636 #define EMMC_IRPT_MASK_BLOCK_GAP_CLR 0xfffffffb
637 #define EMMC_IRPT_MASK_BLOCK_GAP_MSB 2
638 #define EMMC_IRPT_MASK_BLOCK_GAP_LSB 2
639 #define EMMC_IRPT_MASK_DATA_DONE_BITS 1:1
640 #define EMMC_IRPT_MASK_DATA_DONE_SET 0x00000002
641 #define EMMC_IRPT_MASK_DATA_DONE_CLR 0xfffffffd
642 #define EMMC_IRPT_MASK_DATA_DONE_MSB 1
643 #define EMMC_IRPT_MASK_DATA_DONE_LSB 1
644 #define EMMC_IRPT_MASK_CMD_DONE_BITS 0:0
645 #define EMMC_IRPT_MASK_CMD_DONE_SET 0x00000001
646 #define EMMC_IRPT_MASK_CMD_DONE_CLR 0xfffffffe
647 #define EMMC_IRPT_MASK_CMD_DONE_MSB 0
648 #define EMMC_IRPT_MASK_CMD_DONE_LSB 0
649 #define EMMC_IRPT_EN HW_REGISTER_RW( 0x7e300038 )
650 #define EMMC_IRPT_EN_MASK 0xffffffff
651 #define EMMC_IRPT_EN_WIDTH 32
652 #define EMMC_IRPT_EN_RESET 0000000000
653 #define EMMC_IRPT_EN_OEM_ERR_BITS 31:30
654 #define EMMC_IRPT_EN_OEM_ERR_SET 0xc0000000
655 #define EMMC_IRPT_EN_OEM_ERR_CLR 0x3fffffff
656 #define EMMC_IRPT_EN_OEM_ERR_MSB 31
657 #define EMMC_IRPT_EN_OEM_ERR_LSB 30
658 #define EMMC_IRPT_EN_ATA_ERR_BITS 29:29
659 #define EMMC_IRPT_EN_ATA_ERR_SET 0x20000000
660 #define EMMC_IRPT_EN_ATA_ERR_CLR 0xdfffffff
661 #define EMMC_IRPT_EN_ATA_ERR_MSB 29
662 #define EMMC_IRPT_EN_ATA_ERR_LSB 29
663 #define EMMC_IRPT_EN_DMA_ERR_BITS 28:28
664 #define EMMC_IRPT_EN_DMA_ERR_SET 0x10000000
665 #define EMMC_IRPT_EN_DMA_ERR_CLR 0xefffffff
666 #define EMMC_IRPT_EN_DMA_ERR_MSB 28
667 #define EMMC_IRPT_EN_DMA_ERR_LSB 28
668 #define EMMC_IRPT_EN_TUNE_ERR_BITS 26:26
669 #define EMMC_IRPT_EN_TUNE_ERR_SET 0x04000000
670 #define EMMC_IRPT_EN_TUNE_ERR_CLR 0xfbffffff
671 #define EMMC_IRPT_EN_TUNE_ERR_MSB 26
672 #define EMMC_IRPT_EN_TUNE_ERR_LSB 26
673 #define EMMC_IRPT_EN_ADMA_ERR_BITS 25:25
674 #define EMMC_IRPT_EN_ADMA_ERR_SET 0x02000000
675 #define EMMC_IRPT_EN_ADMA_ERR_CLR 0xfdffffff
676 #define EMMC_IRPT_EN_ADMA_ERR_MSB 25
677 #define EMMC_IRPT_EN_ADMA_ERR_LSB 25
678 #define EMMC_IRPT_EN_ACMD_ERR_BITS 24:24
679 #define EMMC_IRPT_EN_ACMD_ERR_SET 0x01000000
680 #define EMMC_IRPT_EN_ACMD_ERR_CLR 0xfeffffff
681 #define EMMC_IRPT_EN_ACMD_ERR_MSB 24
682 #define EMMC_IRPT_EN_ACMD_ERR_LSB 24
683 #define EMMC_IRPT_EN_SDOFF_ERR_BITS 23:23
684 #define EMMC_IRPT_EN_SDOFF_ERR_SET 0x00800000
685 #define EMMC_IRPT_EN_SDOFF_ERR_CLR 0xff7fffff
686 #define EMMC_IRPT_EN_SDOFF_ERR_MSB 23
687 #define EMMC_IRPT_EN_SDOFF_ERR_LSB 23
688 #define EMMC_IRPT_EN_DEND_ERR_BITS 22:22
689 #define EMMC_IRPT_EN_DEND_ERR_SET 0x00400000
690 #define EMMC_IRPT_EN_DEND_ERR_CLR 0xffbfffff
691 #define EMMC_IRPT_EN_DEND_ERR_MSB 22
692 #define EMMC_IRPT_EN_DEND_ERR_LSB 22
693 #define EMMC_IRPT_EN_DCRC_ERR_BITS 21:21
694 #define EMMC_IRPT_EN_DCRC_ERR_SET 0x00200000
695 #define EMMC_IRPT_EN_DCRC_ERR_CLR 0xffdfffff
696 #define EMMC_IRPT_EN_DCRC_ERR_MSB 21
697 #define EMMC_IRPT_EN_DCRC_ERR_LSB 21
698 #define EMMC_IRPT_EN_DTO_ERR_BITS 20:20
699 #define EMMC_IRPT_EN_DTO_ERR_SET 0x00100000
700 #define EMMC_IRPT_EN_DTO_ERR_CLR 0xffefffff
701 #define EMMC_IRPT_EN_DTO_ERR_MSB 20
702 #define EMMC_IRPT_EN_DTO_ERR_LSB 20
703 #define EMMC_IRPT_EN_CBAD_ERR_BITS 19:19
704 #define EMMC_IRPT_EN_CBAD_ERR_SET 0x00080000
705 #define EMMC_IRPT_EN_CBAD_ERR_CLR 0xfff7ffff
706 #define EMMC_IRPT_EN_CBAD_ERR_MSB 19
707 #define EMMC_IRPT_EN_CBAD_ERR_LSB 19
708 #define EMMC_IRPT_EN_CEND_ERR_BITS 18:18
709 #define EMMC_IRPT_EN_CEND_ERR_SET 0x00040000
710 #define EMMC_IRPT_EN_CEND_ERR_CLR 0xfffbffff
711 #define EMMC_IRPT_EN_CEND_ERR_MSB 18
712 #define EMMC_IRPT_EN_CEND_ERR_LSB 18
713 #define EMMC_IRPT_EN_CCRC_ERR_BITS 17:17
714 #define EMMC_IRPT_EN_CCRC_ERR_SET 0x00020000
715 #define EMMC_IRPT_EN_CCRC_ERR_CLR 0xfffdffff
716 #define EMMC_IRPT_EN_CCRC_ERR_MSB 17
717 #define EMMC_IRPT_EN_CCRC_ERR_LSB 17
718 #define EMMC_IRPT_EN_CTO_ERR_BITS 16:16
719 #define EMMC_IRPT_EN_CTO_ERR_SET 0x00010000
720 #define EMMC_IRPT_EN_CTO_ERR_CLR 0xfffeffff
721 #define EMMC_IRPT_EN_CTO_ERR_MSB 16
722 #define EMMC_IRPT_EN_CTO_ERR_LSB 16
723 #define EMMC_IRPT_EN_ENDBOOT_BITS 14:14
724 #define EMMC_IRPT_EN_ENDBOOT_SET 0x00004000
725 #define EMMC_IRPT_EN_ENDBOOT_CLR 0xffffbfff
726 #define EMMC_IRPT_EN_ENDBOOT_MSB 14
727 #define EMMC_IRPT_EN_ENDBOOT_LSB 14
728 #define EMMC_IRPT_EN_BOOTACK_BITS 13:13
729 #define EMMC_IRPT_EN_BOOTACK_SET 0x00002000
730 #define EMMC_IRPT_EN_BOOTACK_CLR 0xffffdfff
731 #define EMMC_IRPT_EN_BOOTACK_MSB 13
732 #define EMMC_IRPT_EN_BOOTACK_LSB 13
733 #define EMMC_IRPT_EN_RETUNE_BITS 12:12
734 #define EMMC_IRPT_EN_RETUNE_SET 0x00001000
735 #define EMMC_IRPT_EN_RETUNE_CLR 0xffffefff
736 #define EMMC_IRPT_EN_RETUNE_MSB 12
737 #define EMMC_IRPT_EN_RETUNE_LSB 12
738 #define EMMC_IRPT_EN_INT_C_BITS 11:11
739 #define EMMC_IRPT_EN_INT_C_SET 0x00000800
740 #define EMMC_IRPT_EN_INT_C_CLR 0xfffff7ff
741 #define EMMC_IRPT_EN_INT_C_MSB 11
742 #define EMMC_IRPT_EN_INT_C_LSB 11
743 #define EMMC_IRPT_EN_INT_B_BITS 10:10
744 #define EMMC_IRPT_EN_INT_B_SET 0x00000400
745 #define EMMC_IRPT_EN_INT_B_CLR 0xfffffbff
746 #define EMMC_IRPT_EN_INT_B_MSB 10
747 #define EMMC_IRPT_EN_INT_B_LSB 10
748 #define EMMC_IRPT_EN_INT_A_BITS 9:9
749 #define EMMC_IRPT_EN_INT_A_SET 0x00000200
750 #define EMMC_IRPT_EN_INT_A_CLR 0xfffffdff
751 #define EMMC_IRPT_EN_INT_A_MSB 9
752 #define EMMC_IRPT_EN_INT_A_LSB 9
753 #define EMMC_IRPT_EN_CARD_BITS 8:8
754 #define EMMC_IRPT_EN_CARD_SET 0x00000100
755 #define EMMC_IRPT_EN_CARD_CLR 0xfffffeff
756 #define EMMC_IRPT_EN_CARD_MSB 8
757 #define EMMC_IRPT_EN_CARD_LSB 8
758 #define EMMC_IRPT_EN_CARD_OUT_BITS 7:7
759 #define EMMC_IRPT_EN_CARD_OUT_SET 0x00000080
760 #define EMMC_IRPT_EN_CARD_OUT_CLR 0xffffff7f
761 #define EMMC_IRPT_EN_CARD_OUT_MSB 7
762 #define EMMC_IRPT_EN_CARD_OUT_LSB 7
763 #define EMMC_IRPT_EN_CARD_IN_BITS 6:6
764 #define EMMC_IRPT_EN_CARD_IN_SET 0x00000040
765 #define EMMC_IRPT_EN_CARD_IN_CLR 0xffffffbf
766 #define EMMC_IRPT_EN_CARD_IN_MSB 6
767 #define EMMC_IRPT_EN_CARD_IN_LSB 6
768 #define EMMC_IRPT_EN_READ_RDY_BITS 5:5
769 #define EMMC_IRPT_EN_READ_RDY_SET 0x00000020
770 #define EMMC_IRPT_EN_READ_RDY_CLR 0xffffffdf
771 #define EMMC_IRPT_EN_READ_RDY_MSB 5
772 #define EMMC_IRPT_EN_READ_RDY_LSB 5
773 #define EMMC_IRPT_EN_WRITE_RDY_BITS 4:4
774 #define EMMC_IRPT_EN_WRITE_RDY_SET 0x00000010
775 #define EMMC_IRPT_EN_WRITE_RDY_CLR 0xffffffef
776 #define EMMC_IRPT_EN_WRITE_RDY_MSB 4
777 #define EMMC_IRPT_EN_WRITE_RDY_LSB 4
778 #define EMMC_IRPT_EN_DMA_BITS 3:3
779 #define EMMC_IRPT_EN_DMA_SET 0x00000008
780 #define EMMC_IRPT_EN_DMA_CLR 0xfffffff7
781 #define EMMC_IRPT_EN_DMA_MSB 3
782 #define EMMC_IRPT_EN_DMA_LSB 3
783 #define EMMC_IRPT_EN_BLOCK_GAP_BITS 2:2
784 #define EMMC_IRPT_EN_BLOCK_GAP_SET 0x00000004
785 #define EMMC_IRPT_EN_BLOCK_GAP_CLR 0xfffffffb
786 #define EMMC_IRPT_EN_BLOCK_GAP_MSB 2
787 #define EMMC_IRPT_EN_BLOCK_GAP_LSB 2
788 #define EMMC_IRPT_EN_DATA_DONE_BITS 1:1
789 #define EMMC_IRPT_EN_DATA_DONE_SET 0x00000002
790 #define EMMC_IRPT_EN_DATA_DONE_CLR 0xfffffffd
791 #define EMMC_IRPT_EN_DATA_DONE_MSB 1
792 #define EMMC_IRPT_EN_DATA_DONE_LSB 1
793 #define EMMC_IRPT_EN_CMD_DONE_BITS 0:0
794 #define EMMC_IRPT_EN_CMD_DONE_SET 0x00000001
795 #define EMMC_IRPT_EN_CMD_DONE_CLR 0xfffffffe
796 #define EMMC_IRPT_EN_CMD_DONE_MSB 0
797 #define EMMC_IRPT_EN_CMD_DONE_LSB 0
798 #define EMMC_CONTROL2 HW_REGISTER_RW( 0x7e30003c )
799 #define EMMC_CONTROL2_MASK 0xc0ff009f
800 #define EMMC_CONTROL2_WIDTH 32
801 #define EMMC_CONTROL2_RESET 0x00080000
802 #define EMMC_CONTROL2_EN_PSV_BITS 31:31
803 #define EMMC_CONTROL2_EN_PSV_SET 0x80000000
804 #define EMMC_CONTROL2_EN_PSV_CLR 0x7fffffff
805 #define EMMC_CONTROL2_EN_PSV_MSB 31
806 #define EMMC_CONTROL2_EN_PSV_LSB 31
807 #define EMMC_CONTROL2_EN_AINT_BITS 30:30
808 #define EMMC_CONTROL2_EN_AINT_SET 0x40000000
809 #define EMMC_CONTROL2_EN_AINT_CLR 0xbfffffff
810 #define EMMC_CONTROL2_EN_AINT_MSB 30
811 #define EMMC_CONTROL2_EN_AINT_LSB 30
812 #define EMMC_CONTROL2_TUNED_BITS 23:23
813 #define EMMC_CONTROL2_TUNED_SET 0x00800000
814 #define EMMC_CONTROL2_TUNED_CLR 0xff7fffff
815 #define EMMC_CONTROL2_TUNED_MSB 23
816 #define EMMC_CONTROL2_TUNED_LSB 23
817 #define EMMC_CONTROL2_TUNEON_BITS 22:22
818 #define EMMC_CONTROL2_TUNEON_SET 0x00400000
819 #define EMMC_CONTROL2_TUNEON_CLR 0xffbfffff
820 #define EMMC_CONTROL2_TUNEON_MSB 22
821 #define EMMC_CONTROL2_TUNEON_LSB 22
822 #define EMMC_CONTROL2_DRVTYPE_BITS 21:20
823 #define EMMC_CONTROL2_DRVTYPE_SET 0x00300000
824 #define EMMC_CONTROL2_DRVTYPE_CLR 0xffcfffff
825 #define EMMC_CONTROL2_DRVTYPE_MSB 21
826 #define EMMC_CONTROL2_DRVTYPE_LSB 20
827 #define EMMC_CONTROL2_SIGTYPE_BITS 19:19
828 #define EMMC_CONTROL2_SIGTYPE_SET 0x00080000
829 #define EMMC_CONTROL2_SIGTYPE_CLR 0xfff7ffff
830 #define EMMC_CONTROL2_SIGTYPE_MSB 19
831 #define EMMC_CONTROL2_SIGTYPE_LSB 19
832 #define EMMC_CONTROL2_UHSMODE_BITS 18:16
833 #define EMMC_CONTROL2_UHSMODE_SET 0x00070000
834 #define EMMC_CONTROL2_UHSMODE_CLR 0xfff8ffff
835 #define EMMC_CONTROL2_UHSMODE_MSB 18
836 #define EMMC_CONTROL2_UHSMODE_LSB 16
837 #define EMMC_CONTROL2_NOTC12_ERR_BITS 7:7
838 #define EMMC_CONTROL2_NOTC12_ERR_SET 0x00000080
839 #define EMMC_CONTROL2_NOTC12_ERR_CLR 0xffffff7f
840 #define EMMC_CONTROL2_NOTC12_ERR_MSB 7
841 #define EMMC_CONTROL2_NOTC12_ERR_LSB 7
842 #define EMMC_CONTROL2_ACBAD_ERR_BITS 4:4
843 #define EMMC_CONTROL2_ACBAD_ERR_SET 0x00000010
844 #define EMMC_CONTROL2_ACBAD_ERR_CLR 0xffffffef
845 #define EMMC_CONTROL2_ACBAD_ERR_MSB 4
846 #define EMMC_CONTROL2_ACBAD_ERR_LSB 4
847 #define EMMC_CONTROL2_ACEND_ERR_BITS 3:3
848 #define EMMC_CONTROL2_ACEND_ERR_SET 0x00000008
849 #define EMMC_CONTROL2_ACEND_ERR_CLR 0xfffffff7
850 #define EMMC_CONTROL2_ACEND_ERR_MSB 3
851 #define EMMC_CONTROL2_ACEND_ERR_LSB 3
852 #define EMMC_CONTROL2_ACCRC_ERR_BITS 2:2
853 #define EMMC_CONTROL2_ACCRC_ERR_SET 0x00000004
854 #define EMMC_CONTROL2_ACCRC_ERR_CLR 0xfffffffb
855 #define EMMC_CONTROL2_ACCRC_ERR_MSB 2
856 #define EMMC_CONTROL2_ACCRC_ERR_LSB 2
857 #define EMMC_CONTROL2_ACTO_ERR_BITS 1:1
858 #define EMMC_CONTROL2_ACTO_ERR_SET 0x00000002
859 #define EMMC_CONTROL2_ACTO_ERR_CLR 0xfffffffd
860 #define EMMC_CONTROL2_ACTO_ERR_MSB 1
861 #define EMMC_CONTROL2_ACTO_ERR_LSB 1
862 #define EMMC_CONTROL2_ACNOX_ERR_BITS 0:0
863 #define EMMC_CONTROL2_ACNOX_ERR_SET 0x00000001
864 #define EMMC_CONTROL2_ACNOX_ERR_CLR 0xfffffffe
865 #define EMMC_CONTROL2_ACNOX_ERR_MSB 0
866 #define EMMC_CONTROL2_ACNOX_ERR_LSB 0
867 #define EMMC_HWCAP0 HW_REGISTER_RW( 0x7e300040 )
868 #define EMMC_HWCAP0_MASK 0xffffffff
869 #define EMMC_HWCAP0_WIDTH 32
870 #define EMMC_HWCAP0_RESET 0000000000
871 #define EMMC_HWCAP0_SLOT_TYPE_BITS 31:30
872 #define EMMC_HWCAP0_SLOT_TYPE_SET 0xc0000000
873 #define EMMC_HWCAP0_SLOT_TYPE_CLR 0x3fffffff
874 #define EMMC_HWCAP0_SLOT_TYPE_MSB 31
875 #define EMMC_HWCAP0_SLOT_TYPE_LSB 30
876 #define EMMC_HWCAP0_AINT_BITS 29:29
877 #define EMMC_HWCAP0_AINT_SET 0x20000000
878 #define EMMC_HWCAP0_AINT_CLR 0xdfffffff
879 #define EMMC_HWCAP0_AINT_MSB 29
880 #define EMMC_HWCAP0_AINT_LSB 29
881 #define EMMC_HWCAP0_BUS64_BITS 28:28
882 #define EMMC_HWCAP0_BUS64_SET 0x10000000
883 #define EMMC_HWCAP0_BUS64_CLR 0xefffffff
884 #define EMMC_HWCAP0_BUS64_MSB 28
885 #define EMMC_HWCAP0_BUS64_LSB 28
886 #define EMMC_HWCAP0_V1_8_BITS 26:26
887 #define EMMC_HWCAP0_V1_8_SET 0x04000000
888 #define EMMC_HWCAP0_V1_8_CLR 0xfbffffff
889 #define EMMC_HWCAP0_V1_8_MSB 26
890 #define EMMC_HWCAP0_V1_8_LSB 26
891 #define EMMC_HWCAP0_V3_0_BITS 25:25
892 #define EMMC_HWCAP0_V3_0_SET 0x02000000
893 #define EMMC_HWCAP0_V3_0_CLR 0xfdffffff
894 #define EMMC_HWCAP0_V3_0_MSB 25
895 #define EMMC_HWCAP0_V3_0_LSB 25
896 #define EMMC_HWCAP0_V3_3_BITS 24:24
897 #define EMMC_HWCAP0_V3_3_SET 0x01000000
898 #define EMMC_HWCAP0_V3_3_CLR 0xfeffffff
899 #define EMMC_HWCAP0_V3_3_MSB 24
900 #define EMMC_HWCAP0_V3_3_LSB 24
901 #define EMMC_HWCAP0_RESUME_BITS 23:23
902 #define EMMC_HWCAP0_RESUME_SET 0x00800000
903 #define EMMC_HWCAP0_RESUME_CLR 0xff7fffff
904 #define EMMC_HWCAP0_RESUME_MSB 23
905 #define EMMC_HWCAP0_RESUME_LSB 23
906 #define EMMC_HWCAP0_SDMA_BITS 22:22
907 #define EMMC_HWCAP0_SDMA_SET 0x00400000
908 #define EMMC_HWCAP0_SDMA_CLR 0xffbfffff
909 #define EMMC_HWCAP0_SDMA_MSB 22
910 #define EMMC_HWCAP0_SDMA_LSB 22
911 #define EMMC_HWCAP0_HS_BITS 21:21
912 #define EMMC_HWCAP0_HS_SET 0x00200000
913 #define EMMC_HWCAP0_HS_CLR 0xffdfffff
914 #define EMMC_HWCAP0_HS_MSB 21
915 #define EMMC_HWCAP0_HS_LSB 21
916 #define EMMC_HWCAP0_ADMA2_BITS 19:19
917 #define EMMC_HWCAP0_ADMA2_SET 0x00080000
918 #define EMMC_HWCAP0_ADMA2_CLR 0xfff7ffff
919 #define EMMC_HWCAP0_ADMA2_MSB 19
920 #define EMMC_HWCAP0_ADMA2_LSB 19
921 #define EMMC_HWCAP0_XMEDBUS_BITS 18:18
922 #define EMMC_HWCAP0_XMEDBUS_SET 0x00040000
923 #define EMMC_HWCAP0_XMEDBUS_CLR 0xfffbffff
924 #define EMMC_HWCAP0_XMEDBUS_MSB 18
925 #define EMMC_HWCAP0_XMEDBUS_LSB 18
926 #define EMMC_HWCAP0_MAXLEN_BITS 17:16
927 #define EMMC_HWCAP0_MAXLEN_SET 0x00030000
928 #define EMMC_HWCAP0_MAXLEN_CLR 0xfffcffff
929 #define EMMC_HWCAP0_MAXLEN_MSB 17
930 #define EMMC_HWCAP0_MAXLEN_LSB 16
931 #define EMMC_HWCAP0_BASEMHZ_BITS 15:8
932 #define EMMC_HWCAP0_BASEMHZ_SET 0x0000ff00
933 #define EMMC_HWCAP0_BASEMHZ_CLR 0xffff00ff
934 #define EMMC_HWCAP0_BASEMHZ_MSB 15
935 #define EMMC_HWCAP0_BASEMHZ_LSB 8
936 #define EMMC_HWCAP0_TCLKUNIT_BITS 7:7
937 #define EMMC_HWCAP0_TCLKUNIT_SET 0x00000080
938 #define EMMC_HWCAP0_TCLKUNIT_CLR 0xffffff7f
939 #define EMMC_HWCAP0_TCLKUNIT_MSB 7
940 #define EMMC_HWCAP0_TCLKUNIT_LSB 7
941 #define EMMC_HWCAP0_TCLKFREQ_BITS 5:0
942 #define EMMC_HWCAP0_TCLKFREQ_SET 0x0000003f
943 #define EMMC_HWCAP0_TCLKFREQ_CLR 0xffffffc0
944 #define EMMC_HWCAP0_TCLKFREQ_MSB 5
945 #define EMMC_HWCAP0_TCLKFREQ_LSB 0
946 #define EMMC_HWCAP1 HW_REGISTER_RW( 0x7e300044 )
947 #define EMMC_HWCAP1_MASK 0x03ffef77
948 #define EMMC_HWCAP1_WIDTH 26
949 #define EMMC_HWCAP1_RESET 0x03000777
950 #define EMMC_HWCAP1_SPI_BLOCKMODE_BITS 25:25
951 #define EMMC_HWCAP1_SPI_BLOCKMODE_SET 0x02000000
952 #define EMMC_HWCAP1_SPI_BLOCKMODE_CLR 0xfdffffff
953 #define EMMC_HWCAP1_SPI_BLOCKMODE_MSB 25
954 #define EMMC_HWCAP1_SPI_BLOCKMODE_LSB 25
955 #define EMMC_HWCAP1_SPI_MODE_BITS 24:24
956 #define EMMC_HWCAP1_SPI_MODE_SET 0x01000000
957 #define EMMC_HWCAP1_SPI_MODE_CLR 0xfeffffff
958 #define EMMC_HWCAP1_SPI_MODE_MSB 24
959 #define EMMC_HWCAP1_SPI_MODE_LSB 24
960 #define EMMC_HWCAP1_MULTIPLIER_BITS 23:16
961 #define EMMC_HWCAP1_MULTIPLIER_SET 0x00ff0000
962 #define EMMC_HWCAP1_MULTIPLIER_CLR 0xff00ffff
963 #define EMMC_HWCAP1_MULTIPLIER_MSB 23
964 #define EMMC_HWCAP1_MULTIPLIER_LSB 16
965 #define EMMC_HWCAP1_DATA_RETUNE_BITS 15:14
966 #define EMMC_HWCAP1_DATA_RETUNE_SET 0x0000c000
967 #define EMMC_HWCAP1_DATA_RETUNE_CLR 0xffff3fff
968 #define EMMC_HWCAP1_DATA_RETUNE_MSB 15
969 #define EMMC_HWCAP1_DATA_RETUNE_LSB 14
970 #define EMMC_HWCAP1_SDR50_TUNE_BITS 13:13
971 #define EMMC_HWCAP1_SDR50_TUNE_SET 0x00002000
972 #define EMMC_HWCAP1_SDR50_TUNE_CLR 0xffffdfff
973 #define EMMC_HWCAP1_SDR50_TUNE_MSB 13
974 #define EMMC_HWCAP1_SDR50_TUNE_LSB 13
975 #define EMMC_HWCAP1_RETUNE_TMR_BITS 11:8
976 #define EMMC_HWCAP1_RETUNE_TMR_SET 0x00000f00
977 #define EMMC_HWCAP1_RETUNE_TMR_CLR 0xfffff0ff
978 #define EMMC_HWCAP1_RETUNE_TMR_MSB 11
979 #define EMMC_HWCAP1_RETUNE_TMR_LSB 8
980 #define EMMC_HWCAP1_DRV18_TYPED_BITS 6:6
981 #define EMMC_HWCAP1_DRV18_TYPED_SET 0x00000040
982 #define EMMC_HWCAP1_DRV18_TYPED_CLR 0xffffffbf
983 #define EMMC_HWCAP1_DRV18_TYPED_MSB 6
984 #define EMMC_HWCAP1_DRV18_TYPED_LSB 6
985 #define EMMC_HWCAP1_DRV18_TYPEC_BITS 5:5
986 #define EMMC_HWCAP1_DRV18_TYPEC_SET 0x00000020
987 #define EMMC_HWCAP1_DRV18_TYPEC_CLR 0xffffffdf
988 #define EMMC_HWCAP1_DRV18_TYPEC_MSB 5
989 #define EMMC_HWCAP1_DRV18_TYPEC_LSB 5
990 #define EMMC_HWCAP1_DRV18_TYPEA_BITS 4:4
991 #define EMMC_HWCAP1_DRV18_TYPEA_SET 0x00000010
992 #define EMMC_HWCAP1_DRV18_TYPEA_CLR 0xffffffef
993 #define EMMC_HWCAP1_DRV18_TYPEA_MSB 4
994 #define EMMC_HWCAP1_DRV18_TYPEA_LSB 4
995 #define EMMC_HWCAP1_DDR50_BITS 2:2
996 #define EMMC_HWCAP1_DDR50_SET 0x00000004
997 #define EMMC_HWCAP1_DDR50_CLR 0xfffffffb
998 #define EMMC_HWCAP1_DDR50_MSB 2
999 #define EMMC_HWCAP1_DDR50_LSB 2
1000 #define EMMC_HWCAP1_SDR104_BITS 1:1
1001 #define EMMC_HWCAP1_SDR104_SET 0x00000002
1002 #define EMMC_HWCAP1_SDR104_CLR 0xfffffffd
1003 #define EMMC_HWCAP1_SDR104_MSB 1
1004 #define EMMC_HWCAP1_SDR104_LSB 1
1005 #define EMMC_HWCAP1_SDR50_BITS 0:0
1006 #define EMMC_HWCAP1_SDR50_SET 0x00000001
1007 #define EMMC_HWCAP1_SDR50_CLR 0xfffffffe
1008 #define EMMC_HWCAP1_SDR50_MSB 0
1009 #define EMMC_HWCAP1_SDR50_LSB 0
1010 #define EMMC_HWMAXAMP0 HW_REGISTER_RW( 0x7e300048 )
1011 #define EMMC_HWMAXAMP0_MASK 0x00ffffff
1012 #define EMMC_HWMAXAMP0_WIDTH 24
1013 #define EMMC_HWMAXAMP0_RESET 0000000000
1014 #define EMMC_HWMAXAMP0_AMP_18V_BITS 23:16
1015 #define EMMC_HWMAXAMP0_AMP_18V_SET 0x00ff0000
1016 #define EMMC_HWMAXAMP0_AMP_18V_CLR 0xff00ffff
1017 #define EMMC_HWMAXAMP0_AMP_18V_MSB 23
1018 #define EMMC_HWMAXAMP0_AMP_18V_LSB 16
1019 #define EMMC_HWMAXAMP0_AMP_30V_BITS 15:8
1020 #define EMMC_HWMAXAMP0_AMP_30V_SET 0x0000ff00
1021 #define EMMC_HWMAXAMP0_AMP_30V_CLR 0xffff00ff
1022 #define EMMC_HWMAXAMP0_AMP_30V_MSB 15
1023 #define EMMC_HWMAXAMP0_AMP_30V_LSB 8
1024 #define EMMC_HWMAXAMP0_AMP_33V_BITS 7:0
1025 #define EMMC_HWMAXAMP0_AMP_33V_SET 0x000000ff
1026 #define EMMC_HWMAXAMP0_AMP_33V_CLR 0xffffff00
1027 #define EMMC_HWMAXAMP0_AMP_33V_MSB 7
1028 #define EMMC_HWMAXAMP0_AMP_33V_LSB 0
1029 #define EMMC_FORCE_IRPT HW_REGISTER_RW( 0x7e300050 )
1030 #define EMMC_FORCE_IRPT_MASK 0xffff00ff
1031 #define EMMC_FORCE_IRPT_WIDTH 32
1032 #define EMMC_FORCE_IRPT_RESET 0x00000001
1033 #define EMMC_FORCE_IRPT_OEM_ERR_BITS 31:30
1034 #define EMMC_FORCE_IRPT_OEM_ERR_SET 0xc0000000
1035 #define EMMC_FORCE_IRPT_OEM_ERR_CLR 0x3fffffff
1036 #define EMMC_FORCE_IRPT_OEM_ERR_MSB 31
1037 #define EMMC_FORCE_IRPT_OEM_ERR_LSB 30
1038 #define EMMC_FORCE_IRPT_ATA_ERR_BITS 29:29
1039 #define EMMC_FORCE_IRPT_ATA_ERR_SET 0x20000000
1040 #define EMMC_FORCE_IRPT_ATA_ERR_CLR 0xdfffffff
1041 #define EMMC_FORCE_IRPT_ATA_ERR_MSB 29
1042 #define EMMC_FORCE_IRPT_ATA_ERR_LSB 29
1043 #define EMMC_FORCE_IRPT_DMA_ERR_BITS 28:28
1044 #define EMMC_FORCE_IRPT_DMA_ERR_SET 0x10000000
1045 #define EMMC_FORCE_IRPT_DMA_ERR_CLR 0xefffffff
1046 #define EMMC_FORCE_IRPT_DMA_ERR_MSB 28
1047 #define EMMC_FORCE_IRPT_DMA_ERR_LSB 28
1048 #define EMMC_FORCE_IRPT_TUNE_ERR_BITS 26:26
1049 #define EMMC_FORCE_IRPT_TUNE_ERR_SET 0x04000000
1050 #define EMMC_FORCE_IRPT_TUNE_ERR_CLR 0xfbffffff
1051 #define EMMC_FORCE_IRPT_TUNE_ERR_MSB 26
1052 #define EMMC_FORCE_IRPT_TUNE_ERR_LSB 26
1053 #define EMMC_FORCE_IRPT_ADMA_ERR_BITS 25:25
1054 #define EMMC_FORCE_IRPT_ADMA_ERR_SET 0x02000000
1055 #define EMMC_FORCE_IRPT_ADMA_ERR_CLR 0xfdffffff
1056 #define EMMC_FORCE_IRPT_ADMA_ERR_MSB 25
1057 #define EMMC_FORCE_IRPT_ADMA_ERR_LSB 25
1058 #define EMMC_FORCE_IRPT_ACMD_ERR_BITS 24:24
1059 #define EMMC_FORCE_IRPT_ACMD_ERR_SET 0x01000000
1060 #define EMMC_FORCE_IRPT_ACMD_ERR_CLR 0xfeffffff
1061 #define EMMC_FORCE_IRPT_ACMD_ERR_MSB 24
1062 #define EMMC_FORCE_IRPT_ACMD_ERR_LSB 24
1063 #define EMMC_FORCE_IRPT_SDOFF_ERR_BITS 23:23
1064 #define EMMC_FORCE_IRPT_SDOFF_ERR_SET 0x00800000
1065 #define EMMC_FORCE_IRPT_SDOFF_ERR_CLR 0xff7fffff
1066 #define EMMC_FORCE_IRPT_SDOFF_ERR_MSB 23
1067 #define EMMC_FORCE_IRPT_SDOFF_ERR_LSB 23
1068 #define EMMC_FORCE_IRPT_DEND_ERR_BITS 22:22
1069 #define EMMC_FORCE_IRPT_DEND_ERR_SET 0x00400000
1070 #define EMMC_FORCE_IRPT_DEND_ERR_CLR 0xffbfffff
1071 #define EMMC_FORCE_IRPT_DEND_ERR_MSB 22
1072 #define EMMC_FORCE_IRPT_DEND_ERR_LSB 22
1073 #define EMMC_FORCE_IRPT_DCRC_ERR_BITS 21:21
1074 #define EMMC_FORCE_IRPT_DCRC_ERR_SET 0x00200000
1075 #define EMMC_FORCE_IRPT_DCRC_ERR_CLR 0xffdfffff
1076 #define EMMC_FORCE_IRPT_DCRC_ERR_MSB 21
1077 #define EMMC_FORCE_IRPT_DCRC_ERR_LSB 21
1078 #define EMMC_FORCE_IRPT_DTO_ERR_BITS 20:20
1079 #define EMMC_FORCE_IRPT_DTO_ERR_SET 0x00100000
1080 #define EMMC_FORCE_IRPT_DTO_ERR_CLR 0xffefffff
1081 #define EMMC_FORCE_IRPT_DTO_ERR_MSB 20
1082 #define EMMC_FORCE_IRPT_DTO_ERR_LSB 20
1083 #define EMMC_FORCE_IRPT_CBAD_ERR_BITS 19:19
1084 #define EMMC_FORCE_IRPT_CBAD_ERR_SET 0x00080000
1085 #define EMMC_FORCE_IRPT_CBAD_ERR_CLR 0xfff7ffff
1086 #define EMMC_FORCE_IRPT_CBAD_ERR_MSB 19
1087 #define EMMC_FORCE_IRPT_CBAD_ERR_LSB 19
1088 #define EMMC_FORCE_IRPT_CEND_ERR_BITS 18:18
1089 #define EMMC_FORCE_IRPT_CEND_ERR_SET 0x00040000
1090 #define EMMC_FORCE_IRPT_CEND_ERR_CLR 0xfffbffff
1091 #define EMMC_FORCE_IRPT_CEND_ERR_MSB 18
1092 #define EMMC_FORCE_IRPT_CEND_ERR_LSB 18
1093 #define EMMC_FORCE_IRPT_CCRC_ERR_BITS 17:17
1094 #define EMMC_FORCE_IRPT_CCRC_ERR_SET 0x00020000
1095 #define EMMC_FORCE_IRPT_CCRC_ERR_CLR 0xfffdffff
1096 #define EMMC_FORCE_IRPT_CCRC_ERR_MSB 17
1097 #define EMMC_FORCE_IRPT_CCRC_ERR_LSB 17
1098 #define EMMC_FORCE_IRPT_CTO_ERR_BITS 16:16
1099 #define EMMC_FORCE_IRPT_CTO_ERR_SET 0x00010000
1100 #define EMMC_FORCE_IRPT_CTO_ERR_CLR 0xfffeffff
1101 #define EMMC_FORCE_IRPT_CTO_ERR_MSB 16
1102 #define EMMC_FORCE_IRPT_CTO_ERR_LSB 16
1103 #define EMMC_FORCE_IRPT_CARD_OUT_BITS 7:7
1104 #define EMMC_FORCE_IRPT_CARD_OUT_SET 0x00000080
1105 #define EMMC_FORCE_IRPT_CARD_OUT_CLR 0xffffff7f
1106 #define EMMC_FORCE_IRPT_CARD_OUT_MSB 7
1107 #define EMMC_FORCE_IRPT_CARD_OUT_LSB 7
1108 #define EMMC_FORCE_IRPT_CARD_IN_BITS 6:6
1109 #define EMMC_FORCE_IRPT_CARD_IN_SET 0x00000040
1110 #define EMMC_FORCE_IRPT_CARD_IN_CLR 0xffffffbf
1111 #define EMMC_FORCE_IRPT_CARD_IN_MSB 6
1112 #define EMMC_FORCE_IRPT_CARD_IN_LSB 6
1113 #define EMMC_FORCE_IRPT_READ_RDY_BITS 5:5
1114 #define EMMC_FORCE_IRPT_READ_RDY_SET 0x00000020
1115 #define EMMC_FORCE_IRPT_READ_RDY_CLR 0xffffffdf
1116 #define EMMC_FORCE_IRPT_READ_RDY_MSB 5
1117 #define EMMC_FORCE_IRPT_READ_RDY_LSB 5
1118 #define EMMC_FORCE_IRPT_WRITE_RDY_BITS 4:4
1119 #define EMMC_FORCE_IRPT_WRITE_RDY_SET 0x00000010
1120 #define EMMC_FORCE_IRPT_WRITE_RDY_CLR 0xffffffef
1121 #define EMMC_FORCE_IRPT_WRITE_RDY_MSB 4
1122 #define EMMC_FORCE_IRPT_WRITE_RDY_LSB 4
1123 #define EMMC_FORCE_IRPT_DMA_BITS 3:3
1124 #define EMMC_FORCE_IRPT_DMA_SET 0x00000008
1125 #define EMMC_FORCE_IRPT_DMA_CLR 0xfffffff7
1126 #define EMMC_FORCE_IRPT_DMA_MSB 3
1127 #define EMMC_FORCE_IRPT_DMA_LSB 3
1128 #define EMMC_FORCE_IRPT_BLOCK_GAP_BITS 2:2
1129 #define EMMC_FORCE_IRPT_BLOCK_GAP_SET 0x00000004
1130 #define EMMC_FORCE_IRPT_BLOCK_GAP_CLR 0xfffffffb
1131 #define EMMC_FORCE_IRPT_BLOCK_GAP_MSB 2
1132 #define EMMC_FORCE_IRPT_BLOCK_GAP_LSB 2
1133 #define EMMC_FORCE_IRPT_DATA_DONE_BITS 1:1
1134 #define EMMC_FORCE_IRPT_DATA_DONE_SET 0x00000002
1135 #define EMMC_FORCE_IRPT_DATA_DONE_CLR 0xfffffffd
1136 #define EMMC_FORCE_IRPT_DATA_DONE_MSB 1
1137 #define EMMC_FORCE_IRPT_DATA_DONE_LSB 1
1138 #define EMMC_FORCE_IRPT_CMD_DONE_BITS 0:0
1139 #define EMMC_FORCE_IRPT_CMD_DONE_SET 0x00000001
1140 #define EMMC_FORCE_IRPT_CMD_DONE_CLR 0xfffffffe
1141 #define EMMC_FORCE_IRPT_CMD_DONE_MSB 0
1142 #define EMMC_FORCE_IRPT_CMD_DONE_LSB 0
1143 #define EMMC_DMA_STATUS HW_REGISTER_RW( 0x7e300054 )
1144 #define EMMC_DMA_STATUS_MASK 0xffff00ff
1145 #define EMMC_DMA_STATUS_WIDTH 32
1146 #define EMMC_DMA_STATUS_RESET 0000000000
1147 #define EMMC_DMA_STATUS_LEN_NOMATCH_BITS 2:2
1148 #define EMMC_DMA_STATUS_LEN_NOMATCH_SET 0x00000004
1149 #define EMMC_DMA_STATUS_LEN_NOMATCH_CLR 0xfffffffb
1150 #define EMMC_DMA_STATUS_LEN_NOMATCH_MSB 2
1151 #define EMMC_DMA_STATUS_LEN_NOMATCH_LSB 2
1152 #define EMMC_DMA_STATUS_ERR_AT_BITS 1:0
1153 #define EMMC_DMA_STATUS_ERR_AT_SET 0x00000003
1154 #define EMMC_DMA_STATUS_ERR_AT_CLR 0xfffffffc
1155 #define EMMC_DMA_STATUS_ERR_AT_MSB 1
1156 #define EMMC_DMA_STATUS_ERR_AT_LSB 0
1157 #define EMMC_BOOT_TIMEOUT HW_REGISTER_RW( 0x7e300070 )
1158 #define EMMC_BOOT_TIMEOUT_MASK 0xffffffff
1159 #define EMMC_BOOT_TIMEOUT_WIDTH 32
1160 #define EMMC_BOOT_TIMEOUT_RESET 0000000000
1161 #define EMMC_BOOT_TIMEOUT_TIMEOUT_BITS 31:0
1162 #define EMMC_BOOT_TIMEOUT_TIMEOUT_SET 0xffffffff
1163 #define EMMC_BOOT_TIMEOUT_TIMEOUT_CLR 0x00000000
1164 #define EMMC_BOOT_TIMEOUT_TIMEOUT_MSB 31
1165 #define EMMC_BOOT_TIMEOUT_TIMEOUT_LSB 0
1166 #define EMMC_DBG_SEL HW_REGISTER_RW( 0x7e300074 )
1167 #define EMMC_DBG_SEL_MASK 0x00000001
1168 #define EMMC_DBG_SEL_WIDTH 1
1169 #define EMMC_DBG_SEL_RESET 0000000000
1170 #define EMMC_DBG_SEL_SELECT_BITS 0:0
1171 #define EMMC_DBG_SEL_SELECT_SET 0x00000001
1172 #define EMMC_DBG_SEL_SELECT_CLR 0xfffffffe
1173 #define EMMC_DBG_SEL_SELECT_MSB 0
1174 #define EMMC_DBG_SEL_SELECT_LSB 0
1175 #define EMMC_EXRDFIFO_CFG HW_REGISTER_RW( 0x7e300080 )
1176 #define EMMC_EXRDFIFO_CFG_MASK 0x00000007
1177 #define EMMC_EXRDFIFO_CFG_WIDTH 3
1178 #define EMMC_EXRDFIFO_CFG_RESET 0000000000
1179 #define EMMC_EXRDFIFO_CFG_RD_THRSH_BITS 2:0
1180 #define EMMC_EXRDFIFO_CFG_RD_THRSH_SET 0x00000007
1181 #define EMMC_EXRDFIFO_CFG_RD_THRSH_CLR 0xfffffff8
1182 #define EMMC_EXRDFIFO_CFG_RD_THRSH_MSB 2
1183 #define EMMC_EXRDFIFO_CFG_RD_THRSH_LSB 0
1184 #define EMMC_EXRDFIFO_EN HW_REGISTER_RW( 0x7e300084 )
1185 #define EMMC_EXRDFIFO_EN_MASK 0x00000001
1186 #define EMMC_EXRDFIFO_EN_WIDTH 1
1187 #define EMMC_EXRDFIFO_EN_RESET 0000000000
1188 #define EMMC_EXRDFIFO_EN_ENABLE_BITS 0:0
1189 #define EMMC_EXRDFIFO_EN_ENABLE_SET 0x00000001
1190 #define EMMC_EXRDFIFO_EN_ENABLE_CLR 0xfffffffe
1191 #define EMMC_EXRDFIFO_EN_ENABLE_MSB 0
1192 #define EMMC_EXRDFIFO_EN_ENABLE_LSB 0
1193 #define EMMC_TUNE_STEP HW_REGISTER_RW( 0x7e300088 )
1194 #define EMMC_TUNE_STEP_MASK 0x00000007
1195 #define EMMC_TUNE_STEP_WIDTH 3
1196 #define EMMC_TUNE_STEP_RESET 0000000000
1197 #define EMMC_TUNE_STEP_DELAY_BITS 2:0
1198 #define EMMC_TUNE_STEP_DELAY_SET 0x00000007
1199 #define EMMC_TUNE_STEP_DELAY_CLR 0xfffffff8
1200 #define EMMC_TUNE_STEP_DELAY_MSB 2
1201 #define EMMC_TUNE_STEP_DELAY_LSB 0
1202 #define EMMC_TUNE_STEPS_STD HW_REGISTER_RW( 0x7e30008c )
1203 #define EMMC_TUNE_STEPS_STD_MASK 0x0000003f
1204 #define EMMC_TUNE_STEPS_STD_WIDTH 6
1205 #define EMMC_TUNE_STEPS_STD_RESET 0000000000
1206 #define EMMC_TUNE_STEPS_STD_STEPS_BITS 5:0
1207 #define EMMC_TUNE_STEPS_STD_STEPS_SET 0x0000003f
1208 #define EMMC_TUNE_STEPS_STD_STEPS_CLR 0xffffffc0
1209 #define EMMC_TUNE_STEPS_STD_STEPS_MSB 5
1210 #define EMMC_TUNE_STEPS_STD_STEPS_LSB 0
1211 #define EMMC_TUNE_STEPS_DDR HW_REGISTER_RW( 0x7e300090 )
1212 #define EMMC_TUNE_STEPS_DDR_MASK 0x0000003f
1213 #define EMMC_TUNE_STEPS_DDR_WIDTH 6
1214 #define EMMC_TUNE_STEPS_DDR_RESET 0000000000
1215 #define EMMC_TUNE_STEPS_DDR_STEPS_BITS 5:0
1216 #define EMMC_TUNE_STEPS_DDR_STEPS_SET 0x0000003f
1217 #define EMMC_TUNE_STEPS_DDR_STEPS_CLR 0xffffffc0
1218 #define EMMC_TUNE_STEPS_DDR_STEPS_MSB 5
1219 #define EMMC_TUNE_STEPS_DDR_STEPS_LSB 0
1220 #define EMMC_BUS_CTRL HW_REGISTER_RW( 0x7e3000e0 )
1221 #define EMMC_BUS_CTRL_MASK 0xffffffff
1222 #define EMMC_BUS_CTRL_WIDTH 32
1223 #define EMMC_BUS_CTRL_RESET 0000000000
1224 #define EMMC_BUS_CTRL_BE_PWR_BITS 30:24
1225 #define EMMC_BUS_CTRL_BE_PWR_SET 0x7f000000
1226 #define EMMC_BUS_CTRL_BE_PWR_CLR 0x80ffffff
1227 #define EMMC_BUS_CTRL_BE_PWR_MSB 30
1228 #define EMMC_BUS_CTRL_BE_PWR_LSB 24
1229 #define EMMC_BUS_CTRL_IRQSEL_BITS 22:20
1230 #define EMMC_BUS_CTRL_IRQSEL_SET 0x00700000
1231 #define EMMC_BUS_CTRL_IRQSEL_CLR 0xff8fffff
1232 #define EMMC_BUS_CTRL_IRQSEL_MSB 22
1233 #define EMMC_BUS_CTRL_IRQSEL_LSB 20
1234 #define EMMC_BUS_CTRL_BUS_WIDTH_BITS 14:8
1235 #define EMMC_BUS_CTRL_BUS_WIDTH_SET 0x00007f00
1236 #define EMMC_BUS_CTRL_BUS_WIDTH_CLR 0xffff80ff
1237 #define EMMC_BUS_CTRL_BUS_WIDTH_MSB 14
1238 #define EMMC_BUS_CTRL_BUS_WIDTH_LSB 8
1239 #define EMMC_BUS_CTRL_IRQ_PINS_BITS 5:3
1240 #define EMMC_BUS_CTRL_IRQ_PINS_SET 0x00000038
1241 #define EMMC_BUS_CTRL_IRQ_PINS_CLR 0xffffffc7
1242 #define EMMC_BUS_CTRL_IRQ_PINS_MSB 5
1243 #define EMMC_BUS_CTRL_IRQ_PINS_LSB 3
1244 #define EMMC_BUS_CTRL_CLK_PINS_BITS 2:0
1245 #define EMMC_BUS_CTRL_CLK_PINS_SET 0x00000007
1246 #define EMMC_BUS_CTRL_CLK_PINS_CLR 0xfffffff8
1247 #define EMMC_BUS_CTRL_CLK_PINS_MSB 2
1248 #define EMMC_BUS_CTRL_CLK_PINS_LSB 0
1249 #define EMMC_SPI_INT_SPT HW_REGISTER_RW( 0x7e3000f0 )
1250 #define EMMC_SPI_INT_SPT_MASK 0x000000ff
1251 #define EMMC_SPI_INT_SPT_WIDTH 8
1252 #define EMMC_SPI_INT_SPT_RESET 0000000000
1253 #define EMMC_SPI_INT_SPT_SELECT_BITS 7:0
1254 #define EMMC_SPI_INT_SPT_SELECT_SET 0x000000ff
1255 #define EMMC_SPI_INT_SPT_SELECT_CLR 0xffffff00
1256 #define EMMC_SPI_INT_SPT_SELECT_MSB 7
1257 #define EMMC_SPI_INT_SPT_SELECT_LSB 0
1258 #define EMMC_SLOTISR_VER HW_REGISTER_RW( 0x7e3000fc )
1259 #define EMMC_SLOTISR_VER_MASK 0xffff00ff
1260 #define EMMC_SLOTISR_VER_WIDTH 32
1261 #define EMMC_SLOTISR_VER_RESET 0x99020000
1262 #define EMMC_SLOTISR_VER_VENDOR_BITS 31:24
1263 #define EMMC_SLOTISR_VER_VENDOR_SET 0xff000000
1264 #define EMMC_SLOTISR_VER_VENDOR_CLR 0x00ffffff
1265 #define EMMC_SLOTISR_VER_VENDOR_MSB 31
1266 #define EMMC_SLOTISR_VER_VENDOR_LSB 24
1267 #define EMMC_SLOTISR_VER_SDVERSION_BITS 23:16
1268 #define EMMC_SLOTISR_VER_SDVERSION_SET 0x00ff0000
1269 #define EMMC_SLOTISR_VER_SDVERSION_CLR 0xff00ffff
1270 #define EMMC_SLOTISR_VER_SDVERSION_MSB 23
1271 #define EMMC_SLOTISR_VER_SDVERSION_LSB 16
1272 #define EMMC_SLOTISR_VER_SLOT_STATUS_BITS 7:0
1273 #define EMMC_SLOTISR_VER_SLOT_STATUS_SET 0x000000ff
1274 #define EMMC_SLOTISR_VER_SLOT_STATUS_CLR 0xffffff00
1275 #define EMMC_SLOTISR_VER_SLOT_STATUS_MSB 7
1276 #define EMMC_SLOTISR_VER_SLOT_STATUS_LSB 0
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