eaea863900a464b636c61acbeef877a1154cb345
[rpi-open-firmware.git] / bcm2708_chip / fpga_microblaze.h
1 // This file was generated by the create_regs script
2 #define FPGA_MB_BASE 0x7e20b700
3 #define FPGA_MB_XSYS_BUILD_NUM HW_REGISTER_RO( 0x7e20b700 )
4 #define FPGA_MB_XSYS_BUILD_NUM_MASK 0xffffffff
5 #define FPGA_MB_XSYS_BUILD_NUM_WIDTH 32
6 #define FPGA_MB_XC0_BUILD_NUM HW_REGISTER_RO( 0x7e20b704 )
7 #define FPGA_MB_XC0_BUILD_NUM_MASK 0xffffffff
8 #define FPGA_MB_XC0_BUILD_NUM_WIDTH 32
9 #define FPGA_MB_XC1_BUILD_NUM HW_REGISTER_RO( 0x7e20b708 )
10 #define FPGA_MB_XC1_BUILD_NUM_MASK 0xffffffff
11 #define FPGA_MB_XC1_BUILD_NUM_WIDTH 32
12 #define FPGA_MB_XPERI_BUILD_NUM HW_REGISTER_RO( 0x7e20b70c )
13 #define FPGA_MB_XPERI_BUILD_NUM_MASK 0xffffffff
14 #define FPGA_MB_XPERI_BUILD_NUM_WIDTH 32
15 #define FPGA_MB_XH264_BUILD_NUM HW_REGISTER_RO( 0x7e20b710 )
16 #define FPGA_MB_XH264_BUILD_NUM_MASK 0xffffffff
17 #define FPGA_MB_XH264_BUILD_NUM_WIDTH 32
18 #define FPGA_MB_XV3D_BUILD_NUM HW_REGISTER_RO( 0x7e20b714 )
19 #define FPGA_MB_XV3D_BUILD_NUM_MASK 0xffffffff
20 #define FPGA_MB_XV3D_BUILD_NUM_WIDTH 32
21 #define FPGA_MB_XSLC1_BUILD_NUM HW_REGISTER_RO( 0x7e20b718 )
22 #define FPGA_MB_XSLC1_BUILD_NUM_MASK 0xffffffff
23 #define FPGA_MB_XSLC1_BUILD_NUM_WIDTH 32
24 #define FPGA_MB_XSLC2_BUILD_NUM HW_REGISTER_RO( 0x7e20b71c )
25 #define FPGA_MB_XSLC2_BUILD_NUM_MASK 0xffffffff
26 #define FPGA_MB_XSLC2_BUILD_NUM_WIDTH 32
27 #define FPGA_MB_XSLC3_BUILD_NUM HW_REGISTER_RO( 0x7e20b720 )
28 #define FPGA_MB_XSLC3_BUILD_NUM_MASK 0xffffffff
29 #define FPGA_MB_XSLC3_BUILD_NUM_WIDTH 32
30 #define FPGA_MB_CORE_CLK_FREQ HW_REGISTER_RO( 0x7e20b724 )
31 #define FPGA_MB_CORE_CLK_FREQ_MASK 0xffffffff
32 #define FPGA_MB_CORE_CLK_FREQ_WIDTH 32
33 #define FPGA_MB_SDC_CLK_FREQ HW_REGISTER_RO( 0x7e20b728 )
34 #define FPGA_MB_SDC_CLK_FREQ_MASK 0xffffffff
35 #define FPGA_MB_SDC_CLK_FREQ_WIDTH 32
36 #define FPGA_MB_SDC_H264_FREQ HW_REGISTER_RO( 0x7e20b72c )
37 #define FPGA_MB_SDC_H264_FREQ_MASK 0xffffffff
38 #define FPGA_MB_SDC_H264_FREQ_WIDTH 32
39 #define FPGA_MB_SDC_V3D_FREQ HW_REGISTER_RO( 0x7e20b730 )
40 #define FPGA_MB_SDC_V3D_FREQ_MASK 0xffffffff
41 #define FPGA_MB_SDC_V3D_FREQ_WIDTH 32
42 #define FPGA_MB_SDC_ISP_FREQ HW_REGISTER_RO( 0x7e20b734 )
43 #define FPGA_MB_SDC_ISP_FREQ_MASK 0xffffffff
44 #define FPGA_MB_SDC_ISP_FREQ_WIDTH 32
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