Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / gpio.h
1 // This file was generated by the create_regs script
2 #define GP_BASE 0x7e200000
3 #define GP_APB_ID 0x6770696f
4 #define GP_FSEL0 HW_REGISTER_RW( 0x7e200000 )
5 #define GP_FSEL0_MASK 0x3fffffff
6 #define GP_FSEL0_WIDTH 30
7 #define GP_FSEL0_RESET 0000000000
8 #define GP_FSEL0_FSEL09_BITS 29:27
9 #define GP_FSEL0_FSEL09_SET 0x38000000
10 #define GP_FSEL0_FSEL09_CLR 0xc7ffffff
11 #define GP_FSEL0_FSEL09_MSB 29
12 #define GP_FSEL0_FSEL09_LSB 27
13 #define GP_FSEL0_FSEL08_BITS 26:24
14 #define GP_FSEL0_FSEL08_SET 0x07000000
15 #define GP_FSEL0_FSEL08_CLR 0xf8ffffff
16 #define GP_FSEL0_FSEL08_MSB 26
17 #define GP_FSEL0_FSEL08_LSB 24
18 #define GP_FSEL0_FSEL07_BITS 23:21
19 #define GP_FSEL0_FSEL07_SET 0x00e00000
20 #define GP_FSEL0_FSEL07_CLR 0xff1fffff
21 #define GP_FSEL0_FSEL07_MSB 23
22 #define GP_FSEL0_FSEL07_LSB 21
23 #define GP_FSEL0_FSEL06_BITS 20:18
24 #define GP_FSEL0_FSEL06_SET 0x001c0000
25 #define GP_FSEL0_FSEL06_CLR 0xffe3ffff
26 #define GP_FSEL0_FSEL06_MSB 20
27 #define GP_FSEL0_FSEL06_LSB 18
28 #define GP_FSEL0_FSEL05_BITS 17:15
29 #define GP_FSEL0_FSEL05_SET 0x00038000
30 #define GP_FSEL0_FSEL05_CLR 0xfffc7fff
31 #define GP_FSEL0_FSEL05_MSB 17
32 #define GP_FSEL0_FSEL05_LSB 15
33 #define GP_FSEL0_FSEL04_BITS 14:12
34 #define GP_FSEL0_FSEL04_SET 0x00007000
35 #define GP_FSEL0_FSEL04_CLR 0xffff8fff
36 #define GP_FSEL0_FSEL04_MSB 14
37 #define GP_FSEL0_FSEL04_LSB 12
38 #define GP_FSEL0_FSEL03_BITS 11:9
39 #define GP_FSEL0_FSEL03_SET 0x00000e00
40 #define GP_FSEL0_FSEL03_CLR 0xfffff1ff
41 #define GP_FSEL0_FSEL03_MSB 11
42 #define GP_FSEL0_FSEL03_LSB 9
43 #define GP_FSEL0_FSEL02_BITS 8:6
44 #define GP_FSEL0_FSEL02_SET 0x000001c0
45 #define GP_FSEL0_FSEL02_CLR 0xfffffe3f
46 #define GP_FSEL0_FSEL02_MSB 8
47 #define GP_FSEL0_FSEL02_LSB 6
48 #define GP_FSEL0_FSEL01_BITS 5:3
49 #define GP_FSEL0_FSEL01_SET 0x00000038
50 #define GP_FSEL0_FSEL01_CLR 0xffffffc7
51 #define GP_FSEL0_FSEL01_MSB 5
52 #define GP_FSEL0_FSEL01_LSB 3
53 #define GP_FSEL0_FSEL00_BITS 2:0
54 #define GP_FSEL0_FSEL00_SET 0x00000007
55 #define GP_FSEL0_FSEL00_CLR 0xfffffff8
56 #define GP_FSEL0_FSEL00_MSB 2
57 #define GP_FSEL0_FSEL00_LSB 0
58 #define GP_FSEL1 HW_REGISTER_RW( 0x7e200004 )
59 #define GP_FSEL1_MASK 0x3fffffff
60 #define GP_FSEL1_WIDTH 30
61 #define GP_FSEL1_RESET 0000000000
62 #define GP_FSEL1_FSEL19_BITS 29:27
63 #define GP_FSEL1_FSEL19_SET 0x38000000
64 #define GP_FSEL1_FSEL19_CLR 0xc7ffffff
65 #define GP_FSEL1_FSEL19_MSB 29
66 #define GP_FSEL1_FSEL19_LSB 27
67 #define GP_FSEL1_FSEL18_BITS 26:24
68 #define GP_FSEL1_FSEL18_SET 0x07000000
69 #define GP_FSEL1_FSEL18_CLR 0xf8ffffff
70 #define GP_FSEL1_FSEL18_MSB 26
71 #define GP_FSEL1_FSEL18_LSB 24
72 #define GP_FSEL1_FSEL17_BITS 23:21
73 #define GP_FSEL1_FSEL17_SET 0x00e00000
74 #define GP_FSEL1_FSEL17_CLR 0xff1fffff
75 #define GP_FSEL1_FSEL17_MSB 23
76 #define GP_FSEL1_FSEL17_LSB 21
77 #define GP_FSEL1_FSEL16_BITS 20:18
78 #define GP_FSEL1_FSEL16_SET 0x001c0000
79 #define GP_FSEL1_FSEL16_CLR 0xffe3ffff
80 #define GP_FSEL1_FSEL16_MSB 20
81 #define GP_FSEL1_FSEL16_LSB 18
82 #define GP_FSEL1_FSEL15_BITS 17:15
83 #define GP_FSEL1_FSEL15_SET 0x00038000
84 #define GP_FSEL1_FSEL15_CLR 0xfffc7fff
85 #define GP_FSEL1_FSEL15_MSB 17
86 #define GP_FSEL1_FSEL15_LSB 15
87 #define GP_FSEL1_FSEL14_BITS 14:12
88 #define GP_FSEL1_FSEL14_SET 0x00007000
89 #define GP_FSEL1_FSEL14_CLR 0xffff8fff
90 #define GP_FSEL1_FSEL14_MSB 14
91 #define GP_FSEL1_FSEL14_LSB 12
92 #define GP_FSEL1_FSEL13_BITS 11:9
93 #define GP_FSEL1_FSEL13_SET 0x00000e00
94 #define GP_FSEL1_FSEL13_CLR 0xfffff1ff
95 #define GP_FSEL1_FSEL13_MSB 11
96 #define GP_FSEL1_FSEL13_LSB 9
97 #define GP_FSEL1_FSEL12_BITS 8:6
98 #define GP_FSEL1_FSEL12_SET 0x000001c0
99 #define GP_FSEL1_FSEL12_CLR 0xfffffe3f
100 #define GP_FSEL1_FSEL12_MSB 8
101 #define GP_FSEL1_FSEL12_LSB 6
102 #define GP_FSEL1_FSEL11_BITS 5:3
103 #define GP_FSEL1_FSEL11_SET 0x00000038
104 #define GP_FSEL1_FSEL11_CLR 0xffffffc7
105 #define GP_FSEL1_FSEL11_MSB 5
106 #define GP_FSEL1_FSEL11_LSB 3
107 #define GP_FSEL1_FSEL10_BITS 2:0
108 #define GP_FSEL1_FSEL10_SET 0x00000007
109 #define GP_FSEL1_FSEL10_CLR 0xfffffff8
110 #define GP_FSEL1_FSEL10_MSB 2
111 #define GP_FSEL1_FSEL10_LSB 0
112 #define GP_FSEL2 HW_REGISTER_RW( 0x7e200008 )
113 #define GP_FSEL2_MASK 0x3fffffff
114 #define GP_FSEL2_WIDTH 30
115 #define GP_FSEL2_RESET 0000000000
116 #define GP_FSEL2_FSEL29_BITS 29:27
117 #define GP_FSEL2_FSEL29_SET 0x38000000
118 #define GP_FSEL2_FSEL29_CLR 0xc7ffffff
119 #define GP_FSEL2_FSEL29_MSB 29
120 #define GP_FSEL2_FSEL29_LSB 27
121 #define GP_FSEL2_FSEL28_BITS 26:24
122 #define GP_FSEL2_FSEL28_SET 0x07000000
123 #define GP_FSEL2_FSEL28_CLR 0xf8ffffff
124 #define GP_FSEL2_FSEL28_MSB 26
125 #define GP_FSEL2_FSEL28_LSB 24
126 #define GP_FSEL2_FSEL27_BITS 23:21
127 #define GP_FSEL2_FSEL27_SET 0x00e00000
128 #define GP_FSEL2_FSEL27_CLR 0xff1fffff
129 #define GP_FSEL2_FSEL27_MSB 23
130 #define GP_FSEL2_FSEL27_LSB 21
131 #define GP_FSEL2_FSEL26_BITS 20:18
132 #define GP_FSEL2_FSEL26_SET 0x001c0000
133 #define GP_FSEL2_FSEL26_CLR 0xffe3ffff
134 #define GP_FSEL2_FSEL26_MSB 20
135 #define GP_FSEL2_FSEL26_LSB 18
136 #define GP_FSEL2_FSEL25_BITS 17:15
137 #define GP_FSEL2_FSEL25_SET 0x00038000
138 #define GP_FSEL2_FSEL25_CLR 0xfffc7fff
139 #define GP_FSEL2_FSEL25_MSB 17
140 #define GP_FSEL2_FSEL25_LSB 15
141 #define GP_FSEL2_FSEL24_BITS 14:12
142 #define GP_FSEL2_FSEL24_SET 0x00007000
143 #define GP_FSEL2_FSEL24_CLR 0xffff8fff
144 #define GP_FSEL2_FSEL24_MSB 14
145 #define GP_FSEL2_FSEL24_LSB 12
146 #define GP_FSEL2_FSEL23_BITS 11:9
147 #define GP_FSEL2_FSEL23_SET 0x00000e00
148 #define GP_FSEL2_FSEL23_CLR 0xfffff1ff
149 #define GP_FSEL2_FSEL23_MSB 11
150 #define GP_FSEL2_FSEL23_LSB 9
151 #define GP_FSEL2_FSEL22_BITS 8:6
152 #define GP_FSEL2_FSEL22_SET 0x000001c0
153 #define GP_FSEL2_FSEL22_CLR 0xfffffe3f
154 #define GP_FSEL2_FSEL22_MSB 8
155 #define GP_FSEL2_FSEL22_LSB 6
156 #define GP_FSEL2_FSEL21_BITS 5:3
157 #define GP_FSEL2_FSEL21_SET 0x00000038
158 #define GP_FSEL2_FSEL21_CLR 0xffffffc7
159 #define GP_FSEL2_FSEL21_MSB 5
160 #define GP_FSEL2_FSEL21_LSB 3
161 #define GP_FSEL2_FSEL20_BITS 2:0
162 #define GP_FSEL2_FSEL20_SET 0x00000007
163 #define GP_FSEL2_FSEL20_CLR 0xfffffff8
164 #define GP_FSEL2_FSEL20_MSB 2
165 #define GP_FSEL2_FSEL20_LSB 0
166 #define GP_FSEL3 HW_REGISTER_RW( 0x7e20000c )
167 #define GP_FSEL3_MASK 0x3fffffff
168 #define GP_FSEL3_WIDTH 30
169 #define GP_FSEL3_RESET 0000000000
170 #define GP_FSEL3_FSEL39_BITS 29:27
171 #define GP_FSEL3_FSEL39_SET 0x38000000
172 #define GP_FSEL3_FSEL39_CLR 0xc7ffffff
173 #define GP_FSEL3_FSEL39_MSB 29
174 #define GP_FSEL3_FSEL39_LSB 27
175 #define GP_FSEL3_FSEL38_BITS 26:24
176 #define GP_FSEL3_FSEL38_SET 0x07000000
177 #define GP_FSEL3_FSEL38_CLR 0xf8ffffff
178 #define GP_FSEL3_FSEL38_MSB 26
179 #define GP_FSEL3_FSEL38_LSB 24
180 #define GP_FSEL3_FSEL37_BITS 23:21
181 #define GP_FSEL3_FSEL37_SET 0x00e00000
182 #define GP_FSEL3_FSEL37_CLR 0xff1fffff
183 #define GP_FSEL3_FSEL37_MSB 23
184 #define GP_FSEL3_FSEL37_LSB 21
185 #define GP_FSEL3_FSEL36_BITS 20:18
186 #define GP_FSEL3_FSEL36_SET 0x001c0000
187 #define GP_FSEL3_FSEL36_CLR 0xffe3ffff
188 #define GP_FSEL3_FSEL36_MSB 20
189 #define GP_FSEL3_FSEL36_LSB 18
190 #define GP_FSEL3_FSEL35_BITS 17:15
191 #define GP_FSEL3_FSEL35_SET 0x00038000
192 #define GP_FSEL3_FSEL35_CLR 0xfffc7fff
193 #define GP_FSEL3_FSEL35_MSB 17
194 #define GP_FSEL3_FSEL35_LSB 15
195 #define GP_FSEL3_FSEL34_BITS 14:12
196 #define GP_FSEL3_FSEL34_SET 0x00007000
197 #define GP_FSEL3_FSEL34_CLR 0xffff8fff
198 #define GP_FSEL3_FSEL34_MSB 14
199 #define GP_FSEL3_FSEL34_LSB 12
200 #define GP_FSEL3_FSEL33_BITS 11:9
201 #define GP_FSEL3_FSEL33_SET 0x00000e00
202 #define GP_FSEL3_FSEL33_CLR 0xfffff1ff
203 #define GP_FSEL3_FSEL33_MSB 11
204 #define GP_FSEL3_FSEL33_LSB 9
205 #define GP_FSEL3_FSEL32_BITS 8:6
206 #define GP_FSEL3_FSEL32_SET 0x000001c0
207 #define GP_FSEL3_FSEL32_CLR 0xfffffe3f
208 #define GP_FSEL3_FSEL32_MSB 8
209 #define GP_FSEL3_FSEL32_LSB 6
210 #define GP_FSEL3_FSEL31_BITS 5:3
211 #define GP_FSEL3_FSEL31_SET 0x00000038
212 #define GP_FSEL3_FSEL31_CLR 0xffffffc7
213 #define GP_FSEL3_FSEL31_MSB 5
214 #define GP_FSEL3_FSEL31_LSB 3
215 #define GP_FSEL3_FSEL30_BITS 2:0
216 #define GP_FSEL3_FSEL30_SET 0x00000007
217 #define GP_FSEL3_FSEL30_CLR 0xfffffff8
218 #define GP_FSEL3_FSEL30_MSB 2
219 #define GP_FSEL3_FSEL30_LSB 0
220 #define GP_FSEL4 HW_REGISTER_RW( 0x7e200010 )
221 #define GP_FSEL4_MASK 0x3fffffff
222 #define GP_FSEL4_WIDTH 30
223 #define GP_FSEL4_RESET 0000000000
224 #define GP_FSEL4_FSEL49_BITS 29:27
225 #define GP_FSEL4_FSEL49_SET 0x38000000
226 #define GP_FSEL4_FSEL49_CLR 0xc7ffffff
227 #define GP_FSEL4_FSEL49_MSB 29
228 #define GP_FSEL4_FSEL49_LSB 27
229 #define GP_FSEL4_FSEL48_BITS 26:24
230 #define GP_FSEL4_FSEL48_SET 0x07000000
231 #define GP_FSEL4_FSEL48_CLR 0xf8ffffff
232 #define GP_FSEL4_FSEL48_MSB 26
233 #define GP_FSEL4_FSEL48_LSB 24
234 #define GP_FSEL4_FSEL47_BITS 23:21
235 #define GP_FSEL4_FSEL47_SET 0x00e00000
236 #define GP_FSEL4_FSEL47_CLR 0xff1fffff
237 #define GP_FSEL4_FSEL47_MSB 23
238 #define GP_FSEL4_FSEL47_LSB 21
239 #define GP_FSEL4_FSEL46_BITS 20:18
240 #define GP_FSEL4_FSEL46_SET 0x001c0000
241 #define GP_FSEL4_FSEL46_CLR 0xffe3ffff
242 #define GP_FSEL4_FSEL46_MSB 20
243 #define GP_FSEL4_FSEL46_LSB 18
244 #define GP_FSEL4_FSEL45_BITS 17:15
245 #define GP_FSEL4_FSEL45_SET 0x00038000
246 #define GP_FSEL4_FSEL45_CLR 0xfffc7fff
247 #define GP_FSEL4_FSEL45_MSB 17
248 #define GP_FSEL4_FSEL45_LSB 15
249 #define GP_FSEL4_FSEL44_BITS 14:12
250 #define GP_FSEL4_FSEL44_SET 0x00007000
251 #define GP_FSEL4_FSEL44_CLR 0xffff8fff
252 #define GP_FSEL4_FSEL44_MSB 14
253 #define GP_FSEL4_FSEL44_LSB 12
254 #define GP_FSEL4_FSEL43_BITS 11:9
255 #define GP_FSEL4_FSEL43_SET 0x00000e00
256 #define GP_FSEL4_FSEL43_CLR 0xfffff1ff
257 #define GP_FSEL4_FSEL43_MSB 11
258 #define GP_FSEL4_FSEL43_LSB 9
259 #define GP_FSEL4_FSEL42_BITS 8:6
260 #define GP_FSEL4_FSEL42_SET 0x000001c0
261 #define GP_FSEL4_FSEL42_CLR 0xfffffe3f
262 #define GP_FSEL4_FSEL42_MSB 8
263 #define GP_FSEL4_FSEL42_LSB 6
264 #define GP_FSEL4_FSEL41_BITS 5:3
265 #define GP_FSEL4_FSEL41_SET 0x00000038
266 #define GP_FSEL4_FSEL41_CLR 0xffffffc7
267 #define GP_FSEL4_FSEL41_MSB 5
268 #define GP_FSEL4_FSEL41_LSB 3
269 #define GP_FSEL4_FSEL40_BITS 2:0
270 #define GP_FSEL4_FSEL40_SET 0x00000007
271 #define GP_FSEL4_FSEL40_CLR 0xfffffff8
272 #define GP_FSEL4_FSEL40_MSB 2
273 #define GP_FSEL4_FSEL40_LSB 0
274 #define GP_FSEL5 HW_REGISTER_RW( 0x7e200014 )
275 #define GP_FSEL5_MASK 0x3fffffff
276 #define GP_FSEL5_WIDTH 30
277 #define GP_FSEL5_RESET 0000000000
278 #define GP_FSEL5_FSEL59_BITS 29:27
279 #define GP_FSEL5_FSEL59_SET 0x38000000
280 #define GP_FSEL5_FSEL59_CLR 0xc7ffffff
281 #define GP_FSEL5_FSEL59_MSB 29
282 #define GP_FSEL5_FSEL59_LSB 27
283 #define GP_FSEL5_FSEL58_BITS 26:24
284 #define GP_FSEL5_FSEL58_SET 0x07000000
285 #define GP_FSEL5_FSEL58_CLR 0xf8ffffff
286 #define GP_FSEL5_FSEL58_MSB 26
287 #define GP_FSEL5_FSEL58_LSB 24
288 #define GP_FSEL5_FSEL57_BITS 23:21
289 #define GP_FSEL5_FSEL57_SET 0x00e00000
290 #define GP_FSEL5_FSEL57_CLR 0xff1fffff
291 #define GP_FSEL5_FSEL57_MSB 23
292 #define GP_FSEL5_FSEL57_LSB 21
293 #define GP_FSEL5_FSEL56_BITS 20:18
294 #define GP_FSEL5_FSEL56_SET 0x001c0000
295 #define GP_FSEL5_FSEL56_CLR 0xffe3ffff
296 #define GP_FSEL5_FSEL56_MSB 20
297 #define GP_FSEL5_FSEL56_LSB 18
298 #define GP_FSEL5_FSEL55_BITS 17:15
299 #define GP_FSEL5_FSEL55_SET 0x00038000
300 #define GP_FSEL5_FSEL55_CLR 0xfffc7fff
301 #define GP_FSEL5_FSEL55_MSB 17
302 #define GP_FSEL5_FSEL55_LSB 15
303 #define GP_FSEL5_FSEL54_BITS 14:12
304 #define GP_FSEL5_FSEL54_SET 0x00007000
305 #define GP_FSEL5_FSEL54_CLR 0xffff8fff
306 #define GP_FSEL5_FSEL54_MSB 14
307 #define GP_FSEL5_FSEL54_LSB 12
308 #define GP_FSEL5_FSEL53_BITS 11:9
309 #define GP_FSEL5_FSEL53_SET 0x00000e00
310 #define GP_FSEL5_FSEL53_CLR 0xfffff1ff
311 #define GP_FSEL5_FSEL53_MSB 11
312 #define GP_FSEL5_FSEL53_LSB 9
313 #define GP_FSEL5_FSEL52_BITS 8:6
314 #define GP_FSEL5_FSEL52_SET 0x000001c0
315 #define GP_FSEL5_FSEL52_CLR 0xfffffe3f
316 #define GP_FSEL5_FSEL52_MSB 8
317 #define GP_FSEL5_FSEL52_LSB 6
318 #define GP_FSEL5_FSEL51_BITS 5:3
319 #define GP_FSEL5_FSEL51_SET 0x00000038
320 #define GP_FSEL5_FSEL51_CLR 0xffffffc7
321 #define GP_FSEL5_FSEL51_MSB 5
322 #define GP_FSEL5_FSEL51_LSB 3
323 #define GP_FSEL5_FSEL50_BITS 2:0
324 #define GP_FSEL5_FSEL50_SET 0x00000007
325 #define GP_FSEL5_FSEL50_CLR 0xfffffff8
326 #define GP_FSEL5_FSEL50_MSB 2
327 #define GP_FSEL5_FSEL50_LSB 0
328 #define GP_FSEL6 HW_REGISTER_RW( 0x7e200018 )
329 #define GP_FSEL6_MASK 0x3fffffff
330 #define GP_FSEL6_WIDTH 30
331 #define GP_FSEL6_RESET 0000000000
332 #define GP_FSEL6_FSEL69_BITS 29:27
333 #define GP_FSEL6_FSEL69_SET 0x38000000
334 #define GP_FSEL6_FSEL69_CLR 0xc7ffffff
335 #define GP_FSEL6_FSEL69_MSB 29
336 #define GP_FSEL6_FSEL69_LSB 27
337 #define GP_FSEL6_FSEL68_BITS 26:24
338 #define GP_FSEL6_FSEL68_SET 0x07000000
339 #define GP_FSEL6_FSEL68_CLR 0xf8ffffff
340 #define GP_FSEL6_FSEL68_MSB 26
341 #define GP_FSEL6_FSEL68_LSB 24
342 #define GP_FSEL6_FSEL67_BITS 23:21
343 #define GP_FSEL6_FSEL67_SET 0x00e00000
344 #define GP_FSEL6_FSEL67_CLR 0xff1fffff
345 #define GP_FSEL6_FSEL67_MSB 23
346 #define GP_FSEL6_FSEL67_LSB 21
347 #define GP_FSEL6_FSEL66_BITS 20:18
348 #define GP_FSEL6_FSEL66_SET 0x001c0000
349 #define GP_FSEL6_FSEL66_CLR 0xffe3ffff
350 #define GP_FSEL6_FSEL66_MSB 20
351 #define GP_FSEL6_FSEL66_LSB 18
352 #define GP_FSEL6_FSEL65_BITS 17:15
353 #define GP_FSEL6_FSEL65_SET 0x00038000
354 #define GP_FSEL6_FSEL65_CLR 0xfffc7fff
355 #define GP_FSEL6_FSEL65_MSB 17
356 #define GP_FSEL6_FSEL65_LSB 15
357 #define GP_FSEL6_FSEL64_BITS 14:12
358 #define GP_FSEL6_FSEL64_SET 0x00007000
359 #define GP_FSEL6_FSEL64_CLR 0xffff8fff
360 #define GP_FSEL6_FSEL64_MSB 14
361 #define GP_FSEL6_FSEL64_LSB 12
362 #define GP_FSEL6_FSEL63_BITS 11:9
363 #define GP_FSEL6_FSEL63_SET 0x00000e00
364 #define GP_FSEL6_FSEL63_CLR 0xfffff1ff
365 #define GP_FSEL6_FSEL63_MSB 11
366 #define GP_FSEL6_FSEL63_LSB 9
367 #define GP_FSEL6_FSEL62_BITS 8:6
368 #define GP_FSEL6_FSEL62_SET 0x000001c0
369 #define GP_FSEL6_FSEL62_CLR 0xfffffe3f
370 #define GP_FSEL6_FSEL62_MSB 8
371 #define GP_FSEL6_FSEL62_LSB 6
372 #define GP_FSEL6_FSEL61_BITS 5:3
373 #define GP_FSEL6_FSEL61_SET 0x00000038
374 #define GP_FSEL6_FSEL61_CLR 0xffffffc7
375 #define GP_FSEL6_FSEL61_MSB 5
376 #define GP_FSEL6_FSEL61_LSB 3
377 #define GP_FSEL6_FSEL60_BITS 2:0
378 #define GP_FSEL6_FSEL60_SET 0x00000007
379 #define GP_FSEL6_FSEL60_CLR 0xfffffff8
380 #define GP_FSEL6_FSEL60_MSB 2
381 #define GP_FSEL6_FSEL60_LSB 0
382 #define GP_SET0 HW_REGISTER_RW( 0x7e20001c )
383 #define GP_SET0_MASK 0xffffffff
384 #define GP_SET0_WIDTH 32
385 #define GP_SET0_RESET 0000000000
386 #define GP_SET0_SETn0_BITS 31:0
387 #define GP_SET0_SETn0_SET 0xffffffff
388 #define GP_SET0_SETn0_CLR 0x00000000
389 #define GP_SET0_SETn0_MSB 31
390 #define GP_SET0_SETn0_LSB 0
391 #define GP_SET1 HW_REGISTER_RW( 0x7e200020 )
392 #define GP_SET1_MASK 0xffffffff
393 #define GP_SET1_WIDTH 32
394 #define GP_SET1_RESET 0000000000
395 #define GP_SET1_SETn32_BITS 31:0
396 #define GP_SET1_SETn32_SET 0xffffffff
397 #define GP_SET1_SETn32_CLR 0x00000000
398 #define GP_SET1_SETn32_MSB 31
399 #define GP_SET1_SETn32_LSB 0
400 #define GP_SET2 HW_REGISTER_RW( 0x7e200024 )
401 #define GP_SET2_MASK 0x0000003f
402 #define GP_SET2_WIDTH 6
403 #define GP_SET2_RESET 0000000000
404 #define GP_SET2_SETn64_BITS 5:0
405 #define GP_SET2_SETn64_SET 0x0000003f
406 #define GP_SET2_SETn64_CLR 0xffffffc0
407 #define GP_SET2_SETn64_MSB 5
408 #define GP_SET2_SETn64_LSB 0
409 #define GP_CLR0 HW_REGISTER_RW( 0x7e200028 )
410 #define GP_CLR0_MASK 0xffffffff
411 #define GP_CLR0_WIDTH 32
412 #define GP_CLR0_RESET 0000000000
413 #define GP_CLR0_CLRn0_BITS 31:0
414 #define GP_CLR0_CLRn0_SET 0xffffffff
415 #define GP_CLR0_CLRn0_CLR 0x00000000
416 #define GP_CLR0_CLRn0_MSB 31
417 #define GP_CLR0_CLRn0_LSB 0
418 #define GP_CLR1 HW_REGISTER_RW( 0x7e20002c )
419 #define GP_CLR1_MASK 0xffffffff
420 #define GP_CLR1_WIDTH 32
421 #define GP_CLR1_RESET 0000000000
422 #define GP_CLR1_CLRn32_BITS 31:0
423 #define GP_CLR1_CLRn32_SET 0xffffffff
424 #define GP_CLR1_CLRn32_CLR 0x00000000
425 #define GP_CLR1_CLRn32_MSB 31
426 #define GP_CLR1_CLRn32_LSB 0
427 #define GP_CLR2 HW_REGISTER_RW( 0x7e200030 )
428 #define GP_CLR2_MASK 0x0000003f
429 #define GP_CLR2_WIDTH 6
430 #define GP_CLR2_RESET 0000000000
431 #define GP_CLR2_CLRn64_BITS 5:0
432 #define GP_CLR2_CLRn64_SET 0x0000003f
433 #define GP_CLR2_CLRn64_CLR 0xffffffc0
434 #define GP_CLR2_CLRn64_MSB 5
435 #define GP_CLR2_CLRn64_LSB 0
436 #define GP_LEV0 HW_REGISTER_RO( 0x7e200034 )
437 #define GP_LEV0_MASK 0xffffffff
438 #define GP_LEV0_WIDTH 32
439 #define GP_LEV0_RESET 0000000000
440 #define GP_LEV0_LEVn0_BITS 31:0
441 #define GP_LEV0_LEVn0_SET 0xffffffff
442 #define GP_LEV0_LEVn0_CLR 0x00000000
443 #define GP_LEV0_LEVn0_MSB 31
444 #define GP_LEV0_LEVn0_LSB 0
445 #define GP_LEV1 HW_REGISTER_RO( 0x7e200038 )
446 #define GP_LEV1_MASK 0xffffffff
447 #define GP_LEV1_WIDTH 32
448 #define GP_LEV1_RESET 0000000000
449 #define GP_LEV1_LEVn32_BITS 31:0
450 #define GP_LEV1_LEVn32_SET 0xffffffff
451 #define GP_LEV1_LEVn32_CLR 0x00000000
452 #define GP_LEV1_LEVn32_MSB 31
453 #define GP_LEV1_LEVn32_LSB 0
454 #define GP_LEV2 HW_REGISTER_RO( 0x7e20003c )
455 #define GP_LEV2_MASK 0x0000003f
456 #define GP_LEV2_WIDTH 6
457 #define GP_LEV2_RESET 0000000000
458 #define GP_LEV2_LEVn64_BITS 5:0
459 #define GP_LEV2_LEVn64_SET 0x0000003f
460 #define GP_LEV2_LEVn64_CLR 0xffffffc0
461 #define GP_LEV2_LEVn64_MSB 5
462 #define GP_LEV2_LEVn64_LSB 0
463 #define GP_EDS0 HW_REGISTER_RW( 0x7e200040 )
464 #define GP_EDS0_MASK 0xffffffff
465 #define GP_EDS0_WIDTH 32
466 #define GP_EDS0_RESET 0000000000
467 #define GP_EDS0_EDSn0_BITS 31:0
468 #define GP_EDS0_EDSn0_SET 0xffffffff
469 #define GP_EDS0_EDSn0_CLR 0x00000000
470 #define GP_EDS0_EDSn0_MSB 31
471 #define GP_EDS0_EDSn0_LSB 0
472 #define GP_EDS1 HW_REGISTER_RW( 0x7e200044 )
473 #define GP_EDS1_MASK 0xffffffff
474 #define GP_EDS1_WIDTH 32
475 #define GP_EDS1_RESET 0000000000
476 #define GP_EDS1_EDSn32_BITS 31:0
477 #define GP_EDS1_EDSn32_SET 0xffffffff
478 #define GP_EDS1_EDSn32_CLR 0x00000000
479 #define GP_EDS1_EDSn32_MSB 31
480 #define GP_EDS1_EDSn32_LSB 0
481 #define GP_EDS2 HW_REGISTER_RW( 0x7e200048 )
482 #define GP_EDS2_MASK 0x0000003f
483 #define GP_EDS2_WIDTH 6
484 #define GP_EDS2_RESET 0000000000
485 #define GP_EDS2_EDSn64_BITS 5:0
486 #define GP_EDS2_EDSn64_SET 0x0000003f
487 #define GP_EDS2_EDSn64_CLR 0xffffffc0
488 #define GP_EDS2_EDSn64_MSB 5
489 #define GP_EDS2_EDSn64_LSB 0
490 #define GP_REN0 HW_REGISTER_RW( 0x7e20004c )
491 #define GP_REN0_MASK 0xffffffff
492 #define GP_REN0_WIDTH 32
493 #define GP_REN0_RESET 0000000000
494 #define GP_REN0_RENn0_BITS 31:0
495 #define GP_REN0_RENn0_SET 0xffffffff
496 #define GP_REN0_RENn0_CLR 0x00000000
497 #define GP_REN0_RENn0_MSB 31
498 #define GP_REN0_RENn0_LSB 0
499 #define GP_REN1 HW_REGISTER_RW( 0x7e200050 )
500 #define GP_REN1_MASK 0xffffffff
501 #define GP_REN1_WIDTH 32
502 #define GP_REN1_RESET 0000000000
503 #define GP_REN1_RENn32_BITS 31:0
504 #define GP_REN1_RENn32_SET 0xffffffff
505 #define GP_REN1_RENn32_CLR 0x00000000
506 #define GP_REN1_RENn32_MSB 31
507 #define GP_REN1_RENn32_LSB 0
508 #define GP_REN2 HW_REGISTER_RW( 0x7e200054 )
509 #define GP_REN2_MASK 0x0000003f
510 #define GP_REN2_WIDTH 6
511 #define GP_REN2_RESET 0000000000
512 #define GP_REN2_RENn64_BITS 5:0
513 #define GP_REN2_RENn64_SET 0x0000003f
514 #define GP_REN2_RENn64_CLR 0xffffffc0
515 #define GP_REN2_RENn64_MSB 5
516 #define GP_REN2_RENn64_LSB 0
517 #define GP_FEN0 HW_REGISTER_RW( 0x7e200058 )
518 #define GP_FEN0_MASK 0xffffffff
519 #define GP_FEN0_WIDTH 32
520 #define GP_FEN0_RESET 0000000000
521 #define GP_FEN0_FENn0_BITS 31:0
522 #define GP_FEN0_FENn0_SET 0xffffffff
523 #define GP_FEN0_FENn0_CLR 0x00000000
524 #define GP_FEN0_FENn0_MSB 31
525 #define GP_FEN0_FENn0_LSB 0
526 #define GP_FEN1 HW_REGISTER_RW( 0x7e20005c )
527 #define GP_FEN1_MASK 0xffffffff
528 #define GP_FEN1_WIDTH 32
529 #define GP_FEN1_RESET 0000000000
530 #define GP_FEN1_FENn32_BITS 31:0
531 #define GP_FEN1_FENn32_SET 0xffffffff
532 #define GP_FEN1_FENn32_CLR 0x00000000
533 #define GP_FEN1_FENn32_MSB 31
534 #define GP_FEN1_FENn32_LSB 0
535 #define GP_FEN2 HW_REGISTER_RW( 0x7e200060 )
536 #define GP_FEN2_MASK 0x0000003f
537 #define GP_FEN2_WIDTH 6
538 #define GP_FEN2_RESET 0000000000
539 #define GP_FEN2_FENn64_BITS 5:0
540 #define GP_FEN2_FENn64_SET 0x0000003f
541 #define GP_FEN2_FENn64_CLR 0xffffffc0
542 #define GP_FEN2_FENn64_MSB 5
543 #define GP_FEN2_FENn64_LSB 0
544 #define GP_HEN0 HW_REGISTER_RW( 0x7e200064 )
545 #define GP_HEN0_MASK 0xffffffff
546 #define GP_HEN0_WIDTH 32
547 #define GP_HEN0_RESET 0000000000
548 #define GP_HEN0_HENn0_BITS 31:0
549 #define GP_HEN0_HENn0_SET 0xffffffff
550 #define GP_HEN0_HENn0_CLR 0x00000000
551 #define GP_HEN0_HENn0_MSB 31
552 #define GP_HEN0_HENn0_LSB 0
553 #define GP_HEN1 HW_REGISTER_RW( 0x7e200068 )
554 #define GP_HEN1_MASK 0xffffffff
555 #define GP_HEN1_WIDTH 32
556 #define GP_HEN1_RESET 0000000000
557 #define GP_HEN1_HENn32_BITS 31:0
558 #define GP_HEN1_HENn32_SET 0xffffffff
559 #define GP_HEN1_HENn32_CLR 0x00000000
560 #define GP_HEN1_HENn32_MSB 31
561 #define GP_HEN1_HENn32_LSB 0
562 #define GP_HEN2 HW_REGISTER_RW( 0x7e20006c )
563 #define GP_HEN2_MASK 0x0000003f
564 #define GP_HEN2_WIDTH 6
565 #define GP_HEN2_RESET 0000000000
566 #define GP_HEN2_HENn64_BITS 5:0
567 #define GP_HEN2_HENn64_SET 0x0000003f
568 #define GP_HEN2_HENn64_CLR 0xffffffc0
569 #define GP_HEN2_HENn64_MSB 5
570 #define GP_HEN2_HENn64_LSB 0
571 #define GP_LEN0 HW_REGISTER_RW( 0x7e200070 )
572 #define GP_LEN0_MASK 0xffffffff
573 #define GP_LEN0_WIDTH 32
574 #define GP_LEN0_RESET 0000000000
575 #define GP_LEN0_LENn0_BITS 31:0
576 #define GP_LEN0_LENn0_SET 0xffffffff
577 #define GP_LEN0_LENn0_CLR 0x00000000
578 #define GP_LEN0_LENn0_MSB 31
579 #define GP_LEN0_LENn0_LSB 0
580 #define GP_LEN1 HW_REGISTER_RW( 0x7e200074 )
581 #define GP_LEN1_MASK 0xffffffff
582 #define GP_LEN1_WIDTH 32
583 #define GP_LEN1_RESET 0000000000
584 #define GP_LEN1_LENn32_BITS 31:0
585 #define GP_LEN1_LENn32_SET 0xffffffff
586 #define GP_LEN1_LENn32_CLR 0x00000000
587 #define GP_LEN1_LENn32_MSB 31
588 #define GP_LEN1_LENn32_LSB 0
589 #define GP_LEN2 HW_REGISTER_RW( 0x7e200078 )
590 #define GP_LEN2_MASK 0x0000003f
591 #define GP_LEN2_WIDTH 6
592 #define GP_LEN2_RESET 0000000000
593 #define GP_LEN2_LENn64_BITS 5:0
594 #define GP_LEN2_LENn64_SET 0x0000003f
595 #define GP_LEN2_LENn64_CLR 0xffffffc0
596 #define GP_LEN2_LENn64_MSB 5
597 #define GP_LEN2_LENn64_LSB 0
598 #define GP_AREN0 HW_REGISTER_RW( 0x7e20007c )
599 #define GP_AREN0_MASK 0xffffffff
600 #define GP_AREN0_WIDTH 32
601 #define GP_AREN0_RESET 0000000000
602 #define GP_AREN0_ARENn0_BITS 31:0
603 #define GP_AREN0_ARENn0_SET 0xffffffff
604 #define GP_AREN0_ARENn0_CLR 0x00000000
605 #define GP_AREN0_ARENn0_MSB 31
606 #define GP_AREN0_ARENn0_LSB 0
607 #define GP_AREN1 HW_REGISTER_RW( 0x7e200080 )
608 #define GP_AREN1_MASK 0xffffffff
609 #define GP_AREN1_WIDTH 32
610 #define GP_AREN1_RESET 0000000000
611 #define GP_AREN1_ARENn32_BITS 31:0
612 #define GP_AREN1_ARENn32_SET 0xffffffff
613 #define GP_AREN1_ARENn32_CLR 0x00000000
614 #define GP_AREN1_ARENn32_MSB 31
615 #define GP_AREN1_ARENn32_LSB 0
616 #define GP_AREN2 HW_REGISTER_RW( 0x7e200084 )
617 #define GP_AREN2_MASK 0x0000003f
618 #define GP_AREN2_WIDTH 6
619 #define GP_AREN2_RESET 0000000000
620 #define GP_AREN2_ARENn64_BITS 5:0
621 #define GP_AREN2_ARENn64_SET 0x0000003f
622 #define GP_AREN2_ARENn64_CLR 0xffffffc0
623 #define GP_AREN2_ARENn64_MSB 5
624 #define GP_AREN2_ARENn64_LSB 0
625 #define GP_AFEN0 HW_REGISTER_RW( 0x7e200088 )
626 #define GP_AFEN0_MASK 0xffffffff
627 #define GP_AFEN0_WIDTH 32
628 #define GP_AFEN0_RESET 0000000000
629 #define GP_AFEN0_AFENn0_BITS 31:0
630 #define GP_AFEN0_AFENn0_SET 0xffffffff
631 #define GP_AFEN0_AFENn0_CLR 0x00000000
632 #define GP_AFEN0_AFENn0_MSB 31
633 #define GP_AFEN0_AFENn0_LSB 0
634 #define GP_AFEN1 HW_REGISTER_RW( 0x7e20008c )
635 #define GP_AFEN1_MASK 0xffffffff
636 #define GP_AFEN1_WIDTH 32
637 #define GP_AFEN1_RESET 0000000000
638 #define GP_AFEN1_AFENn32_BITS 31:0
639 #define GP_AFEN1_AFENn32_SET 0xffffffff
640 #define GP_AFEN1_AFENn32_CLR 0x00000000
641 #define GP_AFEN1_AFENn32_MSB 31
642 #define GP_AFEN1_AFENn32_LSB 0
643 #define GP_AFEN2 HW_REGISTER_RW( 0x7e200090 )
644 #define GP_AFEN2_MASK 0x0000003f
645 #define GP_AFEN2_WIDTH 6
646 #define GP_AFEN2_RESET 0000000000
647 #define GP_AFEN2_AFENn64_BITS 5:0
648 #define GP_AFEN2_AFENn64_SET 0x0000003f
649 #define GP_AFEN2_AFENn64_CLR 0xffffffc0
650 #define GP_AFEN2_AFENn64_MSB 5
651 #define GP_AFEN2_AFENn64_LSB 0
652 #define GP_PUD HW_REGISTER_RW( 0x7e200094 )
653 #define GP_PUD_MASK 0x00000003
654 #define GP_PUD_WIDTH 2
655 #define GP_PUD_RESET 0000000000
656 #define GP_PUD_PUD_BITS 1:0
657 #define GP_PUD_PUD_SET 0x00000003
658 #define GP_PUD_PUD_CLR 0xfffffffc
659 #define GP_PUD_PUD_MSB 1
660 #define GP_PUD_PUD_LSB 0
661 #define GP_PUDCLK0 HW_REGISTER_RW( 0x7e200098 )
662 #define GP_PUDCLK0_MASK 0xffffffff
663 #define GP_PUDCLK0_WIDTH 32
664 #define GP_PUDCLK0_RESET 0000000000
665 #define GP_PUDCLK0_PUDCLKn0_BITS 31:0
666 #define GP_PUDCLK0_PUDCLKn0_SET 0xffffffff
667 #define GP_PUDCLK0_PUDCLKn0_CLR 0x00000000
668 #define GP_PUDCLK0_PUDCLKn0_MSB 31
669 #define GP_PUDCLK0_PUDCLKn0_LSB 0
670 #define GP_PUDCLK1 HW_REGISTER_RW( 0x7e20009c )
671 #define GP_PUDCLK1_MASK 0xffffffff
672 #define GP_PUDCLK1_WIDTH 32
673 #define GP_PUDCLK1_RESET 0000000000
674 #define GP_PUDCLK1_PUDCLKn32_BITS 31:0
675 #define GP_PUDCLK1_PUDCLKn32_SET 0xffffffff
676 #define GP_PUDCLK1_PUDCLKn32_CLR 0x00000000
677 #define GP_PUDCLK1_PUDCLKn32_MSB 31
678 #define GP_PUDCLK1_PUDCLKn32_LSB 0
679 #define GP_PUDCLK2 HW_REGISTER_RW( 0x7e2000a0 )
680 #define GP_PUDCLK2_MASK 0x0000003f
681 #define GP_PUDCLK2_WIDTH 6
682 #define GP_PUDCLK2_RESET 0000000000
683 #define GP_PUDCLK2_PUDCLKn64_BITS 5:0
684 #define GP_PUDCLK2_PUDCLKn64_SET 0x0000003f
685 #define GP_PUDCLK2_PUDCLKn64_CLR 0xffffffc0
686 #define GP_PUDCLK2_PUDCLKn64_MSB 5
687 #define GP_PUDCLK2_PUDCLKn64_LSB 0
688 #define GP_SEN0 HW_REGISTER_RW( 0x7e2000a4 )
689 #define GP_SEN0_MASK 0xffffffff
690 #define GP_SEN0_WIDTH 32
691 #define GP_SEN0_RESET 0xffffffff
692 #define GP_SEN0_SEN_BITS 31:0
693 #define GP_SEN0_SEN_SET 0xffffffff
694 #define GP_SEN0_SEN_CLR 0x00000000
695 #define GP_SEN0_SEN_MSB 31
696 #define GP_SEN0_SEN_LSB 0
697 #define GP_SEN1 HW_REGISTER_RW( 0x7e2000a8 )
698 #define GP_SEN1_MASK 0x003fffff
699 #define GP_SEN1_WIDTH 22
700 #define GP_SEN1_RESET 0x003fffff
701 #define GP_SEN1_SEN_BITS 21:0
702 #define GP_SEN1_SEN_SET 0x003fffff
703 #define GP_SEN1_SEN_CLR 0xffc00000
704 #define GP_SEN1_SEN_MSB 21
705 #define GP_SEN1_SEN_LSB 0
706 #define GP_GPTEST HW_REGISTER_RW( 0x7e2000b0 )
707 #define GP_GPTEST_MASK 0x0000000f
708 #define GP_GPTEST_WIDTH 4
709 #define GP_GPTEST_RESET 0000000000
710 #define GP_GPTEST_SMPS_BITS 0:0
711 #define GP_GPTEST_SMPS_SET 0x00000001
712 #define GP_GPTEST_SMPS_CLR 0xfffffffe
713 #define GP_GPTEST_SMPS_MSB 0
714 #define GP_GPTEST_SMPS_LSB 0
715 #define GP_GPTEST_SPARE_BITS 3:1
716 #define GP_GPTEST_SPARE_SET 0x0000000e
717 #define GP_GPTEST_SPARE_CLR 0xfffffff1
718 #define GP_GPTEST_SPARE_MSB 3
719 #define GP_GPTEST_SPARE_LSB 1
720 #define GP_AJBCONF HW_REGISTER_RW( 0x7e2000c0 )
721 #define GP_AJBCONF_MASK 0x80ffffff
722 #define GP_AJBCONF_WIDTH 32
723 #define GP_AJBCONF_RESET 0000000000
724 #define GP_AJBTMS HW_REGISTER_RW( 0x7e2000c4 )
725 #define GP_AJBTMS_MASK 0xffffffff
726 #define GP_AJBTMS_WIDTH 32
727 #define GP_AJBTMS_RESET 0000000000
728 #define GP_AJBTDI HW_REGISTER_RW( 0x7e2000c8 )
729 #define GP_AJBTDI_MASK 0xffffffff
730 #define GP_AJBTDI_WIDTH 32
731 #define GP_AJBTDI_RESET 0000000000
732 #define GP_AJBTDO HW_REGISTER_RW( 0x7e2000cc )
733 #define GP_AJBTDO_MASK 0xffffffff
734 #define GP_AJBTDO_WIDTH 32
735 #define GP_AJBTDO_RESET 0000000000
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