093a71b886a665f86f272f84ddf99ec3435eaae9
[rpi-open-firmware.git] / bcm2708_chip / hardware.h
1
2 // macro definitions plus aliases to maintain some old reg names
3 // Commented out to reveal fake defines
4 //#include "register_map_macros.h"
5
6 // Necessary macros to make C code understand registers
7 #if defined(_ATHENA_)
8 #define HW_REGISTER_RW(addr) ((addr))
9 #else
10 #define HW_REGISTER_RW(addr) (*(volatile unsigned long *)(addr))
11 #endif
12 #define HW_REGISTER_RO(addr) (*(const volatile unsigned long *)(addr))
13 #define HW_POINTER_TO_ADDRESS(pointer) ((uint32_t)(void *)&(pointer))
14
15 //interrupt definitions
16 #define INTERRUPT_HW_NUM (64)
17 #define INTERRUPT_HW_OFFSET (64)
18 #define INTERRUPT_SW_OFFSET (32)
19 #define INTERRUPT_SW_NUM (32)
20 #define INTERRUPT_TIMER0 (INTERRUPT_HW_OFFSET + 0 )
21 #define INTERRUPT_TIMER1 (INTERRUPT_HW_OFFSET + 1 )
22 #define INTERRUPT_TIMER2 (INTERRUPT_HW_OFFSET + 2 )
23 #define INTERRUPT_TIMER3 (INTERRUPT_HW_OFFSET + 3 )
24 #define INTERRUPT_CODEC0 (INTERRUPT_HW_OFFSET + 4 )
25 #define INTERRUPT_CODEC1 (INTERRUPT_HW_OFFSET + 5 )
26 #define INTERRUPT_CODEC2 (INTERRUPT_HW_OFFSET + 6 )
27 #define INTERRUPT_JPEG (INTERRUPT_HW_OFFSET + 7 )
28 #define INTERRUPT_ISP (INTERRUPT_HW_OFFSET + 8 )
29 #define INTERRUPT_USB (INTERRUPT_HW_OFFSET + 9 )
30 #define INTERRUPT_3D (INTERRUPT_HW_OFFSET + 10 )
31 #define INTERRUPT_TRANSPOSER (INTERRUPT_HW_OFFSET + 11 )
32 #define INTERRUPT_MULTICORESYNC0 (INTERRUPT_HW_OFFSET + 12 )
33 #define INTERRUPT_MULTICORESYNC1 (INTERRUPT_HW_OFFSET + 13 )
34 #define INTERRUPT_MULTICORESYNC2 (INTERRUPT_HW_OFFSET + 14 )
35 #define INTERRUPT_MULTICORESYNC3 (INTERRUPT_HW_OFFSET + 15 )
36 #define INTERRUPT_DMA0 (INTERRUPT_HW_OFFSET + 16 )
37 #define INTERRUPT_DMA1 (INTERRUPT_HW_OFFSET + 17 )
38 #define INTERRUPT_DMA2 (INTERRUPT_HW_OFFSET + 18 )
39 #define INTERRUPT_DMA3 (INTERRUPT_HW_OFFSET + 19 )
40 #define INTERRUPT_DMA4 (INTERRUPT_HW_OFFSET + 20 )
41 #define INTERRUPT_DMA5 (INTERRUPT_HW_OFFSET + 21 )
42 #define INTERRUPT_DMA6 (INTERRUPT_HW_OFFSET + 22 )
43 #define INTERRUPT_DMA7 (INTERRUPT_HW_OFFSET + 23 )
44 #define INTERRUPT_DMA8 (INTERRUPT_HW_OFFSET + 24 )
45 #define INTERRUPT_DMA9 (INTERRUPT_HW_OFFSET + 25 )
46 #define INTERRUPT_DMA10 (INTERRUPT_HW_OFFSET + 26 )
47 #define INTERRUPT_DMA11 (INTERRUPT_HW_OFFSET + 27 )
48 #define INTERRUPT_DMA12 (INTERRUPT_HW_OFFSET + 28 )
49 #define INTERRUPT_DMA13 (INTERRUPT_HW_OFFSET + 29 )
50 #define INTERRUPT_DMA14 (INTERRUPT_HW_OFFSET + 30 )
51 #define INTERRUPT_DMA15 (INTERRUPT_HW_OFFSET + 31 )
52 #define INTERRUPT_HOSTPORT (INTERRUPT_HW_OFFSET + 32 )
53 #define INTERRUPT_VIDEOSCALER (INTERRUPT_HW_OFFSET + 33 )
54 #define INTERRUPT_CCP2TX (INTERRUPT_HW_OFFSET + 34 )
55 #define INTERRUPT_SDC (INTERRUPT_HW_OFFSET + 35 )
56 #define INTERRUPT_DSI0 (INTERRUPT_HW_OFFSET + 36 )
57 #define INTERRUPT_SPARE2 (INTERRUPT_HW_OFFSET + 37 )
58 #define INTERRUPT_CAM0 (INTERRUPT_HW_OFFSET + 38 )
59 #define INTERRUPT_CAM1 (INTERRUPT_HW_OFFSET + 39 )
60 #define INTERRUPT_HDMI0 (INTERRUPT_HW_OFFSET + 40 )
61 #define INTERRUPT_HDMI1 (INTERRUPT_HW_OFFSET + 41 )
62 #define INTERRUPT_PIXELVALVE1 (INTERRUPT_HW_OFFSET + 42 )
63 #define INTERRUPT_SPARE3 (INTERRUPT_HW_OFFSET + 43 )
64 #define INTERRUPT_DSI1 (INTERRUPT_HW_OFFSET + 44 )
65 #define INTERRUPT_PWA0 (INTERRUPT_HW_OFFSET + 45 )
66 #define INTERRUPT_PWA1 (INTERRUPT_HW_OFFSET + 46 )
67 #define INTERRUPT_CPR (INTERRUPT_HW_OFFSET + 47 )
68 #define INTERRUPT_SMI (INTERRUPT_HW_OFFSET + 48 )
69 #define INTERRUPT_GPIO0 (INTERRUPT_HW_OFFSET + 49 )
70 #define INTERRUPT_GPIO1 (INTERRUPT_HW_OFFSET + 50 )
71 #define INTERRUPT_GPIO2 (INTERRUPT_HW_OFFSET + 51 )
72 #define INTERRUPT_GPIO3 (INTERRUPT_HW_OFFSET + 52 )
73 #define INTERRUPT_I2C (INTERRUPT_HW_OFFSET + 53 )
74 #define INTERRUPT_SPI (INTERRUPT_HW_OFFSET + 54 )
75 #define INTERRUPT_I2SPCM (INTERRUPT_HW_OFFSET + 55 )
76 #define INTERRUPT_SDIO (INTERRUPT_HW_OFFSET + 56 )
77 #define INTERRUPT_UART (INTERRUPT_HW_OFFSET + 57 )
78 #define INTERRUPT_SLIMBUS (INTERRUPT_HW_OFFSET + 58 )
79 #define INTERRUPT_VEC (INTERRUPT_HW_OFFSET + 59 )
80 #define INTERRUPT_CPG (INTERRUPT_HW_OFFSET + 60 )
81 #define INTERRUPT_RNG (INTERRUPT_HW_OFFSET + 61 )
82 #define INTERRUPT_SPARE4 (INTERRUPT_HW_OFFSET + 62 )
83 #define INTERRUPT_SPARE5 (INTERRUPT_HW_OFFSET + 63 )
84 #define INTERRUPT_DUMMY (INTERRUPT_HW_OFFSET + 63 )
85 #define ISRC0_0 IC0_SRC0
86 #define ISRC0_1 IC1_SRC0
87 #define ISRC1_0 IC0_SRC1
88 #define ISRC1_1 IC1_SRC1
89
90
91
92 /*---------------------------------------------------------------------------*/
93
94 // auto generated regestermap
95 #include "register_map.h"
96
97 /*---------------------------------------------------------------------------*/
98 /* DMA Source Definitions */
99
100 // port 0 is wired as permanently on inside the DMA
101 #define CAM_DMA (0<<DMA0_TI_PERMAP_LSB)
102 #define DISP_DMA (0<<DMA0_TI_PERMAP_LSB)
103 #define MS_DMA (0<<DMA0_TI_PERMAP_LSB)
104 #define BIT_STREAM_DMA (0<<DMA0_TI_PERMAP_LSB)
105 #define ACIS_DMA (0<<DMA0_TI_PERMAP_LSB)
106 #define SDRAM_CTRL_DMA (0<<DMA0_TI_PERMAP_LSB)
107
108 #define DSI_DMA ( 1<<DMA0_TI_PERMAP_LSB)
109 #define PCM_TX_DMA ( 2<<DMA0_TI_PERMAP_LSB)
110 #define PCM_RX_DMA ( 3<<DMA0_TI_PERMAP_LSB)
111 #define SMI_DMA ( 4<<DMA0_TI_PERMAP_LSB)
112 #define PWM_DMA ( 5<<DMA0_TI_PERMAP_LSB)
113 #define SPI_TX_DMA ( 6<<DMA0_TI_PERMAP_LSB)
114 #define SPI_RX_DMA ( 7<<DMA0_TI_PERMAP_LSB)
115 #define SLIM_DTX_DMA ( 8<<DMA0_TI_PERMAP_LSB)
116 #define SLIM_DRX_DMA ( 9<<DMA0_TI_PERMAP_LSB)
117 #define SLIM_CTX_DMA (10<<DMA0_TI_PERMAP_LSB)
118 #define SLIM_CRX_DMA (11<<DMA0_TI_PERMAP_LSB)
119 #define UNUSED_DMA_12 (12<<DMA0_TI_PERMAP_LSB)
120 #define SD_HOST_DMA (13<<DMA0_TI_PERMAP_LSB)
121 #define UNUSED_DMA_14 (14<<DMA0_TI_PERMAP_LSB)
122 #define DSI1_DMA (15<<DMA0_TI_PERMAP_LSB)
123
124 #define UNUSED_DMA_16 (16<<DMA0_TI_PERMAP_LSB)
125 #define HDMI_DMA (17<<DMA0_TI_PERMAP_LSB)
126 #define UNUSED_DMA_18 (18<<DMA0_TI_PERMAP_LSB)
127
128 #define CRYPTO_IP_DMA (19<<DMA0_TI_PERMAP_LSB)
129 #define CRYPTO_OP_DMA (20<<DMA0_TI_PERMAP_LSB)
130 #define SCALER_0_DMA (21<<DMA0_TI_PERMAP_LSB)
131 #define SCALER_1_DMA (22<<DMA0_TI_PERMAP_LSB)
132 #define SCALER_2_DMA (23<<DMA0_TI_PERMAP_LSB)
133 #define SMI_SCALER_0_DMA (24<<DMA0_TI_PERMAP_LSB)
134 #define SMI_SCALER_1_DMA (25<<DMA0_TI_PERMAP_LSB)
135 #define SMI_SCALER_2_DMA (26<<DMA0_TI_PERMAP_LSB)
136
137 // 27-32 unused
138 #define DMA_TI_S_128 (1<<9)
139 #define DMA_TI_S_INC (1<<8)
140 #define DMA_TI_D_32 0
141 #define DMA_TI_D_DREQ (1<<6)
142 #define DMA_TI_PER_MAP(n) (((n) & 0x1f) <<16)
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