81b44e006863b41b6489d50195c562e430a66ba2
[rpi-open-firmware.git] / bcm2708_chip / hdmi.h
1 // This file was generated by the create_regs script
2 #define HD_BASE 0x7e808000
3 #define HD_APB_ID 0x48444d49
4 #define HD_HDM_CTL HW_REGISTER_RW( 0x7e80800c )
5 #define HD_HDM_CTL_MASK 0x000003f7
6 #define HD_HDM_CTL_WIDTH 10
7 #define HD_HDM_CTL_RESET 0x000000f0
8 #define HD_HDM_CTL_ENABLE_BITS 0:0
9 #define HD_HDM_CTL_ENABLE_SET 0x00000001
10 #define HD_HDM_CTL_ENABLE_CLR 0xfffffffe
11 #define HD_HDM_CTL_ENABLE_MSB 0
12 #define HD_HDM_CTL_ENABLE_LSB 0
13 #define HD_HDM_CTL_ENABLE_RESET 0x0
14 #define HD_HDM_CTL_ENDIAN_BITS 1:1
15 #define HD_HDM_CTL_ENDIAN_SET 0x00000002
16 #define HD_HDM_CTL_ENDIAN_CLR 0xfffffffd
17 #define HD_HDM_CTL_ENDIAN_MSB 1
18 #define HD_HDM_CTL_ENDIAN_LSB 1
19 #define HD_HDM_CTL_ENDIAN_RESET 0x0
20 #define HD_HDM_CTL_SW_RST_BITS 2:2
21 #define HD_HDM_CTL_SW_RST_SET 0x00000004
22 #define HD_HDM_CTL_SW_RST_CLR 0xfffffffb
23 #define HD_HDM_CTL_SW_RST_MSB 2
24 #define HD_HDM_CTL_SW_RST_LSB 2
25 #define HD_HDM_CTL_SW_RST_RESET 0x0
26 #define HD_HDM_CTL_PDSTBY_BITS 5:4
27 #define HD_HDM_CTL_PDSTBY_SET 0x00000030
28 #define HD_HDM_CTL_PDSTBY_CLR 0xffffffcf
29 #define HD_HDM_CTL_PDSTBY_MSB 5
30 #define HD_HDM_CTL_PDSTBY_LSB 4
31 #define HD_HDM_CTL_PDSTBY_RESET 0x3
32 #define HD_HDM_CTL_RFSTBY_BITS 7:6
33 #define HD_HDM_CTL_RFSTBY_SET 0x000000c0
34 #define HD_HDM_CTL_RFSTBY_CLR 0xffffff3f
35 #define HD_HDM_CTL_RFSTBY_MSB 7
36 #define HD_HDM_CTL_RFSTBY_LSB 6
37 #define HD_HDM_CTL_RFSTBY_RESET 0x3
38 #define HD_HDM_CTL_CECOVR_BITS 8:8
39 #define HD_HDM_CTL_CECOVR_SET 0x00000100
40 #define HD_HDM_CTL_CECOVR_CLR 0xfffffeff
41 #define HD_HDM_CTL_CECOVR_MSB 8
42 #define HD_HDM_CTL_CECOVR_LSB 8
43 #define HD_HDM_CTL_CECOVR_RESET 0x0
44 #define HD_HDM_CTL_CECRXD_BITS 9:9
45 #define HD_HDM_CTL_CECRXD_SET 0x00000200
46 #define HD_HDM_CTL_CECRXD_CLR 0xfffffdff
47 #define HD_HDM_CTL_CECRXD_MSB 9
48 #define HD_HDM_CTL_CECRXD_LSB 9
49 #define HD_HDM_CTL_CECRXD_RESET 0x0
50 #define HD_MAI_CTL HW_REGISTER_RW( 0x7e808014 )
51 #define HD_MAI_CTL_MASK 0x0000ffff
52 #define HD_MAI_CTL_WIDTH 16
53 #define HD_MAI_CTL_RESET 0x00000020
54 #define HD_MAI_CTL_RST_MAI_BITS 0:0
55 #define HD_MAI_CTL_RST_MAI_SET 0x00000001
56 #define HD_MAI_CTL_RST_MAI_CLR 0xfffffffe
57 #define HD_MAI_CTL_RST_MAI_MSB 0
58 #define HD_MAI_CTL_RST_MAI_LSB 0
59 #define HD_MAI_CTL_RST_MAI_RESET 0x0
60 #define HD_MAI_CTL_ERRORF_BITS 1:1
61 #define HD_MAI_CTL_ERRORF_SET 0x00000002
62 #define HD_MAI_CTL_ERRORF_CLR 0xfffffffd
63 #define HD_MAI_CTL_ERRORF_MSB 1
64 #define HD_MAI_CTL_ERRORF_LSB 1
65 #define HD_MAI_CTL_ERRORF_RESET 0x0
66 #define HD_MAI_CTL_ERRORE_BITS 2:2
67 #define HD_MAI_CTL_ERRORE_SET 0x00000004
68 #define HD_MAI_CTL_ERRORE_CLR 0xfffffffb
69 #define HD_MAI_CTL_ERRORE_MSB 2
70 #define HD_MAI_CTL_ERRORE_LSB 2
71 #define HD_MAI_CTL_ERRORE_RESET 0x0
72 #define HD_MAI_CTL_ENABLE_BITS 3:3
73 #define HD_MAI_CTL_ENABLE_SET 0x00000008
74 #define HD_MAI_CTL_ENABLE_CLR 0xfffffff7
75 #define HD_MAI_CTL_ENABLE_MSB 3
76 #define HD_MAI_CTL_ENABLE_LSB 3
77 #define HD_MAI_CTL_ENABLE_RESET 0x0
78 #define HD_MAI_CTL_CHNUM_BITS 7:4
79 #define HD_MAI_CTL_CHNUM_SET 0x000000f0
80 #define HD_MAI_CTL_CHNUM_CLR 0xffffff0f
81 #define HD_MAI_CTL_CHNUM_MSB 7
82 #define HD_MAI_CTL_CHNUM_LSB 4
83 #define HD_MAI_CTL_CHNUM_RESET 0x2
84 #define HD_MAI_CTL_PAREN_BITS 8:8
85 #define HD_MAI_CTL_PAREN_SET 0x00000100
86 #define HD_MAI_CTL_PAREN_CLR 0xfffffeff
87 #define HD_MAI_CTL_PAREN_MSB 8
88 #define HD_MAI_CTL_PAREN_LSB 8
89 #define HD_MAI_CTL_PAREN_RESET 0x0
90 #define HD_MAI_CTL_FLUSH_BITS 9:9
91 #define HD_MAI_CTL_FLUSH_SET 0x00000200
92 #define HD_MAI_CTL_FLUSH_CLR 0xfffffdff
93 #define HD_MAI_CTL_FLUSH_MSB 9
94 #define HD_MAI_CTL_FLUSH_LSB 9
95 #define HD_MAI_CTL_FLUSH_RESET 0x0
96 #define HD_MAI_CTL_EMPTY_BITS 10:10
97 #define HD_MAI_CTL_EMPTY_SET 0x00000400
98 #define HD_MAI_CTL_EMPTY_CLR 0xfffffbff
99 #define HD_MAI_CTL_EMPTY_MSB 10
100 #define HD_MAI_CTL_EMPTY_LSB 10
101 #define HD_MAI_CTL_EMPTY_RESET 0x0
102 #define HD_MAI_CTL_FULL_BITS 11:11
103 #define HD_MAI_CTL_FULL_SET 0x00000800
104 #define HD_MAI_CTL_FULL_CLR 0xfffff7ff
105 #define HD_MAI_CTL_FULL_MSB 11
106 #define HD_MAI_CTL_FULL_LSB 11
107 #define HD_MAI_CTL_FULL_RESET 0x0
108 #define HD_MAI_CTL_WHOLSMP_BITS 12:12
109 #define HD_MAI_CTL_WHOLSMP_SET 0x00001000
110 #define HD_MAI_CTL_WHOLSMP_CLR 0xffffefff
111 #define HD_MAI_CTL_WHOLSMP_MSB 12
112 #define HD_MAI_CTL_WHOLSMP_LSB 12
113 #define HD_MAI_CTL_WHOLSMP_RESET 0x0
114 #define HD_MAI_CTL_CHALIGN_BITS 13:13
115 #define HD_MAI_CTL_CHALIGN_SET 0x00002000
116 #define HD_MAI_CTL_CHALIGN_CLR 0xffffdfff
117 #define HD_MAI_CTL_CHALIGN_MSB 13
118 #define HD_MAI_CTL_CHALIGN_LSB 13
119 #define HD_MAI_CTL_CHALIGN_RESET 0x0
120 #define HD_MAI_CTL_BUSY_BITS 14:14
121 #define HD_MAI_CTL_BUSY_SET 0x00004000
122 #define HD_MAI_CTL_BUSY_CLR 0xffffbfff
123 #define HD_MAI_CTL_BUSY_MSB 14
124 #define HD_MAI_CTL_BUSY_LSB 14
125 #define HD_MAI_CTL_BUSY_RESET 0x0
126 #define HD_MAI_CTL_DLATE_BITS 15:15
127 #define HD_MAI_CTL_DLATE_SET 0x00008000
128 #define HD_MAI_CTL_DLATE_CLR 0xffff7fff
129 #define HD_MAI_CTL_DLATE_MSB 15
130 #define HD_MAI_CTL_DLATE_LSB 15
131 #define HD_MAI_CTL_DLATE_RESET 0x0
132 #define HD_MAI_THR HW_REGISTER_RW( 0x7e808018 )
133 #define HD_MAI_THR_MASK 0xffffffff
134 #define HD_MAI_THR_WIDTH 32
135 #define HD_MAI_THR_RESET 0x01010101
136 #define HD_MAI_THR_DREQLOW_BITS 5:0
137 #define HD_MAI_THR_DREQLOW_SET 0x0000003f
138 #define HD_MAI_THR_DREQLOW_CLR 0xffffffc0
139 #define HD_MAI_THR_DREQLOW_MSB 5
140 #define HD_MAI_THR_DREQLOW_LSB 0
141 #define HD_MAI_THR_DREQLOW_RESET 0x1
142 #define HD_MAI_THR_DREQHIGH_BITS 13:8
143 #define HD_MAI_THR_DREQHIGH_SET 0x00003f00
144 #define HD_MAI_THR_DREQHIGH_CLR 0xffffc0ff
145 #define HD_MAI_THR_DREQHIGH_MSB 13
146 #define HD_MAI_THR_DREQHIGH_LSB 8
147 #define HD_MAI_THR_DREQHIGH_RESET 0x1
148 #define HD_MAI_THR_PANICLOW_BITS 21:16
149 #define HD_MAI_THR_PANICLOW_SET 0x003f0000
150 #define HD_MAI_THR_PANICLOW_CLR 0xffc0ffff
151 #define HD_MAI_THR_PANICLOW_MSB 21
152 #define HD_MAI_THR_PANICLOW_LSB 16
153 #define HD_MAI_THR_PANICLOW_RESET 0x1
154 #define HD_MAI_THR_PANICHIGH_BITS 29:24
155 #define HD_MAI_THR_PANICHIGH_SET 0x3f000000
156 #define HD_MAI_THR_PANICHIGH_CLR 0xc0ffffff
157 #define HD_MAI_THR_PANICHIGH_MSB 29
158 #define HD_MAI_THR_PANICHIGH_LSB 24
159 #define HD_MAI_THR_PANICHIGH_RESET 0x1
160 #define HD_MAI_FMT HW_REGISTER_RW( 0x7e80801c )
161 #define HD_MAI_FMT_MASK 0xffffffff
162 #define HD_MAI_FMT_WIDTH 32
163 #define HD_MAI_FMT_RESET 0000000000
164 #define HD_MAI_DAT HW_REGISTER_RW( 0x7e808020 )
165 #define HD_MAI_DAT_MASK 0xffffffff
166 #define HD_MAI_DAT_WIDTH 32
167 #define HD_MAI_DAT_RESET 0000000000
168 #define HD_SPARE HW_REGISTER_RW( 0x7e808024 )
169 #define HD_SPARE_MASK 0xffffffff
170 #define HD_SPARE_WIDTH 32
171 #define HD_SPARE_RESET 0000000000
172 #define HD_MAI_SMP HW_REGISTER_RW( 0x7e80802c )
173 #define HD_MAI_SMP_MASK 0xffffffff
174 #define HD_MAI_SMP_WIDTH 32
175 #define HD_MAI_SMP_RESET 0000000000
176 #define HD_VID_CTL HW_REGISTER_RW( 0x7e808038 )
177 #define HD_VID_CTL_MASK 0xfffc0000
178 #define HD_VID_CTL_WIDTH 32
179 #define HD_VID_CTL_RESET 0x00040000
180 #define HD_VID_CTL_BLANKPIX_BITS 18:18
181 #define HD_VID_CTL_BLANKPIX_SET 0x00040000
182 #define HD_VID_CTL_BLANKPIX_CLR 0xfffbffff
183 #define HD_VID_CTL_BLANKPIX_MSB 18
184 #define HD_VID_CTL_BLANKPIX_LSB 18
185 #define HD_VID_CTL_BLANKPIX_RESET 0x1
186 #define HD_VID_CTL_EMPRGB_BITS 19:19
187 #define HD_VID_CTL_EMPRGB_SET 0x00080000
188 #define HD_VID_CTL_EMPRGB_CLR 0xfff7ffff
189 #define HD_VID_CTL_EMPRGB_MSB 19
190 #define HD_VID_CTL_EMPRGB_LSB 19
191 #define HD_VID_CTL_EMPRGB_RESET 0x0
192 #define HD_VID_CTL_EMPSYNC_BITS 20:20
193 #define HD_VID_CTL_EMPSYNC_SET 0x00100000
194 #define HD_VID_CTL_EMPSYNC_CLR 0xffefffff
195 #define HD_VID_CTL_EMPSYNC_MSB 20
196 #define HD_VID_CTL_EMPSYNC_LSB 20
197 #define HD_VID_CTL_EMPSYNC_RESET 0x0
198 #define HD_VID_CTL_FULRGB_BITS 21:21
199 #define HD_VID_CTL_FULRGB_SET 0x00200000
200 #define HD_VID_CTL_FULRGB_CLR 0xffdfffff
201 #define HD_VID_CTL_FULRGB_MSB 21
202 #define HD_VID_CTL_FULRGB_LSB 21
203 #define HD_VID_CTL_FULRGB_RESET 0x0
204 #define HD_VID_CTL_FULSYNC_BITS 22:22
205 #define HD_VID_CTL_FULSYNC_SET 0x00400000
206 #define HD_VID_CTL_FULSYNC_CLR 0xffbfffff
207 #define HD_VID_CTL_FULSYNC_MSB 22
208 #define HD_VID_CTL_FULSYNC_LSB 22
209 #define HD_VID_CTL_FULSYNC_RESET 0x0
210 #define HD_VID_CTL_CLRRGB_BITS 23:23
211 #define HD_VID_CTL_CLRRGB_SET 0x00800000
212 #define HD_VID_CTL_CLRRGB_CLR 0xff7fffff
213 #define HD_VID_CTL_CLRRGB_MSB 23
214 #define HD_VID_CTL_CLRRGB_LSB 23
215 #define HD_VID_CTL_CLRRGB_RESET 0x0
216 #define HD_VID_CTL_CLRSYNC_BITS 24:24
217 #define HD_VID_CTL_CLRSYNC_SET 0x01000000
218 #define HD_VID_CTL_CLRSYNC_CLR 0xfeffffff
219 #define HD_VID_CTL_CLRSYNC_MSB 24
220 #define HD_VID_CTL_CLRSYNC_LSB 24
221 #define HD_VID_CTL_CLRSYNC_RESET 0x0
222 #define HD_VID_CTL_ERROR_BITS 26:25
223 #define HD_VID_CTL_ERROR_SET 0x06000000
224 #define HD_VID_CTL_ERROR_CLR 0xf9ffffff
225 #define HD_VID_CTL_ERROR_MSB 26
226 #define HD_VID_CTL_ERROR_LSB 25
227 #define HD_VID_CTL_ERROR_RESET 0x0
228 #define HD_VID_CTL_HPOL_BITS 27:27
229 #define HD_VID_CTL_HPOL_SET 0x08000000
230 #define HD_VID_CTL_HPOL_CLR 0xf7ffffff
231 #define HD_VID_CTL_HPOL_MSB 27
232 #define HD_VID_CTL_HPOL_LSB 27
233 #define HD_VID_CTL_HPOL_RESET 0x0
234 #define HD_VID_CTL_VPOL_BITS 28:28
235 #define HD_VID_CTL_VPOL_SET 0x10000000
236 #define HD_VID_CTL_VPOL_CLR 0xefffffff
237 #define HD_VID_CTL_VPOL_MSB 28
238 #define HD_VID_CTL_VPOL_LSB 28
239 #define HD_VID_CTL_VPOL_RESET 0x0
240 #define HD_VID_CTL_RST_FRAMEC_BITS 29:29
241 #define HD_VID_CTL_RST_FRAMEC_SET 0x20000000
242 #define HD_VID_CTL_RST_FRAMEC_CLR 0xdfffffff
243 #define HD_VID_CTL_RST_FRAMEC_MSB 29
244 #define HD_VID_CTL_RST_FRAMEC_LSB 29
245 #define HD_VID_CTL_RST_FRAMEC_RESET 0x0
246 #define HD_VID_CTL_UFEN_BITS 30:30
247 #define HD_VID_CTL_UFEN_SET 0x40000000
248 #define HD_VID_CTL_UFEN_CLR 0xbfffffff
249 #define HD_VID_CTL_UFEN_MSB 30
250 #define HD_VID_CTL_UFEN_LSB 30
251 #define HD_VID_CTL_UFEN_RESET 0x0
252 #define HD_VID_CTL_ENABLE_BITS 31:31
253 #define HD_VID_CTL_ENABLE_SET 0x80000000
254 #define HD_VID_CTL_ENABLE_CLR 0x7fffffff
255 #define HD_VID_CTL_ENABLE_MSB 31
256 #define HD_VID_CTL_ENABLE_LSB 31
257 #define HD_VID_CTL_ENABLE_RESET 0x0
258 #define HD_CSC_CTL HW_REGISTER_RW( 0x7e808040 )
259 #define HD_CSC_CTL_MASK 0x000000ff
260 #define HD_CSC_CTL_WIDTH 8
261 #define HD_CSC_CTL_RESET 0000000000
262 #define HD_CSC_CTL_ENABLE_BITS 0:0
263 #define HD_CSC_CTL_ENABLE_SET 0x00000001
264 #define HD_CSC_CTL_ENABLE_CLR 0xfffffffe
265 #define HD_CSC_CTL_ENABLE_MSB 0
266 #define HD_CSC_CTL_ENABLE_LSB 0
267 #define HD_CSC_CTL_ENABLE_RESET 0x0
268 #define HD_CSC_CTL_USERGB2YCC_BITS 1:1
269 #define HD_CSC_CTL_USERGB2YCC_SET 0x00000002
270 #define HD_CSC_CTL_USERGB2YCC_CLR 0xfffffffd
271 #define HD_CSC_CTL_USERGB2YCC_MSB 1
272 #define HD_CSC_CTL_USERGB2YCC_LSB 1
273 #define HD_CSC_CTL_USERGB2YCC_RESET 0x0
274 #define HD_CSC_CTL_MODE_BITS 3:2
275 #define HD_CSC_CTL_MODE_SET 0x0000000c
276 #define HD_CSC_CTL_MODE_CLR 0xfffffff3
277 #define HD_CSC_CTL_MODE_MSB 3
278 #define HD_CSC_CTL_MODE_LSB 2
279 #define HD_CSC_CTL_MODE_RESET 0x0
280 #define HD_CSC_CTL_PADMSB_BITS 4:4
281 #define HD_CSC_CTL_PADMSB_SET 0x00000010
282 #define HD_CSC_CTL_PADMSB_CLR 0xffffffef
283 #define HD_CSC_CTL_PADMSB_MSB 4
284 #define HD_CSC_CTL_PADMSB_LSB 4
285 #define HD_CSC_CTL_PADMSB_RESET 0x0
286 #define HD_CSC_CTL_COLORD_BITS 7:5
287 #define HD_CSC_CTL_COLORD_SET 0x000000e0
288 #define HD_CSC_CTL_COLORD_CLR 0xffffff1f
289 #define HD_CSC_CTL_COLORD_MSB 7
290 #define HD_CSC_CTL_COLORD_LSB 5
291 #define HD_CSC_CTL_COLORD_RESET 0x0
292 #define HD_CSC_12_11 HW_REGISTER_RW( 0x7e808044 )
293 #define HD_CSC_12_11_MASK 0xffffffff
294 #define HD_CSC_12_11_WIDTH 32
295 #define HD_CSC_12_11_RESET 0000000000
296 #define HD_CSC_14_13 HW_REGISTER_RW( 0x7e808048 )
297 #define HD_CSC_14_13_MASK 0xffffffff
298 #define HD_CSC_14_13_WIDTH 32
299 #define HD_CSC_14_13_RESET 0000000000
300 #define HD_CSC_22_21 HW_REGISTER_RW( 0x7e80804c )
301 #define HD_CSC_22_21_MASK 0xffffffff
302 #define HD_CSC_22_21_WIDTH 32
303 #define HD_CSC_22_21_RESET 0000000000
304 #define HD_CSC_24_23 HW_REGISTER_RW( 0x7e808050 )
305 #define HD_CSC_24_23_MASK 0xffffffff
306 #define HD_CSC_24_23_WIDTH 32
307 #define HD_CSC_24_23_RESET 0000000000
308 #define HD_CSC_32_31 HW_REGISTER_RW( 0x7e808054 )
309 #define HD_CSC_32_31_MASK 0xffffffff
310 #define HD_CSC_32_31_WIDTH 32
311 #define HD_CSC_32_31_RESET 0000000000
312 #define HD_CSC_34_33 HW_REGISTER_RW( 0x7e808058 )
313 #define HD_CSC_34_33_MASK 0xffffffff
314 #define HD_CSC_34_33_WIDTH 32
315 #define HD_CSC_34_33_RESET 0000000000
316 #define HD_FRAME_CNT HW_REGISTER_RW( 0x7e808068 )
317 #define HD_FRAME_CNT_MASK 0xffffffff
318 #define HD_FRAME_CNT_WIDTH 32
319 #define HD_FRAME_CNT_RESET 0000000000
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