61d646a3058213ab83562bdfc0d8471eddde43cf
[rpi-open-firmware.git] / bcm2708_chip / hdmicore.h
1 // This file was generated by the create_regs script
2 #define HDMI_BASE 0x7e902000
3 #define HDMI_CORE_REV HW_REGISTER_RW( 0x7e902000 )
4 #define HDMI_CORE_REV_MASK 0x0000ffff
5 #define HDMI_CORE_REV_WIDTH 16
6 #define HDMI_CORE_REV_RESET 0x00000600
7 #define HDMI_SW_RESET_CNTRL HW_REGISTER_RW( 0x7e902004 )
8 #define HDMI_SW_RESET_CNTRL_MASK 0x00000003
9 #define HDMI_SW_RESET_CNTRL_WIDTH 2
10 #define HDMI_SW_RESET_CNTRL_RESET 0000000000
11 #define HDMI_HOTPLUG_INT HW_REGISTER_RW( 0x7e902008 )
12 #define HDMI_HOTPLUG_INT_MASK 0x00000007
13 #define HDMI_HOTPLUG_INT_WIDTH 3
14 #define HDMI_HOTPLUG_INT_RESET 0x00000006
15 #define HDMI_HOTPLUG HW_REGISTER_RW( 0x7e90200c )
16 #define HDMI_HOTPLUG_MASK 0x00000001
17 #define HDMI_HOTPLUG_WIDTH 1
18 #define HDMI_HOTPLUG_RESET 0000000000
19 #define HDMI_BKSV0 HW_REGISTER_RW( 0x7e902010 )
20 #define HDMI_BKSV0_MASK 0xffffffff
21 #define HDMI_BKSV0_WIDTH 32
22 #define HDMI_BKSV0_RESET 0000000000
23 #define HDMI_BKSV1 HW_REGISTER_RW( 0x7e902014 )
24 #define HDMI_BKSV1_MASK 0xffffffff
25 #define HDMI_BKSV1_WIDTH 32
26 #define HDMI_BKSV1_RESET 0000000000
27 #define HDMI_AN0 HW_REGISTER_RW( 0x7e902018 )
28 #define HDMI_AN0_MASK 0xffffffff
29 #define HDMI_AN0_WIDTH 32
30 #define HDMI_AN0_RESET 0000000000
31 #define HDMI_AN1 HW_REGISTER_RW( 0x7e90201c )
32 #define HDMI_AN1_MASK 0xffffffff
33 #define HDMI_AN1_WIDTH 32
34 #define HDMI_AN1_RESET 0000000000
35 #define HDMI_AN_INFLUENCE_1 HW_REGISTER_RW( 0x7e902020 )
36 #define HDMI_AN_INFLUENCE_1_MASK 0xffffffff
37 #define HDMI_AN_INFLUENCE_1_WIDTH 32
38 #define HDMI_AN_INFLUENCE_1_RESET 0000000000
39 #define HDMI_AN_INFLUENCE_2 HW_REGISTER_RW( 0x7e902024 )
40 #define HDMI_AN_INFLUENCE_2_MASK 0xffffffff
41 #define HDMI_AN_INFLUENCE_2_WIDTH 32
42 #define HDMI_AN_INFLUENCE_2_RESET 0000000000
43 #define HDMI_TST_AN0 HW_REGISTER_RW( 0x7e902028 )
44 #define HDMI_TST_AN0_MASK 0xffffffff
45 #define HDMI_TST_AN0_WIDTH 32
46 #define HDMI_TST_AN0_RESET 0000000000
47 #define HDMI_TST_AN1 HW_REGISTER_RW( 0x7e90202c )
48 #define HDMI_TST_AN1_MASK 0xffffffff
49 #define HDMI_TST_AN1_WIDTH 32
50 #define HDMI_TST_AN1_RESET 0000000000
51 #define HDMI_KSV_FIFO_0 HW_REGISTER_RW( 0x7e902030 )
52 #define HDMI_KSV_FIFO_0_MASK 0xffffffff
53 #define HDMI_KSV_FIFO_0_WIDTH 32
54 #define HDMI_KSV_FIFO_0_RESET 0000000000
55 #define HDMI_KSV_FIFO_1 HW_REGISTER_RW( 0x7e902034 )
56 #define HDMI_KSV_FIFO_1_MASK 0x000000ff
57 #define HDMI_KSV_FIFO_1_WIDTH 8
58 #define HDMI_KSV_FIFO_1_RESET 0000000000
59 #define HDMI_V HW_REGISTER_RW( 0x7e902038 )
60 #define HDMI_V_MASK 0xffffffff
61 #define HDMI_V_WIDTH 32
62 #define HDMI_V_RESET 0000000000
63 #define HDMI_HDCP_KEY_1 HW_REGISTER_RW( 0x7e90203c )
64 #define HDMI_HDCP_KEY_1_MASK 0xffffff3f
65 #define HDMI_HDCP_KEY_1_WIDTH 32
66 #define HDMI_HDCP_KEY_1_RESET 0000000000
67 #define HDMI_HDCP_KEY_2 HW_REGISTER_RW( 0x7e902040 )
68 #define HDMI_HDCP_KEY_2_MASK 0xffffffff
69 #define HDMI_HDCP_KEY_2_WIDTH 32
70 #define HDMI_HDCP_KEY_2_RESET 0000000000
71 #define HDMI_HDCP_CTL HW_REGISTER_RW( 0x7e902044 )
72 #define HDMI_HDCP_CTL_MASK 0x0001030f
73 #define HDMI_HDCP_CTL_WIDTH 17
74 #define HDMI_HDCP_CTL_RESET 0000000000
75 #define HDMI_CP_STATUS HW_REGISTER_RW( 0x7e902048 )
76 #define HDMI_CP_STATUS_MASK 0x8000031f
77 #define HDMI_CP_STATUS_WIDTH 32
78 #define HDMI_CP_STATUS_RESET 0x00000100
79 #define HDMI_CP_INTEGRITY HW_REGISTER_RW( 0x7e90204c )
80 #define HDMI_CP_INTEGRITY_MASK 0xffffff03
81 #define HDMI_CP_INTEGRITY_WIDTH 32
82 #define HDMI_CP_INTEGRITY_RESET 0000000000
83 #define HDMI_CP_INTEGRITY_CFG HW_REGISTER_RW( 0x7e902050 )
84 #define HDMI_CP_INTEGRITY_CFG_MASK 0x0001ffff
85 #define HDMI_CP_INTEGRITY_CFG_WIDTH 17
86 #define HDMI_CP_INTEGRITY_CFG_RESET 0x00001000
87 #define HDMI_CP_CONFIG HW_REGISTER_RW( 0x7e902054 )
88 #define HDMI_CP_CONFIG_MASK 0x7fffffff
89 #define HDMI_CP_CONFIG_WIDTH 31
90 #define HDMI_CP_CONFIG_RESET 0x00130080
91 #define HDMI_CP_TST HW_REGISTER_RW( 0x7e902058 )
92 #define HDMI_CP_TST_MASK 0x002001ff
93 #define HDMI_CP_TST_WIDTH 22
94 #define HDMI_CP_TST_RESET 0000000000
95 #define HDMI_FIFO_CTL HW_REGISTER_RW( 0x7e90205c )
96 #define HDMI_FIFO_CTL_MASK 0x0000efff
97 #define HDMI_FIFO_CTL_WIDTH 16
98 #define HDMI_FIFO_CTL_RESET 0000000000
99 #define HDMI_FIFO_CTL_ON_VB_DONE_BITS 15:15
100 #define HDMI_FIFO_CTL_ON_VB_DONE_SET 0x00008000
101 #define HDMI_FIFO_CTL_ON_VB_DONE_CLR 0xffff7fff
102 #define HDMI_FIFO_CTL_ON_VB_DONE_MSB 15
103 #define HDMI_FIFO_CTL_ON_VB_DONE_LSB 15
104 #define HDMI_FIFO_CTL_RECENTER_DONE_BITS 14:14
105 #define HDMI_FIFO_CTL_RECENTER_DONE_SET 0x00004000
106 #define HDMI_FIFO_CTL_RECENTER_DONE_CLR 0xffffbfff
107 #define HDMI_FIFO_CTL_RECENTER_DONE_MSB 14
108 #define HDMI_FIFO_CTL_RECENTER_DONE_LSB 14
109 #define HDMI_FIFO_CTL_USE_EMPTY_BITS 13:13
110 #define HDMI_FIFO_CTL_USE_EMPTY_SET 0x00002000
111 #define HDMI_FIFO_CTL_USE_EMPTY_CLR 0xffffdfff
112 #define HDMI_FIFO_CTL_USE_EMPTY_MSB 13
113 #define HDMI_FIFO_CTL_USE_EMPTY_LSB 13
114 #define HDMI_FIFO_CTL_VB_CNT_BITS 11:8
115 #define HDMI_FIFO_CTL_VB_CNT_SET 0x00000f00
116 #define HDMI_FIFO_CTL_VB_CNT_CLR 0xfffff0ff
117 #define HDMI_FIFO_CTL_VB_CNT_MSB 11
118 #define HDMI_FIFO_CTL_VB_CNT_LSB 8
119 #define HDMI_FIFO_CTL_ON_VB_BITS 7:7
120 #define HDMI_FIFO_CTL_ON_VB_SET 0x00000080
121 #define HDMI_FIFO_CTL_ON_VB_CLR 0xffffff7f
122 #define HDMI_FIFO_CTL_ON_VB_MSB 7
123 #define HDMI_FIFO_CTL_ON_VB_LSB 7
124 #define HDMI_FIFO_CTL_RECENTER_BITS 6:6
125 #define HDMI_FIFO_CTL_RECENTER_SET 0x00000040
126 #define HDMI_FIFO_CTL_RECENTER_CLR 0xffffffbf
127 #define HDMI_FIFO_CTL_RECENTER_MSB 6
128 #define HDMI_FIFO_CTL_RECENTER_LSB 6
129 #define HDMI_FIFO_CTL_FIFO_RESET_BITS 5:5
130 #define HDMI_FIFO_CTL_FIFO_RESET_SET 0x00000020
131 #define HDMI_FIFO_CTL_FIFO_RESET_CLR 0xffffffdf
132 #define HDMI_FIFO_CTL_FIFO_RESET_MSB 5
133 #define HDMI_FIFO_CTL_FIFO_RESET_LSB 5
134 #define HDMI_FIFO_CTL_USE_PLL_LOCK_BITS 4:4
135 #define HDMI_FIFO_CTL_USE_PLL_LOCK_SET 0x00000010
136 #define HDMI_FIFO_CTL_USE_PLL_LOCK_CLR 0xffffffef
137 #define HDMI_FIFO_CTL_USE_PLL_LOCK_MSB 4
138 #define HDMI_FIFO_CTL_USE_PLL_LOCK_LSB 4
139 #define HDMI_FIFO_CTL_INV_CLK_XFR_BITS 3:3
140 #define HDMI_FIFO_CTL_INV_CLK_XFR_SET 0x00000008
141 #define HDMI_FIFO_CTL_INV_CLK_XFR_CLR 0xfffffff7
142 #define HDMI_FIFO_CTL_INV_CLK_XFR_MSB 3
143 #define HDMI_FIFO_CTL_INV_CLK_XFR_LSB 3
144 #define HDMI_FIFO_CTL_CAPTURE_POINTER_BITS 2:2
145 #define HDMI_FIFO_CTL_CAPTURE_POINTER_SET 0x00000004
146 #define HDMI_FIFO_CTL_CAPTURE_POINTER_CLR 0xfffffffb
147 #define HDMI_FIFO_CTL_CAPTURE_POINTER_MSB 2
148 #define HDMI_FIFO_CTL_CAPTURE_POINTER_LSB 2
149 #define HDMI_FIFO_CTL_USE_FULL_BITS 1:1
150 #define HDMI_FIFO_CTL_USE_FULL_SET 0x00000002
151 #define HDMI_FIFO_CTL_USE_FULL_CLR 0xfffffffd
152 #define HDMI_FIFO_CTL_USE_FULL_MSB 1
153 #define HDMI_FIFO_CTL_USE_FULL_LSB 1
154 #define HDMI_FIFO_CTL_MASTER_SLAVE_N_BITS 0:0
155 #define HDMI_FIFO_CTL_MASTER_SLAVE_N_SET 0x00000001
156 #define HDMI_FIFO_CTL_MASTER_SLAVE_N_CLR 0xfffffffe
157 #define HDMI_FIFO_CTL_MASTER_SLAVE_N_MSB 0
158 #define HDMI_FIFO_CTL_MASTER_SLAVE_N_LSB 0
159 #define HDMI_READ_POINTERS HW_REGISTER_RW( 0x7e902060 )
160 #define HDMI_READ_POINTERS_MASK 0x7fffffff
161 #define HDMI_READ_POINTERS_WIDTH 31
162 #define HDMI_READ_POINTERS_RESET 0000000000
163 #define HDMI_READ_POINTERS_DOMAIN_HALF_FULL_BITS 30:30
164 #define HDMI_READ_POINTERS_DOMAIN_HALF_FULL_SET 0x40000000
165 #define HDMI_READ_POINTERS_DOMAIN_HALF_FULL_CLR 0xbfffffff
166 #define HDMI_READ_POINTERS_DOMAIN_HALF_FULL_MSB 30
167 #define HDMI_READ_POINTERS_DOMAIN_HALF_FULL_LSB 30
168 #define HDMI_READ_POINTERS_DOMAIN_WR_ADDR_BITS 29:27
169 #define HDMI_READ_POINTERS_DOMAIN_WR_ADDR_SET 0x38000000
170 #define HDMI_READ_POINTERS_DOMAIN_WR_ADDR_CLR 0xc7ffffff
171 #define HDMI_READ_POINTERS_DOMAIN_WR_ADDR_MSB 29
172 #define HDMI_READ_POINTERS_DOMAIN_WR_ADDR_LSB 27
173 #define HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_BITS 26:24
174 #define HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_SET 0x07000000
175 #define HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_CLR 0xf8ffffff
176 #define HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_MSB 26
177 #define HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_LSB 24
178 #define HDMI_READ_POINTERS_DRFT_HOLD_WR_BITS 23:23
179 #define HDMI_READ_POINTERS_DRFT_HOLD_WR_SET 0x00800000
180 #define HDMI_READ_POINTERS_DRFT_HOLD_WR_CLR 0xff7fffff
181 #define HDMI_READ_POINTERS_DRFT_HOLD_WR_MSB 23
182 #define HDMI_READ_POINTERS_DRFT_HOLD_WR_LSB 23
183 #define HDMI_READ_POINTERS_DRFT_HOLD_RD_BITS 22:22
184 #define HDMI_READ_POINTERS_DRFT_HOLD_RD_SET 0x00400000
185 #define HDMI_READ_POINTERS_DRFT_HOLD_RD_CLR 0xffbfffff
186 #define HDMI_READ_POINTERS_DRFT_HOLD_RD_MSB 22
187 #define HDMI_READ_POINTERS_DRFT_HOLD_RD_LSB 22
188 #define HDMI_READ_POINTERS_DRFT_ALMOST_FULL_BITS 21:21
189 #define HDMI_READ_POINTERS_DRFT_ALMOST_FULL_SET 0x00200000
190 #define HDMI_READ_POINTERS_DRFT_ALMOST_FULL_CLR 0xffdfffff
191 #define HDMI_READ_POINTERS_DRFT_ALMOST_FULL_MSB 21
192 #define HDMI_READ_POINTERS_DRFT_ALMOST_FULL_LSB 21
193 #define HDMI_READ_POINTERS_DRFT_FULL_MINUS_BITS 20:20
194 #define HDMI_READ_POINTERS_DRFT_FULL_MINUS_SET 0x00100000
195 #define HDMI_READ_POINTERS_DRFT_FULL_MINUS_CLR 0xffefffff
196 #define HDMI_READ_POINTERS_DRFT_FULL_MINUS_MSB 20
197 #define HDMI_READ_POINTERS_DRFT_FULL_MINUS_LSB 20
198 #define HDMI_READ_POINTERS_DRFT_OVERFLOW_BITS 19:19
199 #define HDMI_READ_POINTERS_DRFT_OVERFLOW_SET 0x00080000
200 #define HDMI_READ_POINTERS_DRFT_OVERFLOW_CLR 0xfff7ffff
201 #define HDMI_READ_POINTERS_DRFT_OVERFLOW_MSB 19
202 #define HDMI_READ_POINTERS_DRFT_OVERFLOW_LSB 19
203 #define HDMI_READ_POINTERS_DRFT_ALMOST_MT_BITS 18:18
204 #define HDMI_READ_POINTERS_DRFT_ALMOST_MT_SET 0x00040000
205 #define HDMI_READ_POINTERS_DRFT_ALMOST_MT_CLR 0xfffbffff
206 #define HDMI_READ_POINTERS_DRFT_ALMOST_MT_MSB 18
207 #define HDMI_READ_POINTERS_DRFT_ALMOST_MT_LSB 18
208 #define HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_BITS 17:17
209 #define HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_SET 0x00020000
210 #define HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_CLR 0xfffdffff
211 #define HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_MSB 17
212 #define HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_LSB 17
213 #define HDMI_READ_POINTERS_DRFT_UNDERFLOW_BITS 16:16
214 #define HDMI_READ_POINTERS_DRFT_UNDERFLOW_SET 0x00010000
215 #define HDMI_READ_POINTERS_DRFT_UNDERFLOW_CLR 0xfffeffff
216 #define HDMI_READ_POINTERS_DRFT_UNDERFLOW_MSB 16
217 #define HDMI_READ_POINTERS_DRFT_UNDERFLOW_LSB 16
218 #define HDMI_READ_POINTERS_DRFT_WR_ADDR_BITS 15:8
219 #define HDMI_READ_POINTERS_DRFT_WR_ADDR_SET 0x0000ff00
220 #define HDMI_READ_POINTERS_DRFT_WR_ADDR_CLR 0xffff00ff
221 #define HDMI_READ_POINTERS_DRFT_WR_ADDR_MSB 15
222 #define HDMI_READ_POINTERS_DRFT_WR_ADDR_LSB 8
223 #define HDMI_READ_POINTERS_DRFT_RD_ADDR_BITS 7:7
224 #define HDMI_READ_POINTERS_DRFT_RD_ADDR_SET 0x00000080
225 #define HDMI_READ_POINTERS_DRFT_RD_ADDR_CLR 0xffffff7f
226 #define HDMI_READ_POINTERS_DRFT_RD_ADDR_MSB 7
227 #define HDMI_READ_POINTERS_DRFT_RD_ADDR_LSB 7
228 #define HDMI_ENCODER_CTL HW_REGISTER_RW( 0x7e902070 )
229 #define HDMI_ENCODER_CTL_MASK 0x00000001
230 #define HDMI_ENCODER_CTL_WIDTH 1
231 #define HDMI_ENCODER_CTL_RESET 0000000000
232 #define HDMI_PERT_CONFIG HW_REGISTER_RW( 0x7e902074 )
233 #define HDMI_PERT_CONFIG_MASK 0x00000fff
234 #define HDMI_PERT_CONFIG_WIDTH 12
235 #define HDMI_PERT_CONFIG_RESET 0000000000
236 #define HDMI_PERT_LFSR_PRELOAD HW_REGISTER_RW( 0x7e902078 )
237 #define HDMI_PERT_LFSR_PRELOAD_MASK 0xffffffff
238 #define HDMI_PERT_LFSR_PRELOAD_WIDTH 32
239 #define HDMI_PERT_LFSR_PRELOAD_RESET 0000000000
240 #define HDMI_PERT_LFSR_FEEDBACK_MASK HW_REGISTER_RW( 0x7e90207c )
241 #define HDMI_PERT_LFSR_FEEDBACK_MASK_MASK 0xffffffff
242 #define HDMI_PERT_LFSR_FEEDBACK_MASK_WIDTH 32
243 #define HDMI_PERT_LFSR_FEEDBACK_MASK_RESET 0000000000
244 #define HDMI_PERT_INSERT_ERR HW_REGISTER_RW( 0x7e902080 )
245 #define HDMI_PERT_INSERT_ERR_MASK 0x00ffffff
246 #define HDMI_PERT_INSERT_ERR_WIDTH 24
247 #define HDMI_PERT_INSERT_ERR_RESET 0000000000
248 #define HDMI_PERT_INSERT_ERR_SEP HW_REGISTER_RW( 0x7e902084 )
249 #define HDMI_PERT_INSERT_ERR_SEP_MASK 0xffffffff
250 #define HDMI_PERT_INSERT_ERR_SEP_WIDTH 32
251 #define HDMI_PERT_INSERT_ERR_SEP_RESET 0000000000
252 #define HDMI_PERT_TEST_LENGTH HW_REGISTER_RW( 0x7e902088 )
253 #define HDMI_PERT_TEST_LENGTH_MASK 0xffffffff
254 #define HDMI_PERT_TEST_LENGTH_WIDTH 32
255 #define HDMI_PERT_TEST_LENGTH_RESET 0000000000
256 #define HDMI_PERT_DATA HW_REGISTER_RW( 0x7e90208c )
257 #define HDMI_PERT_DATA_MASK 0x00ffffff
258 #define HDMI_PERT_DATA_WIDTH 24
259 #define HDMI_PERT_DATA_RESET 0000000000
260 #define HDMI_MAI_CHANNEL_MAP HW_REGISTER_RW( 0x7e902090 )
261 #define HDMI_MAI_CHANNEL_MAP_MASK 0x00ffffff
262 #define HDMI_MAI_CHANNEL_MAP_WIDTH 24
263 #define HDMI_MAI_CHANNEL_MAP_RESET 0x00fac688
264 #define HDMI_MAI_CONFIG HW_REGISTER_RW( 0x7e902094 )
265 #define HDMI_MAI_CONFIG_MASK 0x0fffffff
266 #define HDMI_MAI_CONFIG_WIDTH 28
267 #define HDMI_MAI_CONFIG_RESET 0x00000003
268 #define HDMI_MAI_FORMAT HW_REGISTER_RW( 0x7e902098 )
269 #define HDMI_MAI_FORMAT_MASK 0xffffffff
270 #define HDMI_MAI_FORMAT_WIDTH 32
271 #define HDMI_MAI_FORMAT_RESET 0000000000
272 #define HDMI_AUDIO_PACKET_CONFIG HW_REGISTER_RW( 0x7e90209c )
273 #define HDMI_AUDIO_PACKET_CONFIG_MASK 0x3fffffff
274 #define HDMI_AUDIO_PACKET_CONFIG_WIDTH 30
275 #define HDMI_AUDIO_PACKET_CONFIG_RESET 0x21000403
276 #define HDMI_RAM_PACKET_CONFIG HW_REGISTER_RW( 0x7e9020a0 )
277 #define HDMI_RAM_PACKET_CONFIG_MASK 0x00013fff
278 #define HDMI_RAM_PACKET_CONFIG_WIDTH 17
279 #define HDMI_RAM_PACKET_CONFIG_RESET 0000000000
280 #define HDMI_RAM_PACKET_STATUS HW_REGISTER_RW( 0x7e9020a4 )
281 #define HDMI_RAM_PACKET_STATUS_MASK 0x00003fff
282 #define HDMI_RAM_PACKET_STATUS_WIDTH 14
283 #define HDMI_RAM_PACKET_STATUS_RESET 0000000000
284 #define HDMI_CRP_CFG HW_REGISTER_RW( 0x7e9020a8 )
285 #define HDMI_CRP_CFG_MASK 0x0fffffff
286 #define HDMI_CRP_CFG_WIDTH 28
287 #define HDMI_CRP_CFG_RESET 0x08000000
288 #define HDMI_CTS_0 HW_REGISTER_RW( 0x7e9020ac )
289 #define HDMI_CTS_0_MASK 0x000fffff
290 #define HDMI_CTS_0_WIDTH 20
291 #define HDMI_CTS_0_RESET 0000000000
292 #define HDMI_CTS_1 HW_REGISTER_RW( 0x7e9020b0 )
293 #define HDMI_CTS_1_MASK 0x000fffff
294 #define HDMI_CTS_1_WIDTH 20
295 #define HDMI_CTS_1_RESET 0000000000
296 #define HDMI_CTS_PERIOD_0 HW_REGISTER_RW( 0x7e9020b4 )
297 #define HDMI_CTS_PERIOD_0_MASK 0xff0fffff
298 #define HDMI_CTS_PERIOD_0_WIDTH 32
299 #define HDMI_CTS_PERIOD_0_RESET 0x010124f8
300 #define HDMI_CTS_PERIOD_1 HW_REGISTER_RW( 0x7e9020b8 )
301 #define HDMI_CTS_PERIOD_1_MASK 0xff0fffff
302 #define HDMI_CTS_PERIOD_1_WIDTH 32
303 #define HDMI_CTS_PERIOD_1_RESET 0x010124f8
304 #define HDMI_BCH_CONFIGURATION HW_REGISTER_RW( 0x7e9020bc )
305 #define HDMI_BCH_CONFIGURATION_MASK 0x000001ff
306 #define HDMI_BCH_CONFIGURATION_WIDTH 9
307 #define HDMI_BCH_CONFIGURATION_RESET 0x00000083
308 #define HDMI_SCHEDULER_CONTROL HW_REGISTER_RW( 0x7e9020c0 )
309 #define HDMI_SCHEDULER_CONTROL_MASK 0x003fff7f
310 #define HDMI_SCHEDULER_CONTROL_WIDTH 22
311 #define HDMI_SCHEDULER_CONTROL_RESET 0x000cb008
312 #define HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_BITS 21:18
313 #define HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_SET 0x003c0000
314 #define HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_CLR 0xffc3ffff
315 #define HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_MSB 21
316 #define HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_LSB 18
317 #define HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_BITS 17:17
318 #define HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_SET 0x00020000
319 #define HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_CLR 0xfffdffff
320 #define HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_MSB 17
321 #define HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_LSB 17
322 #define HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_BITS 16:16
323 #define HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_SET 0x00010000
324 #define HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_CLR 0xfffeffff
325 #define HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_MSB 16
326 #define HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_LSB 16
327 #define HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_BITS 15:15
328 #define HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_SET 0x00008000
329 #define HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_CLR 0xffff7fff
330 #define HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_MSB 15
331 #define HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_LSB 15
332 #define HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_BITS 14:14
333 #define HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_SET 0x00004000
334 #define HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_CLR 0xffffbfff
335 #define HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_MSB 14
336 #define HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_LSB 14
337 #define HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_BITS 13:8
338 #define HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_SET 0x00003f00
339 #define HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_CLR 0xffffc0ff
340 #define HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_MSB 13
341 #define HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_LSB 8
342 #define HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_BITS 6:6
343 #define HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_SET 0x00000040
344 #define HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_CLR 0xffffffbf
345 #define HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_MSB 6
346 #define HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_LSB 6
347 #define HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_BITS 5:5
348 #define HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_SET 0x00000020
349 #define HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_CLR 0xffffffdf
350 #define HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_MSB 5
351 #define HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_LSB 5
352 #define HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_BITS 4:4
353 #define HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_SET 0x00000010
354 #define HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_CLR 0xffffffef
355 #define HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_MSB 4
356 #define HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_LSB 4
357 #define HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_BITS 3:3
358 #define HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_SET 0x00000008
359 #define HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_CLR 0xfffffff7
360 #define HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_MSB 3
361 #define HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_LSB 3
362 #define HDMI_SCHEDULER_CONTROL_USE_PREDICTS_BITS 2:2
363 #define HDMI_SCHEDULER_CONTROL_USE_PREDICTS_SET 0x00000004
364 #define HDMI_SCHEDULER_CONTROL_USE_PREDICTS_CLR 0xfffffffb
365 #define HDMI_SCHEDULER_CONTROL_USE_PREDICTS_MSB 2
366 #define HDMI_SCHEDULER_CONTROL_USE_PREDICTS_LSB 2
367 #define HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_BITS 1:1
368 #define HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_SET 0x00000002
369 #define HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_CLR 0xfffffffd
370 #define HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_MSB 1
371 #define HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_LSB 1
372 #define HDMI_SCHEDULER_CONTROL_MODE_REQ_BITS 0:0
373 #define HDMI_SCHEDULER_CONTROL_MODE_REQ_SET 0x00000001
374 #define HDMI_SCHEDULER_CONTROL_MODE_REQ_CLR 0xfffffffe
375 #define HDMI_SCHEDULER_CONTROL_MODE_REQ_MSB 0
376 #define HDMI_SCHEDULER_CONTROL_MODE_REQ_LSB 0
377 #define HDMI_HORZA HW_REGISTER_RW( 0x7e9020c4 )
378 #define HDMI_HORZA_MASK 0x00007fff
379 #define HDMI_HORZA_WIDTH 15
380 #define HDMI_HORZA_RESET 0x00000280
381 #define HDMI_HORZA_MANUAL_VPOL_BITS 14:14
382 #define HDMI_HORZA_MANUAL_VPOL_SET 0x00004000
383 #define HDMI_HORZA_MANUAL_VPOL_CLR 0xffffbfff
384 #define HDMI_HORZA_MANUAL_VPOL_MSB 14
385 #define HDMI_HORZA_MANUAL_VPOL_LSB 14
386 #define HDMI_HORZA_MANUAL_HPOL_BITS 13:13
387 #define HDMI_HORZA_MANUAL_HPOL_SET 0x00002000
388 #define HDMI_HORZA_MANUAL_HPOL_CLR 0xffffdfff
389 #define HDMI_HORZA_MANUAL_HPOL_MSB 13
390 #define HDMI_HORZA_MANUAL_HPOL_LSB 13
391 #define HDMI_HORZA_MANUAL_HAP_BITS 12:0
392 #define HDMI_HORZA_MANUAL_HAP_SET 0x00001fff
393 #define HDMI_HORZA_MANUAL_HAP_CLR 0xffffe000
394 #define HDMI_HORZA_MANUAL_HAP_MSB 12
395 #define HDMI_HORZA_MANUAL_HAP_LSB 0
396 #define HDMI_HORZB HW_REGISTER_RW( 0x7e9020c8 )
397 #define HDMI_HORZB_MASK 0x3fffffff
398 #define HDMI_HORZB_WIDTH 30
399 #define HDMI_HORZB_RESET 0x03018010
400 #define HDMI_HORZB_MANUAL_HBP_BITS 29:20
401 #define HDMI_HORZB_MANUAL_HBP_SET 0x3ff00000
402 #define HDMI_HORZB_MANUAL_HBP_CLR 0xc00fffff
403 #define HDMI_HORZB_MANUAL_HBP_MSB 29
404 #define HDMI_HORZB_MANUAL_HBP_LSB 20
405 #define HDMI_HORZB_MANUAL_HSP_BITS 19:10
406 #define HDMI_HORZB_MANUAL_HSP_SET 0x000ffc00
407 #define HDMI_HORZB_MANUAL_HSP_CLR 0xfff003ff
408 #define HDMI_HORZB_MANUAL_HSP_MSB 19
409 #define HDMI_HORZB_MANUAL_HSP_LSB 10
410 #define HDMI_HORZB_MANUAL_HFP_BITS 9:9
411 #define HDMI_HORZB_MANUAL_HFP_SET 0x00000200
412 #define HDMI_HORZB_MANUAL_HFP_CLR 0xfffffdff
413 #define HDMI_HORZB_MANUAL_HFP_MSB 9
414 #define HDMI_HORZB_MANUAL_HFP_LSB 9
415 #define HDMI_VERTA0 HW_REGISTER_RW( 0x7e9020cc )
416 #define HDMI_VERTA0_MASK 0x01ffffff
417 #define HDMI_VERTA0_WIDTH 25
418 #define HDMI_VERTA0_RESET 0x002141e0
419 #define HDMI_VERTA0_MANUAL_VSP0_BITS 24:20
420 #define HDMI_VERTA0_MANUAL_VSP0_SET 0x01f00000
421 #define HDMI_VERTA0_MANUAL_VSP0_CLR 0xfe0fffff
422 #define HDMI_VERTA0_MANUAL_VSP0_MSB 24
423 #define HDMI_VERTA0_MANUAL_VSP0_LSB 20
424 #define HDMI_VERTA0_MANUAL_VFP0_BITS 19:13
425 #define HDMI_VERTA0_MANUAL_VFP0_SET 0x000fe000
426 #define HDMI_VERTA0_MANUAL_VFP0_CLR 0xfff01fff
427 #define HDMI_VERTA0_MANUAL_VFP0_MSB 19
428 #define HDMI_VERTA0_MANUAL_VFP0_LSB 13
429 #define HDMI_VERTA0_MANUAL_VAL0_BITS 12:0
430 #define HDMI_VERTA0_MANUAL_VAL0_SET 0x00001fff
431 #define HDMI_VERTA0_MANUAL_VAL0_CLR 0xffffe000
432 #define HDMI_VERTA0_MANUAL_VAL0_MSB 12
433 #define HDMI_VERTA0_MANUAL_VAL0_LSB 0
434 #define HDMI_VERTB0 HW_REGISTER_RW( 0x7e9020d0 )
435 #define HDMI_VERTB0_MASK 0x003fffff
436 #define HDMI_VERTB0_WIDTH 22
437 #define HDMI_VERTB0_RESET 0x00000021
438 #define HDMI_VERTB0_MANUAL_VSPO0_BITS 21:9
439 #define HDMI_VERTB0_MANUAL_VSPO0_SET 0x003ffe00
440 #define HDMI_VERTB0_MANUAL_VSPO0_CLR 0xffc001ff
441 #define HDMI_VERTB0_MANUAL_VSPO0_MSB 21
442 #define HDMI_VERTB0_MANUAL_VSPO0_LSB 9
443 #define HDMI_VERTB0_MANUAL_VBP0_BITS 8:8
444 #define HDMI_VERTB0_MANUAL_VBP0_SET 0x00000100
445 #define HDMI_VERTB0_MANUAL_VBP0_CLR 0xfffffeff
446 #define HDMI_VERTB0_MANUAL_VBP0_MSB 8
447 #define HDMI_VERTB0_MANUAL_VBP0_LSB 8
448 #define HDMI_VERTA1 HW_REGISTER_RW( 0x7e9020d4 )
449 #define HDMI_VERTA1_MASK 0x01ffffff
450 #define HDMI_VERTA1_WIDTH 25
451 #define HDMI_VERTA1_RESET 0x002141e0
452 #define HDMI_VERTA1_MANUAL_VSP1_BITS 24:20
453 #define HDMI_VERTA1_MANUAL_VSP1_SET 0x01f00000
454 #define HDMI_VERTA1_MANUAL_VSP1_CLR 0xfe0fffff
455 #define HDMI_VERTA1_MANUAL_VSP1_MSB 24
456 #define HDMI_VERTA1_MANUAL_VSP1_LSB 20
457 #define HDMI_VERTA1_MANUAL_VFP1_BITS 19:13
458 #define HDMI_VERTA1_MANUAL_VFP1_SET 0x000fe000
459 #define HDMI_VERTA1_MANUAL_VFP1_CLR 0xfff01fff
460 #define HDMI_VERTA1_MANUAL_VFP1_MSB 19
461 #define HDMI_VERTA1_MANUAL_VFP1_LSB 13
462 #define HDMI_VERTA1_MANUAL_VAL1_BITS 12:0
463 #define HDMI_VERTA1_MANUAL_VAL1_SET 0x00001fff
464 #define HDMI_VERTA1_MANUAL_VAL1_CLR 0xffffe000
465 #define HDMI_VERTA1_MANUAL_VAL1_MSB 12
466 #define HDMI_VERTA1_MANUAL_VAL1_LSB 0
467 #define HDMI_VERTB1 HW_REGISTER_RW( 0x7e9020d8 )
468 #define HDMI_VERTB1_MASK 0x003fffff
469 #define HDMI_VERTB1_WIDTH 22
470 #define HDMI_VERTB1_RESET 0x00000021
471 #define HDMI_VERTB1_MANUAL_VSPO1_BITS 21:9
472 #define HDMI_VERTB1_MANUAL_VSPO1_SET 0x003ffe00
473 #define HDMI_VERTB1_MANUAL_VSPO1_CLR 0xffc001ff
474 #define HDMI_VERTB1_MANUAL_VSPO1_MSB 21
475 #define HDMI_VERTB1_MANUAL_VSPO1_LSB 9
476 #define HDMI_VERTB1_MANUAL_VBP1_BITS 8:8
477 #define HDMI_VERTB1_MANUAL_VBP1_SET 0x00000100
478 #define HDMI_VERTB1_MANUAL_VBP1_CLR 0xfffffeff
479 #define HDMI_VERTB1_MANUAL_VBP1_MSB 8
480 #define HDMI_VERTB1_MANUAL_VBP1_LSB 8
481 #define HDMI_TEST HW_REGISTER_RW( 0x7e9020dc )
482 #define HDMI_TEST_MASK 0x00000fff
483 #define HDMI_TEST_WIDTH 12
484 #define HDMI_TEST_RESET 0000000000
485 #define HDMI_MBIST_TM HW_REGISTER_RW( 0x7e9020e0 )
486 #define HDMI_MBIST_TM_MASK 0x00ffffff
487 #define HDMI_MBIST_TM_WIDTH 24
488 #define HDMI_MBIST_TM_RESET 0000000000
489 #define HDMI_MISC_CONTROL HW_REGISTER_RW( 0x7e9020e4 )
490 #define HDMI_MISC_CONTROL_MASK 0x7fffffff
491 #define HDMI_MISC_CONTROL_WIDTH 31
492 #define HDMI_MISC_CONTROL_RESET 0000000000
493 #define HDMI_CEC_CNTRL_1 HW_REGISTER_RW( 0x7e9020e8 )
494 #define HDMI_CEC_CNTRL_1_MASK 0xffffffff
495 #define HDMI_CEC_CNTRL_1_WIDTH 32
496 #define HDMI_CEC_CNTRL_1_RESET 0x0000e7be
497 #define HDMI_CEC_CNTRL_2 HW_REGISTER_RW( 0x7e9020ec )
498 #define HDMI_CEC_CNTRL_2_MASK 0x7fffffff
499 #define HDMI_CEC_CNTRL_2_WIDTH 31
500 #define HDMI_CEC_CNTRL_2_RESET 0x508d63d5
501 #define HDMI_CEC_CNTRL_3 HW_REGISTER_RW( 0x7e9020f0 )
502 #define HDMI_CEC_CNTRL_3_MASK 0xffffffff
503 #define HDMI_CEC_CNTRL_3_WIDTH 32
504 #define HDMI_CEC_CNTRL_3_RESET 0x96826f5c
505 #define HDMI_CEC_CNTRL_4 HW_REGISTER_RW( 0x7e9020f4 )
506 #define HDMI_CEC_CNTRL_4_MASK 0xffffffff
507 #define HDMI_CEC_CNTRL_4_WIDTH 32
508 #define HDMI_CEC_CNTRL_4_RESET 0xead4c3be
509 #define HDMI_CEC_CNTRL_5 HW_REGISTER_RW( 0x7e9020f8 )
510 #define HDMI_CEC_CNTRL_5_MASK 0x0fffffff
511 #define HDMI_CEC_CNTRL_5_WIDTH 28
512 #define HDMI_CEC_CNTRL_5_RESET 0x004cfff5
513 #define HDMI_CEC_TX_DATA_1 HW_REGISTER_RW( 0x7e9020fc )
514 #define HDMI_CEC_TX_DATA_1_MASK 0xffffffff
515 #define HDMI_CEC_TX_DATA_1_WIDTH 32
516 #define HDMI_CEC_TX_DATA_1_RESET 0000000000
517 #define HDMI_CEC_TX_DATA_2 HW_REGISTER_RW( 0x7e902100 )
518 #define HDMI_CEC_TX_DATA_2_MASK 0xffffffff
519 #define HDMI_CEC_TX_DATA_2_WIDTH 32
520 #define HDMI_CEC_TX_DATA_2_RESET 0000000000
521 #define HDMI_CEC_TX_DATA_3 HW_REGISTER_RW( 0x7e902104 )
522 #define HDMI_CEC_TX_DATA_3_MASK 0xffffffff
523 #define HDMI_CEC_TX_DATA_3_WIDTH 32
524 #define HDMI_CEC_TX_DATA_3_RESET 0000000000
525 #define HDMI_CEC_TX_DATA_4 HW_REGISTER_RW( 0x7e902108 )
526 #define HDMI_CEC_TX_DATA_4_MASK 0xffffffff
527 #define HDMI_CEC_TX_DATA_4_WIDTH 32
528 #define HDMI_CEC_TX_DATA_4_RESET 0000000000
529 #define HDMI_CEC_RX_DATA_1 HW_REGISTER_RW( 0x7e90210c )
530 #define HDMI_CEC_RX_DATA_1_MASK 0xffffffff
531 #define HDMI_CEC_RX_DATA_1_WIDTH 32
532 #define HDMI_CEC_RX_DATA_1_RESET 0000000000
533 #define HDMI_CEC_RX_DATA_2 HW_REGISTER_RW( 0x7e902110 )
534 #define HDMI_CEC_RX_DATA_2_MASK 0xffffffff
535 #define HDMI_CEC_RX_DATA_2_WIDTH 32
536 #define HDMI_CEC_RX_DATA_2_RESET 0000000000
537 #define HDMI_CEC_RX_DATA_3 HW_REGISTER_RW( 0x7e902114 )
538 #define HDMI_CEC_RX_DATA_3_MASK 0xffffffff
539 #define HDMI_CEC_RX_DATA_3_WIDTH 32
540 #define HDMI_CEC_RX_DATA_3_RESET 0000000000
541 #define HDMI_CEC_RX_DATA_4 HW_REGISTER_RW( 0x7e902118 )
542 #define HDMI_CEC_RX_DATA_4_MASK 0xffffffff
543 #define HDMI_CEC_RX_DATA_4_WIDTH 32
544 #define HDMI_CEC_RX_DATA_4_RESET 0000000000
545 #define HDMI_PACKET_FIFO_CTL HW_REGISTER_RW( 0x7e90211c )
546 #define HDMI_PACKET_FIFO_CTL_MASK 0x00000003
547 #define HDMI_PACKET_FIFO_CTL_WIDTH 2
548 #define HDMI_PACKET_FIFO_CTL_RESET 0000000000
549 #define HDMI_PACKET_FIFO_CFG HW_REGISTER_RW( 0x7e902120 )
550 #define HDMI_PACKET_FIFO_CFG_MASK 0x00000001
551 #define HDMI_PACKET_FIFO_CFG_WIDTH 1
552 #define HDMI_PACKET_FIFO_CFG_RESET 0000000000
553 #define HDMI_PACKET_FIFO_STATUS HW_REGISTER_RW( 0x7e902124 )
554 #define HDMI_PACKET_FIFO_STATUS_MASK 0x03073f1f
555 #define HDMI_PACKET_FIFO_STATUS_WIDTH 26
556 #define HDMI_PACKET_FIFO_STATUS_RESET 0x03010000
557 #define HDMI_DVO_TIMING_ADJUST_A HW_REGISTER_RW( 0x7e902128 )
558 #define HDMI_DVO_TIMING_ADJUST_A_MASK 0x000fffff
559 #define HDMI_DVO_TIMING_ADJUST_A_WIDTH 20
560 #define HDMI_DVO_TIMING_ADJUST_A_RESET 0x00088888
561 #define HDMI_DVO_TIMING_ADJUST_B HW_REGISTER_RW( 0x7e90212c )
562 #define HDMI_DVO_TIMING_ADJUST_B_MASK 0xffffffff
563 #define HDMI_DVO_TIMING_ADJUST_B_WIDTH 32
564 #define HDMI_DVO_TIMING_ADJUST_B_RESET 0x88888888
565 #define HDMI_DVO_TIMING_ADJUST_C HW_REGISTER_RW( 0x7e902130 )
566 #define HDMI_DVO_TIMING_ADJUST_C_MASK 0xffffffff
567 #define HDMI_DVO_TIMING_ADJUST_C_WIDTH 32
568 #define HDMI_DVO_TIMING_ADJUST_C_RESET 0x88888888
569 #define HDMI_DVO_TIMING_ADJUST_D HW_REGISTER_RW( 0x7e902134 )
570 #define HDMI_DVO_TIMING_ADJUST_D_MASK 0xffffffff
571 #define HDMI_DVO_TIMING_ADJUST_D_WIDTH 32
572 #define HDMI_DVO_TIMING_ADJUST_D_RESET 0x88888888
573 #define HDMI_DETECTED_HORZA HW_REGISTER_RW( 0x7e902138 )
574 #define HDMI_DETECTED_HORZA_MASK 0x00007fff
575 #define HDMI_DETECTED_HORZA_WIDTH 15
576 #define HDMI_DETECTED_HORZA_RESET 0x00000280
577 #define HDMI_DETECTED_HORZA_MANUAL_VPOL_BITS 14:14
578 #define HDMI_DETECTED_HORZA_MANUAL_VPOL_SET 0x00004000
579 #define HDMI_DETECTED_HORZA_MANUAL_VPOL_CLR 0xffffbfff
580 #define HDMI_DETECTED_HORZA_MANUAL_VPOL_MSB 14
581 #define HDMI_DETECTED_HORZA_MANUAL_VPOL_LSB 14
582 #define HDMI_DETECTED_HORZA_MANUAL_HPOL_BITS 13:13
583 #define HDMI_DETECTED_HORZA_MANUAL_HPOL_SET 0x00002000
584 #define HDMI_DETECTED_HORZA_MANUAL_HPOL_CLR 0xffffdfff
585 #define HDMI_DETECTED_HORZA_MANUAL_HPOL_MSB 13
586 #define HDMI_DETECTED_HORZA_MANUAL_HPOL_LSB 13
587 #define HDMI_DETECTED_HORZA_MANUAL_HAP_BITS 12:0
588 #define HDMI_DETECTED_HORZA_MANUAL_HAP_SET 0x00001fff
589 #define HDMI_DETECTED_HORZA_MANUAL_HAP_CLR 0xffffe000
590 #define HDMI_DETECTED_HORZA_MANUAL_HAP_MSB 12
591 #define HDMI_DETECTED_HORZA_MANUAL_HAP_LSB 0
592 #define HDMI_DETECTED_HORZB HW_REGISTER_RW( 0x7e90213c )
593 #define HDMI_DETECTED_HORZB_MASK 0x3ffffe00
594 #define HDMI_DETECTED_HORZB_WIDTH 30
595 #define HDMI_DETECTED_HORZB_RESET 0x03018010
596 #define HDMI_DETECTED_HORZB_MANUAL_HBP_BITS 29:20
597 #define HDMI_DETECTED_HORZB_MANUAL_HBP_SET 0x3ff00000
598 #define HDMI_DETECTED_HORZB_MANUAL_HBP_CLR 0xc00fffff
599 #define HDMI_DETECTED_HORZB_MANUAL_HBP_MSB 29
600 #define HDMI_DETECTED_HORZB_MANUAL_HBP_LSB 20
601 #define HDMI_DETECTED_HORZB_MANUAL_HSP_BITS 19:10
602 #define HDMI_DETECTED_HORZB_MANUAL_HSP_SET 0x000ffc00
603 #define HDMI_DETECTED_HORZB_MANUAL_HSP_CLR 0xfff003ff
604 #define HDMI_DETECTED_HORZB_MANUAL_HSP_MSB 19
605 #define HDMI_DETECTED_HORZB_MANUAL_HSP_LSB 10
606 #define HDMI_DETECTED_HORZB_MANUAL_HFP_BITS 9:9
607 #define HDMI_DETECTED_HORZB_MANUAL_HFP_SET 0x00000200
608 #define HDMI_DETECTED_HORZB_MANUAL_HFP_CLR 0xfffffdff
609 #define HDMI_DETECTED_HORZB_MANUAL_HFP_MSB 9
610 #define HDMI_DETECTED_HORZB_MANUAL_HFP_LSB 9
611 #define HDMI_DETECTED_VERTA0 HW_REGISTER_RW( 0x7e902140 )
612 #define HDMI_DETECTED_VERTA0_MASK 0x01ffffff
613 #define HDMI_DETECTED_VERTA0_WIDTH 25
614 #define HDMI_DETECTED_VERTA0_RESET 0x002141e0
615 #define HDMI_DETECTED_VERTA0_MANUAL_VSP0_BITS 24:20
616 #define HDMI_DETECTED_VERTA0_MANUAL_VSP0_SET 0x01f00000
617 #define HDMI_DETECTED_VERTA0_MANUAL_VSP0_CLR 0xfe0fffff
618 #define HDMI_DETECTED_VERTA0_MANUAL_VSP0_MSB 24
619 #define HDMI_DETECTED_VERTA0_MANUAL_VSP0_LSB 20
620 #define HDMI_DETECTED_VERTA0_MANUAL_VFP0_BITS 19:13
621 #define HDMI_DETECTED_VERTA0_MANUAL_VFP0_SET 0x000fe000
622 #define HDMI_DETECTED_VERTA0_MANUAL_VFP0_CLR 0xfff01fff
623 #define HDMI_DETECTED_VERTA0_MANUAL_VFP0_MSB 19
624 #define HDMI_DETECTED_VERTA0_MANUAL_VFP0_LSB 13
625 #define HDMI_DETECTED_VERTA0_MANUAL_VAL0_BITS 12:0
626 #define HDMI_DETECTED_VERTA0_MANUAL_VAL0_SET 0x00001fff
627 #define HDMI_DETECTED_VERTA0_MANUAL_VAL0_CLR 0xffffe000
628 #define HDMI_DETECTED_VERTA0_MANUAL_VAL0_MSB 12
629 #define HDMI_DETECTED_VERTA0_MANUAL_VAL0_LSB 0
630 #define HDMI_DETECTED_VERTB0 HW_REGISTER_RW( 0x7e902144 )
631 #define HDMI_DETECTED_VERTB0_MASK 0x003fff00
632 #define HDMI_DETECTED_VERTB0_WIDTH 22
633 #define HDMI_DETECTED_VERTB0_RESET 0x00000021
634 #define HDMI_DETECTED_VERTB0_MANUAL_VSPO0_BITS 21:9
635 #define HDMI_DETECTED_VERTB0_MANUAL_VSPO0_SET 0x003ffe00
636 #define HDMI_DETECTED_VERTB0_MANUAL_VSPO0_CLR 0xffc001ff
637 #define HDMI_DETECTED_VERTB0_MANUAL_VSPO0_MSB 21
638 #define HDMI_DETECTED_VERTB0_MANUAL_VSPO0_LSB 9
639 #define HDMI_DETECTED_VERTB0_MANUAL_VBP0_BITS 8:8
640 #define HDMI_DETECTED_VERTB0_MANUAL_VBP0_SET 0x00000100
641 #define HDMI_DETECTED_VERTB0_MANUAL_VBP0_CLR 0xfffffeff
642 #define HDMI_DETECTED_VERTB0_MANUAL_VBP0_MSB 8
643 #define HDMI_DETECTED_VERTB0_MANUAL_VBP0_LSB 8
644 #define HDMI_DETECTED_VERTA1 HW_REGISTER_RW( 0x7e902148 )
645 #define HDMI_DETECTED_VERTA1_MASK 0x01ffffff
646 #define HDMI_DETECTED_VERTA1_WIDTH 25
647 #define HDMI_DETECTED_VERTA1_RESET 0x002141e0
648 #define HDMI_DETECTED_VERTA1_MANUAL_VSP1_BITS 24:20
649 #define HDMI_DETECTED_VERTA1_MANUAL_VSP1_SET 0x01f00000
650 #define HDMI_DETECTED_VERTA1_MANUAL_VSP1_CLR 0xfe0fffff
651 #define HDMI_DETECTED_VERTA1_MANUAL_VSP1_MSB 24
652 #define HDMI_DETECTED_VERTA1_MANUAL_VSP1_LSB 20
653 #define HDMI_DETECTED_VERTA1_MANUAL_VFP1_BITS 19:13
654 #define HDMI_DETECTED_VERTA1_MANUAL_VFP1_SET 0x000fe000
655 #define HDMI_DETECTED_VERTA1_MANUAL_VFP1_CLR 0xfff01fff
656 #define HDMI_DETECTED_VERTA1_MANUAL_VFP1_MSB 19
657 #define HDMI_DETECTED_VERTA1_MANUAL_VFP1_LSB 13
658 #define HDMI_DETECTED_VERTA1_MANUAL_VAL1_BITS 12:0
659 #define HDMI_DETECTED_VERTA1_MANUAL_VAL1_SET 0x00001fff
660 #define HDMI_DETECTED_VERTA1_MANUAL_VAL1_CLR 0xffffe000
661 #define HDMI_DETECTED_VERTA1_MANUAL_VAL1_MSB 12
662 #define HDMI_DETECTED_VERTA1_MANUAL_VAL1_LSB 0
663 #define HDMI_DETECTED_VERTB1 HW_REGISTER_RW( 0x7e90214c )
664 #define HDMI_DETECTED_VERTB1_MASK 0x003fff00
665 #define HDMI_DETECTED_VERTB1_WIDTH 22
666 #define HDMI_DETECTED_VERTB1_RESET 0x00000021
667 #define HDMI_DETECTED_VERTB1_MANUAL_VSPO1_BITS 21:9
668 #define HDMI_DETECTED_VERTB1_MANUAL_VSPO1_SET 0x003ffe00
669 #define HDMI_DETECTED_VERTB1_MANUAL_VSPO1_CLR 0xffc001ff
670 #define HDMI_DETECTED_VERTB1_MANUAL_VSPO1_MSB 21
671 #define HDMI_DETECTED_VERTB1_MANUAL_VSPO1_LSB 9
672 #define HDMI_DETECTED_VERTB1_MANUAL_VBP1_BITS 8:8
673 #define HDMI_DETECTED_VERTB1_MANUAL_VBP1_SET 0x00000100
674 #define HDMI_DETECTED_VERTB1_MANUAL_VBP1_CLR 0xfffffeff
675 #define HDMI_DETECTED_VERTB1_MANUAL_VBP1_MSB 8
676 #define HDMI_DETECTED_VERTB1_MANUAL_VBP1_LSB 8
677 #define HDMI_13_AUDIO_CFG_1 HW_REGISTER_RW( 0x7e902150 )
678 #define HDMI_13_AUDIO_CFG_1_MASK 0x000003ff
679 #define HDMI_13_AUDIO_CFG_1_WIDTH 10
680 #define HDMI_13_AUDIO_CFG_1_RESET 0x000000c8
681 #define HDMI_13_AUDIO_STATUS_1 HW_REGISTER_RW( 0x7e902154 )
682 #define HDMI_13_AUDIO_STATUS_1_MASK 0x00000001
683 #define HDMI_13_AUDIO_STATUS_1_WIDTH 1
684 #define HDMI_13_AUDIO_STATUS_1_RESET 0000000000
685 #define HDMI_HBR_AUDIO_PACKET_HEADER HW_REGISTER_RW( 0x7e902158 )
686 #define HDMI_HBR_AUDIO_PACKET_HEADER_MASK 0x000fffff
687 #define HDMI_HBR_AUDIO_PACKET_HEADER_WIDTH 20
688 #define HDMI_HBR_AUDIO_PACKET_HEADER_RESET 0x00000009
689 #define HDMI_POSTING_MASTER HW_REGISTER_RW( 0x7e90215c )
690 #define HDMI_POSTING_MASTER_MASK 0x000000ff
691 #define HDMI_POSTING_MASTER_WIDTH 8
692 #define HDMI_POSTING_MASTER_RESET 0x000000ff
693 #define HDMI_TX_PHY_TX_PHY_RESET_CTL HW_REGISTER_RW( 0x7e9022c0 )
694 #define HDMI_TX_PHY_TX_PHY_RESET_CTL_MASK 0xffffffff
695 #define HDMI_TX_PHY_TX_PHY_RESET_CTL_WIDTH 32
696 #define HDMI_TX_PHY_TX_PHY_RESET_CTL_RESET 0x003f01ff
697 #define HDMI_TX_PHY_TX_PHY_CTL_0 HW_REGISTER_RW( 0x7e9022c4 )
698 #define HDMI_TX_PHY_TX_PHY_CTL_0_MASK 0xffffffff
699 #define HDMI_TX_PHY_TX_PHY_CTL_0_WIDTH 32
700 #define HDMI_TX_PHY_TX_PHY_CTL_0_RESET 0x8e000000
701 #define HDMI_TX_PHY_TX_PHY_CTL_1 HW_REGISTER_RW( 0x7e9022c8 )
702 #define HDMI_TX_PHY_TX_PHY_CTL_1_MASK 0xffffffff
703 #define HDMI_TX_PHY_TX_PHY_CTL_1_WIDTH 32
704 #define HDMI_TX_PHY_TX_PHY_CTL_1_RESET 0x0404a808
705 #define HDMI_TX_PHY_TX_PHY_CTL_2 HW_REGISTER_RW( 0x7e9022cc )
706 #define HDMI_TX_PHY_TX_PHY_CTL_2_MASK 0xffffffff
707 #define HDMI_TX_PHY_TX_PHY_CTL_2_WIDTH 32
708 #define HDMI_TX_PHY_TX_PHY_CTL_2_RESET 0x00a63004
709 #define HDMI_TX_PHY_TX_PHY_PLL_CFG HW_REGISTER_RW( 0x7e9022d0 )
710 #define HDMI_TX_PHY_TX_PHY_PLL_CFG_MASK 0xc3fbffff
711 #define HDMI_TX_PHY_TX_PHY_PLL_CFG_WIDTH 32
712 #define HDMI_TX_PHY_TX_PHY_PLL_CFG_RESET 0x07f80112
713 #define HDMI_TX_PHY_TX_PHY_TMDS_CFG HW_REGISTER_RW( 0x7e9022d4 )
714 #define HDMI_TX_PHY_TX_PHY_TMDS_CFG_MASK 0xffffffff
715 #define HDMI_TX_PHY_TX_PHY_TMDS_CFG_WIDTH 32
716 #define HDMI_TX_PHY_TX_PHY_TMDS_CFG_RESET 0x0000001f
717 #define HDMI_TX_PHY_TX_PHY_STATUS HW_REGISTER_RW( 0x7e9022d8 )
718 #define HDMI_TX_PHY_TX_PHY_STATUS_MASK 0xffffffff
719 #define HDMI_TX_PHY_TX_PHY_STATUS_WIDTH 32
720 #define HDMI_TX_PHY_TX_PHY_STATUS_RESET 0000000000
721 #define HDMI_TX_PHY_SPREAD_SPECTRUM HW_REGISTER_RW( 0x7e9022dc )
722 #define HDMI_TX_PHY_SPREAD_SPECTRUM_MASK 0xffffffff
723 #define HDMI_TX_PHY_SPREAD_SPECTRUM_WIDTH 32
724 #define HDMI_TX_PHY_SPREAD_SPECTRUM_RESET 0x00003c00
725 #define HDMI_TX_PHY_TX_PHY_SPARE HW_REGISTER_RW( 0x7e9022e0 )
726 #define HDMI_TX_PHY_TX_PHY_SPARE_MASK 0xffffffff
727 #define HDMI_TX_PHY_TX_PHY_SPARE_WIDTH 32
728 #define HDMI_TX_PHY_TX_PHY_SPARE_RESET 0xffff0000
729 #define HDMI_CPU_STATUS HW_REGISTER_RW( 0x7e902340 )
730 #define HDMI_CPU_STATUS_MASK 0xffffffff
731 #define HDMI_CPU_STATUS_WIDTH 32
732 #define HDMI_CPU_STATUS_RESET 0000000000
733 #define HDMI_CPU_SET HW_REGISTER_RW( 0x7e902344 )
734 #define HDMI_CPU_SET_MASK 0xffffffff
735 #define HDMI_CPU_SET_WIDTH 32
736 #define HDMI_CPU_SET_RESET 0000000000
737 #define HDMI_CPU_CLEAR HW_REGISTER_RW( 0x7e902348 )
738 #define HDMI_CPU_CLEAR_MASK 0xffffffff
739 #define HDMI_CPU_CLEAR_WIDTH 32
740 #define HDMI_CPU_CLEAR_RESET 0000000000
741 #define HDMI_CPU_MASK_STATUS HW_REGISTER_RW( 0x7e90234c )
742 #define HDMI_CPU_MASK_STATUS_MASK 0xffffffff
743 #define HDMI_CPU_MASK_STATUS_WIDTH 32
744 #define HDMI_CPU_MASK_STATUS_RESET 0x0001ffff
745 #define HDMI_CPU_MASK_SET HW_REGISTER_RW( 0x7e902350 )
746 #define HDMI_CPU_MASK_SET_MASK 0xffffffff
747 #define HDMI_CPU_MASK_SET_WIDTH 32
748 #define HDMI_CPU_MASK_SET_RESET 0x0001ffff
749 #define HDMI_CPU_MASK_CLEAR HW_REGISTER_RW( 0x7e902354 )
750 #define HDMI_CPU_MASK_CLEAR_MASK 0xffffffff
751 #define HDMI_CPU_MASK_CLEAR_WIDTH 32
752 #define HDMI_CPU_MASK_CLEAR_RESET 0x0001ffff
753 #define HDMI_RAM_GCP_0 HW_REGISTER_RW( 0x7e902400 )
754 #define HDMI_RAM_GCP_0_MASK 0xffffffff
755 #define HDMI_RAM_GCP_0_WIDTH 32
756 #define HDMI_RAM_GCP_0_RESET 0000000000
757 #define HDMI_RAM_GCP_1 HW_REGISTER_RW( 0x7e902404 )
758 #define HDMI_RAM_GCP_1_MASK 0xffffffff
759 #define HDMI_RAM_GCP_1_WIDTH 32
760 #define HDMI_RAM_GCP_1_RESET 0000000000
761 #define HDMI_RAM_GCP_2 HW_REGISTER_RW( 0x7e902408 )
762 #define HDMI_RAM_GCP_2_MASK 0xffffffff
763 #define HDMI_RAM_GCP_2_WIDTH 32
764 #define HDMI_RAM_GCP_2_RESET 0000000000
765 #define HDMI_RAM_GCP_3 HW_REGISTER_RW( 0x7e90240c )
766 #define HDMI_RAM_GCP_3_MASK 0xffffffff
767 #define HDMI_RAM_GCP_3_WIDTH 32
768 #define HDMI_RAM_GCP_3_RESET 0000000000
769 #define HDMI_RAM_GCP_4 HW_REGISTER_RW( 0x7e902410 )
770 #define HDMI_RAM_GCP_4_MASK 0xffffffff
771 #define HDMI_RAM_GCP_4_WIDTH 32
772 #define HDMI_RAM_GCP_4_RESET 0000000000
773 #define HDMI_RAM_GCP_5 HW_REGISTER_RW( 0x7e902414 )
774 #define HDMI_RAM_GCP_5_MASK 0xffffffff
775 #define HDMI_RAM_GCP_5_WIDTH 32
776 #define HDMI_RAM_GCP_5_RESET 0000000000
777 #define HDMI_RAM_GCP_6 HW_REGISTER_RW( 0x7e902418 )
778 #define HDMI_RAM_GCP_6_MASK 0xffffffff
779 #define HDMI_RAM_GCP_6_WIDTH 32
780 #define HDMI_RAM_GCP_6_RESET 0000000000
781 #define HDMI_RAM_GCP_7 HW_REGISTER_RW( 0x7e90241c )
782 #define HDMI_RAM_GCP_7_MASK 0xffffffff
783 #define HDMI_RAM_GCP_7_WIDTH 32
784 #define HDMI_RAM_GCP_7_RESET 0000000000
785 #define HDMI_RAM_GCP_8 HW_REGISTER_RW( 0x7e902420 )
786 #define HDMI_RAM_GCP_8_MASK 0xffffffff
787 #define HDMI_RAM_GCP_8_WIDTH 32
788 #define HDMI_RAM_GCP_8_RESET 0000000000
789 #define HDMI_RAM_PACKET_1_0 HW_REGISTER_RW( 0x7e902424 )
790 #define HDMI_RAM_PACKET_1_0_MASK 0xffffffff
791 #define HDMI_RAM_PACKET_1_0_WIDTH 32
792 #define HDMI_RAM_PACKET_1_0_RESET 0000000000
793 #define HDMI_RAM_PACKET_1_1 HW_REGISTER_RW( 0x7e902428 )
794 #define HDMI_RAM_PACKET_1_1_MASK 0xffffffff
795 #define HDMI_RAM_PACKET_1_1_WIDTH 32
796 #define HDMI_RAM_PACKET_1_1_RESET 0000000000
797 #define HDMI_RAM_PACKET_1_2 HW_REGISTER_RW( 0x7e90242c )
798 #define HDMI_RAM_PACKET_1_2_MASK 0xffffffff
799 #define HDMI_RAM_PACKET_1_2_WIDTH 32
800 #define HDMI_RAM_PACKET_1_2_RESET 0000000000
801 #define HDMI_RAM_PACKET_1_3 HW_REGISTER_RW( 0x7e902430 )
802 #define HDMI_RAM_PACKET_1_3_MASK 0xffffffff
803 #define HDMI_RAM_PACKET_1_3_WIDTH 32
804 #define HDMI_RAM_PACKET_1_3_RESET 0000000000
805 #define HDMI_RAM_PACKET_1_4 HW_REGISTER_RW( 0x7e902434 )
806 #define HDMI_RAM_PACKET_1_4_MASK 0xffffffff
807 #define HDMI_RAM_PACKET_1_4_WIDTH 32
808 #define HDMI_RAM_PACKET_1_4_RESET 0000000000
809 #define HDMI_RAM_PACKET_1_5 HW_REGISTER_RW( 0x7e902438 )
810 #define HDMI_RAM_PACKET_1_5_MASK 0xffffffff
811 #define HDMI_RAM_PACKET_1_5_WIDTH 32
812 #define HDMI_RAM_PACKET_1_5_RESET 0000000000
813 #define HDMI_RAM_PACKET_1_6 HW_REGISTER_RW( 0x7e90243c )
814 #define HDMI_RAM_PACKET_1_6_MASK 0xffffffff
815 #define HDMI_RAM_PACKET_1_6_WIDTH 32
816 #define HDMI_RAM_PACKET_1_6_RESET 0000000000
817 #define HDMI_RAM_PACKET_1_7 HW_REGISTER_RW( 0x7e902440 )
818 #define HDMI_RAM_PACKET_1_7_MASK 0xffffffff
819 #define HDMI_RAM_PACKET_1_7_WIDTH 32
820 #define HDMI_RAM_PACKET_1_7_RESET 0000000000
821 #define HDMI_RAM_PACKET_1_8 HW_REGISTER_RW( 0x7e902444 )
822 #define HDMI_RAM_PACKET_1_8_MASK 0xffffffff
823 #define HDMI_RAM_PACKET_1_8_WIDTH 32
824 #define HDMI_RAM_PACKET_1_8_RESET 0000000000
825 #define HDMI_RAM_PACKET_2_0 HW_REGISTER_RW( 0x7e902448 )
826 #define HDMI_RAM_PACKET_2_0_MASK 0xffffffff
827 #define HDMI_RAM_PACKET_2_0_WIDTH 32
828 #define HDMI_RAM_PACKET_2_0_RESET 0000000000
829 #define HDMI_RAM_PACKET_2_1 HW_REGISTER_RW( 0x7e90244c )
830 #define HDMI_RAM_PACKET_2_1_MASK 0xffffffff
831 #define HDMI_RAM_PACKET_2_1_WIDTH 32
832 #define HDMI_RAM_PACKET_2_1_RESET 0000000000
833 #define HDMI_RAM_PACKET_2_2 HW_REGISTER_RW( 0x7e902450 )
834 #define HDMI_RAM_PACKET_2_2_MASK 0xffffffff
835 #define HDMI_RAM_PACKET_2_2_WIDTH 32
836 #define HDMI_RAM_PACKET_2_2_RESET 0000000000
837 #define HDMI_RAM_PACKET_2_3 HW_REGISTER_RW( 0x7e902454 )
838 #define HDMI_RAM_PACKET_2_3_MASK 0xffffffff
839 #define HDMI_RAM_PACKET_2_3_WIDTH 32
840 #define HDMI_RAM_PACKET_2_3_RESET 0000000000
841 #define HDMI_RAM_PACKET_2_4 HW_REGISTER_RW( 0x7e902458 )
842 #define HDMI_RAM_PACKET_2_4_MASK 0xffffffff
843 #define HDMI_RAM_PACKET_2_4_WIDTH 32
844 #define HDMI_RAM_PACKET_2_4_RESET 0000000000
845 #define HDMI_RAM_PACKET_2_5 HW_REGISTER_RW( 0x7e90245c )
846 #define HDMI_RAM_PACKET_2_5_MASK 0xffffffff
847 #define HDMI_RAM_PACKET_2_5_WIDTH 32
848 #define HDMI_RAM_PACKET_2_5_RESET 0000000000
849 #define HDMI_RAM_PACKET_2_6 HW_REGISTER_RW( 0x7e902460 )
850 #define HDMI_RAM_PACKET_2_6_MASK 0xffffffff
851 #define HDMI_RAM_PACKET_2_6_WIDTH 32
852 #define HDMI_RAM_PACKET_2_6_RESET 0000000000
853 #define HDMI_RAM_PACKET_2_7 HW_REGISTER_RW( 0x7e902464 )
854 #define HDMI_RAM_PACKET_2_7_MASK 0xffffffff
855 #define HDMI_RAM_PACKET_2_7_WIDTH 32
856 #define HDMI_RAM_PACKET_2_7_RESET 0000000000
857 #define HDMI_RAM_PACKET_2_8 HW_REGISTER_RW( 0x7e902468 )
858 #define HDMI_RAM_PACKET_2_8_MASK 0xffffffff
859 #define HDMI_RAM_PACKET_2_8_WIDTH 32
860 #define HDMI_RAM_PACKET_2_8_RESET 0000000000
861 #define HDMI_RAM_PACKET_3_0 HW_REGISTER_RW( 0x7e90246c )
862 #define HDMI_RAM_PACKET_3_0_MASK 0xffffffff
863 #define HDMI_RAM_PACKET_3_0_WIDTH 32
864 #define HDMI_RAM_PACKET_3_0_RESET 0000000000
865 #define HDMI_RAM_PACKET_3_1 HW_REGISTER_RW( 0x7e902470 )
866 #define HDMI_RAM_PACKET_3_1_MASK 0xffffffff
867 #define HDMI_RAM_PACKET_3_1_WIDTH 32
868 #define HDMI_RAM_PACKET_3_1_RESET 0000000000
869 #define HDMI_RAM_PACKET_3_2 HW_REGISTER_RW( 0x7e902474 )
870 #define HDMI_RAM_PACKET_3_2_MASK 0xffffffff
871 #define HDMI_RAM_PACKET_3_2_WIDTH 32
872 #define HDMI_RAM_PACKET_3_2_RESET 0000000000
873 #define HDMI_RAM_PACKET_3_3 HW_REGISTER_RW( 0x7e902478 )
874 #define HDMI_RAM_PACKET_3_3_MASK 0xffffffff
875 #define HDMI_RAM_PACKET_3_3_WIDTH 32
876 #define HDMI_RAM_PACKET_3_3_RESET 0000000000
877 #define HDMI_RAM_PACKET_3_4 HW_REGISTER_RW( 0x7e90247c )
878 #define HDMI_RAM_PACKET_3_4_MASK 0xffffffff
879 #define HDMI_RAM_PACKET_3_4_WIDTH 32
880 #define HDMI_RAM_PACKET_3_4_RESET 0000000000
881 #define HDMI_RAM_PACKET_3_5 HW_REGISTER_RW( 0x7e902480 )
882 #define HDMI_RAM_PACKET_3_5_MASK 0xffffffff
883 #define HDMI_RAM_PACKET_3_5_WIDTH 32
884 #define HDMI_RAM_PACKET_3_5_RESET 0000000000
885 #define HDMI_RAM_PACKET_3_6 HW_REGISTER_RW( 0x7e902484 )
886 #define HDMI_RAM_PACKET_3_6_MASK 0xffffffff
887 #define HDMI_RAM_PACKET_3_6_WIDTH 32
888 #define HDMI_RAM_PACKET_3_6_RESET 0000000000
889 #define HDMI_RAM_PACKET_3_7 HW_REGISTER_RW( 0x7e902488 )
890 #define HDMI_RAM_PACKET_3_7_MASK 0xffffffff
891 #define HDMI_RAM_PACKET_3_7_WIDTH 32
892 #define HDMI_RAM_PACKET_3_7_RESET 0000000000
893 #define HDMI_RAM_PACKET_3_8 HW_REGISTER_RW( 0x7e90248c )
894 #define HDMI_RAM_PACKET_3_8_MASK 0xffffffff
895 #define HDMI_RAM_PACKET_3_8_WIDTH 32
896 #define HDMI_RAM_PACKET_3_8_RESET 0000000000
897 #define HDMI_RAM_PACKET_4_0 HW_REGISTER_RW( 0x7e902490 )
898 #define HDMI_RAM_PACKET_4_0_MASK 0xffffffff
899 #define HDMI_RAM_PACKET_4_0_WIDTH 32
900 #define HDMI_RAM_PACKET_4_0_RESET 0000000000
901 #define HDMI_RAM_PACKET_4_1 HW_REGISTER_RW( 0x7e902494 )
902 #define HDMI_RAM_PACKET_4_1_MASK 0xffffffff
903 #define HDMI_RAM_PACKET_4_1_WIDTH 32
904 #define HDMI_RAM_PACKET_4_1_RESET 0000000000
905 #define HDMI_RAM_PACKET_4_2 HW_REGISTER_RW( 0x7e902498 )
906 #define HDMI_RAM_PACKET_4_2_MASK 0xffffffff
907 #define HDMI_RAM_PACKET_4_2_WIDTH 32
908 #define HDMI_RAM_PACKET_4_2_RESET 0000000000
909 #define HDMI_RAM_PACKET_4_3 HW_REGISTER_RW( 0x7e90249c )
910 #define HDMI_RAM_PACKET_4_3_MASK 0xffffffff
911 #define HDMI_RAM_PACKET_4_3_WIDTH 32
912 #define HDMI_RAM_PACKET_4_3_RESET 0000000000
913 #define HDMI_RAM_PACKET_4_4 HW_REGISTER_RW( 0x7e9024a0 )
914 #define HDMI_RAM_PACKET_4_4_MASK 0xffffffff
915 #define HDMI_RAM_PACKET_4_4_WIDTH 32
916 #define HDMI_RAM_PACKET_4_4_RESET 0000000000
917 #define HDMI_RAM_PACKET_4_5 HW_REGISTER_RW( 0x7e9024a4 )
918 #define HDMI_RAM_PACKET_4_5_MASK 0xffffffff
919 #define HDMI_RAM_PACKET_4_5_WIDTH 32
920 #define HDMI_RAM_PACKET_4_5_RESET 0000000000
921 #define HDMI_RAM_PACKET_4_6 HW_REGISTER_RW( 0x7e9024a8 )
922 #define HDMI_RAM_PACKET_4_6_MASK 0xffffffff
923 #define HDMI_RAM_PACKET_4_6_WIDTH 32
924 #define HDMI_RAM_PACKET_4_6_RESET 0000000000
925 #define HDMI_RAM_PACKET_4_7 HW_REGISTER_RW( 0x7e9024ac )
926 #define HDMI_RAM_PACKET_4_7_MASK 0xffffffff
927 #define HDMI_RAM_PACKET_4_7_WIDTH 32
928 #define HDMI_RAM_PACKET_4_7_RESET 0000000000
929 #define HDMI_RAM_PACKET_4_8 HW_REGISTER_RW( 0x7e9024b0 )
930 #define HDMI_RAM_PACKET_4_8_MASK 0xffffffff
931 #define HDMI_RAM_PACKET_4_8_WIDTH 32
932 #define HDMI_RAM_PACKET_4_8_RESET 0000000000
933 #define HDMI_RAM_PACKET_5_0 HW_REGISTER_RW( 0x7e9024b4 )
934 #define HDMI_RAM_PACKET_5_0_MASK 0xffffffff
935 #define HDMI_RAM_PACKET_5_0_WIDTH 32
936 #define HDMI_RAM_PACKET_5_0_RESET 0000000000
937 #define HDMI_RAM_PACKET_5_1 HW_REGISTER_RW( 0x7e9024b8 )
938 #define HDMI_RAM_PACKET_5_1_MASK 0xffffffff
939 #define HDMI_RAM_PACKET_5_1_WIDTH 32
940 #define HDMI_RAM_PACKET_5_1_RESET 0000000000
941 #define HDMI_RAM_PACKET_5_2 HW_REGISTER_RW( 0x7e9024bc )
942 #define HDMI_RAM_PACKET_5_2_MASK 0xffffffff
943 #define HDMI_RAM_PACKET_5_2_WIDTH 32
944 #define HDMI_RAM_PACKET_5_2_RESET 0000000000
945 #define HDMI_RAM_PACKET_5_3 HW_REGISTER_RW( 0x7e9024c0 )
946 #define HDMI_RAM_PACKET_5_3_MASK 0xffffffff
947 #define HDMI_RAM_PACKET_5_3_WIDTH 32
948 #define HDMI_RAM_PACKET_5_3_RESET 0000000000
949 #define HDMI_RAM_PACKET_5_4 HW_REGISTER_RW( 0x7e9024c4 )
950 #define HDMI_RAM_PACKET_5_4_MASK 0xffffffff
951 #define HDMI_RAM_PACKET_5_4_WIDTH 32
952 #define HDMI_RAM_PACKET_5_4_RESET 0000000000
953 #define HDMI_RAM_PACKET_5_5 HW_REGISTER_RW( 0x7e9024c8 )
954 #define HDMI_RAM_PACKET_5_5_MASK 0xffffffff
955 #define HDMI_RAM_PACKET_5_5_WIDTH 32
956 #define HDMI_RAM_PACKET_5_5_RESET 0000000000
957 #define HDMI_RAM_PACKET_5_6 HW_REGISTER_RW( 0x7e9024cc )
958 #define HDMI_RAM_PACKET_5_6_MASK 0xffffffff
959 #define HDMI_RAM_PACKET_5_6_WIDTH 32
960 #define HDMI_RAM_PACKET_5_6_RESET 0000000000
961 #define HDMI_RAM_PACKET_5_7 HW_REGISTER_RW( 0x7e9024d0 )
962 #define HDMI_RAM_PACKET_5_7_MASK 0xffffffff
963 #define HDMI_RAM_PACKET_5_7_WIDTH 32
964 #define HDMI_RAM_PACKET_5_7_RESET 0000000000
965 #define HDMI_RAM_PACKET_5_8 HW_REGISTER_RW( 0x7e9024d4 )
966 #define HDMI_RAM_PACKET_5_8_MASK 0xffffffff
967 #define HDMI_RAM_PACKET_5_8_WIDTH 32
968 #define HDMI_RAM_PACKET_5_8_RESET 0000000000
969 #define HDMI_RAM_PACKET_6_0 HW_REGISTER_RW( 0x7e9024d8 )
970 #define HDMI_RAM_PACKET_6_0_MASK 0xffffffff
971 #define HDMI_RAM_PACKET_6_0_WIDTH 32
972 #define HDMI_RAM_PACKET_6_0_RESET 0000000000
973 #define HDMI_RAM_PACKET_6_1 HW_REGISTER_RW( 0x7e9024dc )
974 #define HDMI_RAM_PACKET_6_1_MASK 0xffffffff
975 #define HDMI_RAM_PACKET_6_1_WIDTH 32
976 #define HDMI_RAM_PACKET_6_1_RESET 0000000000
977 #define HDMI_RAM_PACKET_6_2 HW_REGISTER_RW( 0x7e9024e0 )
978 #define HDMI_RAM_PACKET_6_2_MASK 0xffffffff
979 #define HDMI_RAM_PACKET_6_2_WIDTH 32
980 #define HDMI_RAM_PACKET_6_2_RESET 0000000000
981 #define HDMI_RAM_PACKET_6_3 HW_REGISTER_RW( 0x7e9024e4 )
982 #define HDMI_RAM_PACKET_6_3_MASK 0xffffffff
983 #define HDMI_RAM_PACKET_6_3_WIDTH 32
984 #define HDMI_RAM_PACKET_6_3_RESET 0000000000
985 #define HDMI_RAM_PACKET_6_4 HW_REGISTER_RW( 0x7e9024e8 )
986 #define HDMI_RAM_PACKET_6_4_MASK 0xffffffff
987 #define HDMI_RAM_PACKET_6_4_WIDTH 32
988 #define HDMI_RAM_PACKET_6_4_RESET 0000000000
989 #define HDMI_RAM_PACKET_6_5 HW_REGISTER_RW( 0x7e9024ec )
990 #define HDMI_RAM_PACKET_6_5_MASK 0xffffffff
991 #define HDMI_RAM_PACKET_6_5_WIDTH 32
992 #define HDMI_RAM_PACKET_6_5_RESET 0000000000
993 #define HDMI_RAM_PACKET_6_6 HW_REGISTER_RW( 0x7e9024f0 )
994 #define HDMI_RAM_PACKET_6_6_MASK 0xffffffff
995 #define HDMI_RAM_PACKET_6_6_WIDTH 32
996 #define HDMI_RAM_PACKET_6_6_RESET 0000000000
997 #define HDMI_RAM_PACKET_6_7 HW_REGISTER_RW( 0x7e9024f4 )
998 #define HDMI_RAM_PACKET_6_7_MASK 0xffffffff
999 #define HDMI_RAM_PACKET_6_7_WIDTH 32
1000 #define HDMI_RAM_PACKET_6_7_RESET 0000000000
1001 #define HDMI_RAM_PACKET_6_8 HW_REGISTER_RW( 0x7e9024f8 )
1002 #define HDMI_RAM_PACKET_6_8_MASK 0xffffffff
1003 #define HDMI_RAM_PACKET_6_8_WIDTH 32
1004 #define HDMI_RAM_PACKET_6_8_RESET 0000000000
1005 #define HDMI_RAM_PACKET_7_0 HW_REGISTER_RW( 0x7e9024fc )
1006 #define HDMI_RAM_PACKET_7_0_MASK 0xffffffff
1007 #define HDMI_RAM_PACKET_7_0_WIDTH 32
1008 #define HDMI_RAM_PACKET_7_0_RESET 0000000000
1009 #define HDMI_RAM_PACKET_7_1 HW_REGISTER_RW( 0x7e902500 )
1010 #define HDMI_RAM_PACKET_7_1_MASK 0xffffffff
1011 #define HDMI_RAM_PACKET_7_1_WIDTH 32
1012 #define HDMI_RAM_PACKET_7_1_RESET 0000000000
1013 #define HDMI_RAM_PACKET_7_2 HW_REGISTER_RW( 0x7e902504 )
1014 #define HDMI_RAM_PACKET_7_2_MASK 0xffffffff
1015 #define HDMI_RAM_PACKET_7_2_WIDTH 32
1016 #define HDMI_RAM_PACKET_7_2_RESET 0000000000
1017 #define HDMI_RAM_PACKET_7_3 HW_REGISTER_RW( 0x7e902508 )
1018 #define HDMI_RAM_PACKET_7_3_MASK 0xffffffff
1019 #define HDMI_RAM_PACKET_7_3_WIDTH 32
1020 #define HDMI_RAM_PACKET_7_3_RESET 0000000000
1021 #define HDMI_RAM_PACKET_7_4 HW_REGISTER_RW( 0x7e90250c )
1022 #define HDMI_RAM_PACKET_7_4_MASK 0xffffffff
1023 #define HDMI_RAM_PACKET_7_4_WIDTH 32
1024 #define HDMI_RAM_PACKET_7_4_RESET 0000000000
1025 #define HDMI_RAM_PACKET_7_5 HW_REGISTER_RW( 0x7e902510 )
1026 #define HDMI_RAM_PACKET_7_5_MASK 0xffffffff
1027 #define HDMI_RAM_PACKET_7_5_WIDTH 32
1028 #define HDMI_RAM_PACKET_7_5_RESET 0000000000
1029 #define HDMI_RAM_PACKET_7_6 HW_REGISTER_RW( 0x7e902514 )
1030 #define HDMI_RAM_PACKET_7_6_MASK 0xffffffff
1031 #define HDMI_RAM_PACKET_7_6_WIDTH 32
1032 #define HDMI_RAM_PACKET_7_6_RESET 0000000000
1033 #define HDMI_RAM_PACKET_7_7 HW_REGISTER_RW( 0x7e902518 )
1034 #define HDMI_RAM_PACKET_7_7_MASK 0xffffffff
1035 #define HDMI_RAM_PACKET_7_7_WIDTH 32
1036 #define HDMI_RAM_PACKET_7_7_RESET 0000000000
1037 #define HDMI_RAM_PACKET_7_8 HW_REGISTER_RW( 0x7e90251c )
1038 #define HDMI_RAM_PACKET_7_8_MASK 0xffffffff
1039 #define HDMI_RAM_PACKET_7_8_WIDTH 32
1040 #define HDMI_RAM_PACKET_7_8_RESET 0000000000
1041 #define HDMI_RAM_PACKET_8_0 HW_REGISTER_RW( 0x7e902520 )
1042 #define HDMI_RAM_PACKET_8_0_MASK 0xffffffff
1043 #define HDMI_RAM_PACKET_8_0_WIDTH 32
1044 #define HDMI_RAM_PACKET_8_0_RESET 0000000000
1045 #define HDMI_RAM_PACKET_8_1 HW_REGISTER_RW( 0x7e902524 )
1046 #define HDMI_RAM_PACKET_8_1_MASK 0xffffffff
1047 #define HDMI_RAM_PACKET_8_1_WIDTH 32
1048 #define HDMI_RAM_PACKET_8_1_RESET 0000000000
1049 #define HDMI_RAM_PACKET_8_2 HW_REGISTER_RW( 0x7e902528 )
1050 #define HDMI_RAM_PACKET_8_2_MASK 0xffffffff
1051 #define HDMI_RAM_PACKET_8_2_WIDTH 32
1052 #define HDMI_RAM_PACKET_8_2_RESET 0000000000
1053 #define HDMI_RAM_PACKET_8_3 HW_REGISTER_RW( 0x7e90252c )
1054 #define HDMI_RAM_PACKET_8_3_MASK 0xffffffff
1055 #define HDMI_RAM_PACKET_8_3_WIDTH 32
1056 #define HDMI_RAM_PACKET_8_3_RESET 0000000000
1057 #define HDMI_RAM_PACKET_8_4 HW_REGISTER_RW( 0x7e902530 )
1058 #define HDMI_RAM_PACKET_8_4_MASK 0xffffffff
1059 #define HDMI_RAM_PACKET_8_4_WIDTH 32
1060 #define HDMI_RAM_PACKET_8_4_RESET 0000000000
1061 #define HDMI_RAM_PACKET_8_5 HW_REGISTER_RW( 0x7e902534 )
1062 #define HDMI_RAM_PACKET_8_5_MASK 0xffffffff
1063 #define HDMI_RAM_PACKET_8_5_WIDTH 32
1064 #define HDMI_RAM_PACKET_8_5_RESET 0000000000
1065 #define HDMI_RAM_PACKET_8_6 HW_REGISTER_RW( 0x7e902538 )
1066 #define HDMI_RAM_PACKET_8_6_MASK 0xffffffff
1067 #define HDMI_RAM_PACKET_8_6_WIDTH 32
1068 #define HDMI_RAM_PACKET_8_6_RESET 0000000000
1069 #define HDMI_RAM_PACKET_8_7 HW_REGISTER_RW( 0x7e90253c )
1070 #define HDMI_RAM_PACKET_8_7_MASK 0xffffffff
1071 #define HDMI_RAM_PACKET_8_7_WIDTH 32
1072 #define HDMI_RAM_PACKET_8_7_RESET 0000000000
1073 #define HDMI_RAM_PACKET_8_8 HW_REGISTER_RW( 0x7e902540 )
1074 #define HDMI_RAM_PACKET_8_8_MASK 0xffffffff
1075 #define HDMI_RAM_PACKET_8_8_WIDTH 32
1076 #define HDMI_RAM_PACKET_8_8_RESET 0000000000
1077 #define HDMI_RAM_PACKET_9_0 HW_REGISTER_RW( 0x7e902544 )
1078 #define HDMI_RAM_PACKET_9_0_MASK 0xffffffff
1079 #define HDMI_RAM_PACKET_9_0_WIDTH 32
1080 #define HDMI_RAM_PACKET_9_0_RESET 0000000000
1081 #define HDMI_RAM_PACKET_9_1 HW_REGISTER_RW( 0x7e902548 )
1082 #define HDMI_RAM_PACKET_9_1_MASK 0xffffffff
1083 #define HDMI_RAM_PACKET_9_1_WIDTH 32
1084 #define HDMI_RAM_PACKET_9_1_RESET 0000000000
1085 #define HDMI_RAM_PACKET_9_2 HW_REGISTER_RW( 0x7e90254c )
1086 #define HDMI_RAM_PACKET_9_2_MASK 0xffffffff
1087 #define HDMI_RAM_PACKET_9_2_WIDTH 32
1088 #define HDMI_RAM_PACKET_9_2_RESET 0000000000
1089 #define HDMI_RAM_PACKET_9_3 HW_REGISTER_RW( 0x7e902550 )
1090 #define HDMI_RAM_PACKET_9_3_MASK 0xffffffff
1091 #define HDMI_RAM_PACKET_9_3_WIDTH 32
1092 #define HDMI_RAM_PACKET_9_3_RESET 0000000000
1093 #define HDMI_RAM_PACKET_9_4 HW_REGISTER_RW( 0x7e902554 )
1094 #define HDMI_RAM_PACKET_9_4_MASK 0xffffffff
1095 #define HDMI_RAM_PACKET_9_4_WIDTH 32
1096 #define HDMI_RAM_PACKET_9_4_RESET 0000000000
1097 #define HDMI_RAM_PACKET_9_5 HW_REGISTER_RW( 0x7e902558 )
1098 #define HDMI_RAM_PACKET_9_5_MASK 0xffffffff
1099 #define HDMI_RAM_PACKET_9_5_WIDTH 32
1100 #define HDMI_RAM_PACKET_9_5_RESET 0000000000
1101 #define HDMI_RAM_PACKET_9_6 HW_REGISTER_RW( 0x7e90255c )
1102 #define HDMI_RAM_PACKET_9_6_MASK 0xffffffff
1103 #define HDMI_RAM_PACKET_9_6_WIDTH 32
1104 #define HDMI_RAM_PACKET_9_6_RESET 0000000000
1105 #define HDMI_RAM_PACKET_9_7 HW_REGISTER_RW( 0x7e902560 )
1106 #define HDMI_RAM_PACKET_9_7_MASK 0xffffffff
1107 #define HDMI_RAM_PACKET_9_7_WIDTH 32
1108 #define HDMI_RAM_PACKET_9_7_RESET 0000000000
1109 #define HDMI_RAM_PACKET_9_8 HW_REGISTER_RW( 0x7e902564 )
1110 #define HDMI_RAM_PACKET_9_8_MASK 0xffffffff
1111 #define HDMI_RAM_PACKET_9_8_WIDTH 32
1112 #define HDMI_RAM_PACKET_9_8_RESET 0000000000
1113 #define HDMI_RAM_PACKET_10_0 HW_REGISTER_RW( 0x7e902568 )
1114 #define HDMI_RAM_PACKET_10_0_MASK 0xffffffff
1115 #define HDMI_RAM_PACKET_10_0_WIDTH 32
1116 #define HDMI_RAM_PACKET_10_0_RESET 0000000000
1117 #define HDMI_RAM_PACKET_10_1 HW_REGISTER_RW( 0x7e90256c )
1118 #define HDMI_RAM_PACKET_10_1_MASK 0xffffffff
1119 #define HDMI_RAM_PACKET_10_1_WIDTH 32
1120 #define HDMI_RAM_PACKET_10_1_RESET 0000000000
1121 #define HDMI_RAM_PACKET_10_2 HW_REGISTER_RW( 0x7e902570 )
1122 #define HDMI_RAM_PACKET_10_2_MASK 0xffffffff
1123 #define HDMI_RAM_PACKET_10_2_WIDTH 32
1124 #define HDMI_RAM_PACKET_10_2_RESET 0000000000
1125 #define HDMI_RAM_PACKET_10_3 HW_REGISTER_RW( 0x7e902574 )
1126 #define HDMI_RAM_PACKET_10_3_MASK 0xffffffff
1127 #define HDMI_RAM_PACKET_10_3_WIDTH 32
1128 #define HDMI_RAM_PACKET_10_3_RESET 0000000000
1129 #define HDMI_RAM_PACKET_10_4 HW_REGISTER_RW( 0x7e902578 )
1130 #define HDMI_RAM_PACKET_10_4_MASK 0xffffffff
1131 #define HDMI_RAM_PACKET_10_4_WIDTH 32
1132 #define HDMI_RAM_PACKET_10_4_RESET 0000000000
1133 #define HDMI_RAM_PACKET_10_5 HW_REGISTER_RW( 0x7e90257c )
1134 #define HDMI_RAM_PACKET_10_5_MASK 0xffffffff
1135 #define HDMI_RAM_PACKET_10_5_WIDTH 32
1136 #define HDMI_RAM_PACKET_10_5_RESET 0000000000
1137 #define HDMI_RAM_PACKET_10_6 HW_REGISTER_RW( 0x7e902580 )
1138 #define HDMI_RAM_PACKET_10_6_MASK 0xffffffff
1139 #define HDMI_RAM_PACKET_10_6_WIDTH 32
1140 #define HDMI_RAM_PACKET_10_6_RESET 0000000000
1141 #define HDMI_RAM_PACKET_10_7 HW_REGISTER_RW( 0x7e902584 )
1142 #define HDMI_RAM_PACKET_10_7_MASK 0xffffffff
1143 #define HDMI_RAM_PACKET_10_7_WIDTH 32
1144 #define HDMI_RAM_PACKET_10_7_RESET 0000000000
1145 #define HDMI_RAM_PACKET_10_8 HW_REGISTER_RW( 0x7e902588 )
1146 #define HDMI_RAM_PACKET_10_8_MASK 0xffffffff
1147 #define HDMI_RAM_PACKET_10_8_WIDTH 32
1148 #define HDMI_RAM_PACKET_10_8_RESET 0000000000
1149 #define HDMI_RAM_PACKET_11_0 HW_REGISTER_RW( 0x7e90258c )
1150 #define HDMI_RAM_PACKET_11_0_MASK 0xffffffff
1151 #define HDMI_RAM_PACKET_11_0_WIDTH 32
1152 #define HDMI_RAM_PACKET_11_0_RESET 0000000000
1153 #define HDMI_RAM_PACKET_11_1 HW_REGISTER_RW( 0x7e902590 )
1154 #define HDMI_RAM_PACKET_11_1_MASK 0xffffffff
1155 #define HDMI_RAM_PACKET_11_1_WIDTH 32
1156 #define HDMI_RAM_PACKET_11_1_RESET 0000000000
1157 #define HDMI_RAM_PACKET_11_2 HW_REGISTER_RW( 0x7e902594 )
1158 #define HDMI_RAM_PACKET_11_2_MASK 0xffffffff
1159 #define HDMI_RAM_PACKET_11_2_WIDTH 32
1160 #define HDMI_RAM_PACKET_11_2_RESET 0000000000
1161 #define HDMI_RAM_PACKET_11_3 HW_REGISTER_RW( 0x7e902598 )
1162 #define HDMI_RAM_PACKET_11_3_MASK 0xffffffff
1163 #define HDMI_RAM_PACKET_11_3_WIDTH 32
1164 #define HDMI_RAM_PACKET_11_3_RESET 0000000000
1165 #define HDMI_RAM_PACKET_11_4 HW_REGISTER_RW( 0x7e90259c )
1166 #define HDMI_RAM_PACKET_11_4_MASK 0xffffffff
1167 #define HDMI_RAM_PACKET_11_4_WIDTH 32
1168 #define HDMI_RAM_PACKET_11_4_RESET 0000000000
1169 #define HDMI_RAM_PACKET_11_5 HW_REGISTER_RW( 0x7e9025a0 )
1170 #define HDMI_RAM_PACKET_11_5_MASK 0xffffffff
1171 #define HDMI_RAM_PACKET_11_5_WIDTH 32
1172 #define HDMI_RAM_PACKET_11_5_RESET 0000000000
1173 #define HDMI_RAM_PACKET_11_6 HW_REGISTER_RW( 0x7e9025a4 )
1174 #define HDMI_RAM_PACKET_11_6_MASK 0xffffffff
1175 #define HDMI_RAM_PACKET_11_6_WIDTH 32
1176 #define HDMI_RAM_PACKET_11_6_RESET 0000000000
1177 #define HDMI_RAM_PACKET_11_7 HW_REGISTER_RW( 0x7e9025a8 )
1178 #define HDMI_RAM_PACKET_11_7_MASK 0xffffffff
1179 #define HDMI_RAM_PACKET_11_7_WIDTH 32
1180 #define HDMI_RAM_PACKET_11_7_RESET 0000000000
1181 #define HDMI_RAM_PACKET_11_8 HW_REGISTER_RW( 0x7e9025ac )
1182 #define HDMI_RAM_PACKET_11_8_MASK 0xffffffff
1183 #define HDMI_RAM_PACKET_11_8_WIDTH 32
1184 #define HDMI_RAM_PACKET_11_8_RESET 0000000000
1185 #define HDMI_RAM_PACKET_12_0 HW_REGISTER_RW( 0x7e9025b0 )
1186 #define HDMI_RAM_PACKET_12_0_MASK 0xffffffff
1187 #define HDMI_RAM_PACKET_12_0_WIDTH 32
1188 #define HDMI_RAM_PACKET_12_0_RESET 0000000000
1189 #define HDMI_RAM_PACKET_12_1 HW_REGISTER_RW( 0x7e9025b4 )
1190 #define HDMI_RAM_PACKET_12_1_MASK 0xffffffff
1191 #define HDMI_RAM_PACKET_12_1_WIDTH 32
1192 #define HDMI_RAM_PACKET_12_1_RESET 0000000000
1193 #define HDMI_RAM_PACKET_12_2 HW_REGISTER_RW( 0x7e9025b8 )
1194 #define HDMI_RAM_PACKET_12_2_MASK 0xffffffff
1195 #define HDMI_RAM_PACKET_12_2_WIDTH 32
1196 #define HDMI_RAM_PACKET_12_2_RESET 0000000000
1197 #define HDMI_RAM_PACKET_12_3 HW_REGISTER_RW( 0x7e9025bc )
1198 #define HDMI_RAM_PACKET_12_3_MASK 0xffffffff
1199 #define HDMI_RAM_PACKET_12_3_WIDTH 32
1200 #define HDMI_RAM_PACKET_12_3_RESET 0000000000
1201 #define HDMI_RAM_PACKET_12_4 HW_REGISTER_RW( 0x7e9025c0 )
1202 #define HDMI_RAM_PACKET_12_4_MASK 0xffffffff
1203 #define HDMI_RAM_PACKET_12_4_WIDTH 32
1204 #define HDMI_RAM_PACKET_12_4_RESET 0000000000
1205 #define HDMI_RAM_PACKET_12_5 HW_REGISTER_RW( 0x7e9025c4 )
1206 #define HDMI_RAM_PACKET_12_5_MASK 0xffffffff
1207 #define HDMI_RAM_PACKET_12_5_WIDTH 32
1208 #define HDMI_RAM_PACKET_12_5_RESET 0000000000
1209 #define HDMI_RAM_PACKET_12_6 HW_REGISTER_RW( 0x7e9025c8 )
1210 #define HDMI_RAM_PACKET_12_6_MASK 0xffffffff
1211 #define HDMI_RAM_PACKET_12_6_WIDTH 32
1212 #define HDMI_RAM_PACKET_12_6_RESET 0000000000
1213 #define HDMI_RAM_PACKET_12_7 HW_REGISTER_RW( 0x7e9025cc )
1214 #define HDMI_RAM_PACKET_12_7_MASK 0xffffffff
1215 #define HDMI_RAM_PACKET_12_7_WIDTH 32
1216 #define HDMI_RAM_PACKET_12_7_RESET 0000000000
1217 #define HDMI_RAM_PACKET_12_8 HW_REGISTER_RW( 0x7e9025d0 )
1218 #define HDMI_RAM_PACKET_12_8_MASK 0xffffffff
1219 #define HDMI_RAM_PACKET_12_8_WIDTH 32
1220 #define HDMI_RAM_PACKET_12_8_RESET 0000000000
1221 #define HDMI_RAM_PACKET_13_0 HW_REGISTER_RW( 0x7e9025d4 )
1222 #define HDMI_RAM_PACKET_13_0_MASK 0xffffffff
1223 #define HDMI_RAM_PACKET_13_0_WIDTH 32
1224 #define HDMI_RAM_PACKET_13_0_RESET 0000000000
1225 #define HDMI_RAM_PACKET_13_1 HW_REGISTER_RW( 0x7e9025d8 )
1226 #define HDMI_RAM_PACKET_13_1_MASK 0xffffffff
1227 #define HDMI_RAM_PACKET_13_1_WIDTH 32
1228 #define HDMI_RAM_PACKET_13_1_RESET 0000000000
1229 #define HDMI_RAM_PACKET_13_2 HW_REGISTER_RW( 0x7e9025dc )
1230 #define HDMI_RAM_PACKET_13_2_MASK 0xffffffff
1231 #define HDMI_RAM_PACKET_13_2_WIDTH 32
1232 #define HDMI_RAM_PACKET_13_2_RESET 0000000000
1233 #define HDMI_RAM_PACKET_13_3 HW_REGISTER_RW( 0x7e9025e0 )
1234 #define HDMI_RAM_PACKET_13_3_MASK 0xffffffff
1235 #define HDMI_RAM_PACKET_13_3_WIDTH 32
1236 #define HDMI_RAM_PACKET_13_3_RESET 0000000000
1237 #define HDMI_RAM_PACKET_13_4 HW_REGISTER_RW( 0x7e9025e4 )
1238 #define HDMI_RAM_PACKET_13_4_MASK 0xffffffff
1239 #define HDMI_RAM_PACKET_13_4_WIDTH 32
1240 #define HDMI_RAM_PACKET_13_4_RESET 0000000000
1241 #define HDMI_RAM_PACKET_13_5 HW_REGISTER_RW( 0x7e9025e8 )
1242 #define HDMI_RAM_PACKET_13_5_MASK 0xffffffff
1243 #define HDMI_RAM_PACKET_13_5_WIDTH 32
1244 #define HDMI_RAM_PACKET_13_5_RESET 0000000000
1245 #define HDMI_RAM_PACKET_13_6 HW_REGISTER_RW( 0x7e9025ec )
1246 #define HDMI_RAM_PACKET_13_6_MASK 0xffffffff
1247 #define HDMI_RAM_PACKET_13_6_WIDTH 32
1248 #define HDMI_RAM_PACKET_13_6_RESET 0000000000
1249 #define HDMI_RAM_PACKET_13_7 HW_REGISTER_RW( 0x7e9025f0 )
1250 #define HDMI_RAM_PACKET_13_7_MASK 0xffffffff
1251 #define HDMI_RAM_PACKET_13_7_WIDTH 32
1252 #define HDMI_RAM_PACKET_13_7_RESET 0000000000
1253 #define HDMI_RAM_PACKET_13_8 HW_REGISTER_RW( 0x7e9025f4 )
1254 #define HDMI_RAM_PACKET_13_8_MASK 0xffffffff
1255 #define HDMI_RAM_PACKET_13_8_WIDTH 32
1256 #define HDMI_RAM_PACKET_13_8_RESET 0000000000
This page took 0.204852 seconds and 3 git commands to generate.