Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / hvs.h
1 // This file was generated by the create_regs script
2 #define SCALER_BASE 0x7e400000
3 #define SCALER_APB_ID 0x64647276
4 #define SCALER_DISPCTRL HW_REGISTER_RW( 0x7e400000 )
5 #define SCALER_DISPCTRL_MASK 0xffffffff
6 #define SCALER_DISPCTRL_WIDTH 32
7 #define SCALER_DISPCTRL_HVS_EN_BITS 31:31
8 #define SCALER_DISPCTRL_HVS_EN_SET 0x80000000
9 #define SCALER_DISPCTRL_HVS_EN_CLR 0x7fffffff
10 #define SCALER_DISPCTRL_HVS_EN_MSB 31
11 #define SCALER_DISPCTRL_HVS_EN_LSB 31
12 #define SCALER_DISPCTRL_VSCL_DIS_BITS 31:30
13 #define SCALER_DISPCTRL_VSCL_DIS_SET 0xc0000000
14 #define SCALER_DISPCTRL_VSCL_DIS_CLR 0x3fffffff
15 #define SCALER_DISPCTRL_VSCL_DIS_MSB 31
16 #define SCALER_DISPCTRL_VSCL_DIS_LSB 30
17 #define SCALER_DISPCTRL_DSP2_PANIC_BITS 29:28
18 #define SCALER_DISPCTRL_DSP2_PANIC_SET 0x30000000
19 #define SCALER_DISPCTRL_DSP2_PANIC_CLR 0xcfffffff
20 #define SCALER_DISPCTRL_DSP2_PANIC_MSB 29
21 #define SCALER_DISPCTRL_DSP2_PANIC_LSB 28
22 #define SCALER_DISPCTRL_DSP1_PANIC_BITS 27:26
23 #define SCALER_DISPCTRL_DSP1_PANIC_SET 0x0c000000
24 #define SCALER_DISPCTRL_DSP1_PANIC_CLR 0xf3ffffff
25 #define SCALER_DISPCTRL_DSP1_PANIC_MSB 27
26 #define SCALER_DISPCTRL_DSP1_PANIC_LSB 26
27 #define SCALER_DISPCTRL_DSP0_PANIC_BITS 25:24
28 #define SCALER_DISPCTRL_DSP0_PANIC_SET 0x03000000
29 #define SCALER_DISPCTRL_DSP0_PANIC_CLR 0xfcffffff
30 #define SCALER_DISPCTRL_DSP0_PANIC_MSB 25
31 #define SCALER_DISPCTRL_DSP0_PANIC_LSB 24
32 #define SCALER_DISPCTRL_DSP3_MUX_BITS 19:18
33 #define SCALER_DISPCTRL_DSP3_MUX_SET 0x000c0000
34 #define SCALER_DISPCTRL_DSP3_MUX_CLR 0xfff3ffff
35 #define SCALER_DISPCTRL_DSP3_MUX_MSB 19
36 #define SCALER_DISPCTRL_DSP3_MUX_LSB 18
37 #define SCALER_DISPCTRL_TILE_WID_BITS 17:16
38 #define SCALER_DISPCTRL_TILE_WID_SET 0x00030000
39 #define SCALER_DISPCTRL_TILE_WID_CLR 0xfffcffff
40 #define SCALER_DISPCTRL_TILE_WID_MSB 17
41 #define SCALER_DISPCTRL_TILE_WID_LSB 16
42 #define SCALER_DISPCTRL_DSP2_IRQ_CTRL_BITS 12:11
43 #define SCALER_DISPCTRL_DSP2_IRQ_CTRL_SET 0x00001800
44 #define SCALER_DISPCTRL_DSP2_IRQ_CTRL_CLR 0xffffe7ff
45 #define SCALER_DISPCTRL_DSP2_IRQ_CTRL_MSB 12
46 #define SCALER_DISPCTRL_DSP2_IRQ_CTRL_LSB 11
47 #define SCALER_DISPCTRL_DSP1_IRQ_CTRL_BITS 10:9
48 #define SCALER_DISPCTRL_DSP1_IRQ_CTRL_SET 0x00000600
49 #define SCALER_DISPCTRL_DSP1_IRQ_CTRL_CLR 0xfffff9ff
50 #define SCALER_DISPCTRL_DSP1_IRQ_CTRL_MSB 10
51 #define SCALER_DISPCTRL_DSP1_IRQ_CTRL_LSB 9
52 #define SCALER_DISPCTRL_IRQ_EN_BITS 6:0
53 #define SCALER_DISPCTRL_IRQ_EN_SET 0x0000007f
54 #define SCALER_DISPCTRL_IRQ_EN_CLR 0xffffff80
55 #define SCALER_DISPCTRL_IRQ_EN_MSB 6
56 #define SCALER_DISPCTRL_IRQ_EN_LSB 0
57 #define SCALER_DISPSTAT HW_REGISTER_RW( 0x7e400004 )
58 #define SCALER_DISPSTAT_MASK 0xffffffff
59 #define SCALER_DISPSTAT_WIDTH 32
60 #define SCALER_DISPSTAT_PROF_IRQ_BITS 31:0
61 #define SCALER_DISPSTAT_PROF_IRQ_SET 0xffffffff
62 #define SCALER_DISPSTAT_PROF_IRQ_CLR 0x00000000
63 #define SCALER_DISPSTAT_PROF_IRQ_MSB 31
64 #define SCALER_DISPSTAT_PROF_IRQ_LSB 0
65 #define SCALER_DISPSTAT_DSP0_IRQ_BITS 31:1
66 #define SCALER_DISPSTAT_DSP0_IRQ_SET 0xfffffffe
67 #define SCALER_DISPSTAT_DSP0_IRQ_CLR 0x00000001
68 #define SCALER_DISPSTAT_DSP0_IRQ_MSB 31
69 #define SCALER_DISPSTAT_DSP0_IRQ_LSB 1
70 #define SCALER_DISPSTAT_DSP1_IRQ_BITS 31:2
71 #define SCALER_DISPSTAT_DSP1_IRQ_SET 0xfffffffc
72 #define SCALER_DISPSTAT_DSP1_IRQ_CLR 0x00000003
73 #define SCALER_DISPSTAT_DSP1_IRQ_MSB 31
74 #define SCALER_DISPSTAT_DSP1_IRQ_LSB 2
75 #define SCALER_DISPSTAT_DSP2_IRQ_BITS 31:3
76 #define SCALER_DISPSTAT_DSP2_IRQ_SET 0xfffffff8
77 #define SCALER_DISPSTAT_DSP2_IRQ_CLR 0x00000007
78 #define SCALER_DISPSTAT_DSP2_IRQ_MSB 31
79 #define SCALER_DISPSTAT_DSP2_IRQ_LSB 3
80 #define SCALER_DISPSTAT_DMA_IRQ_BITS 31:4
81 #define SCALER_DISPSTAT_DMA_IRQ_SET 0xfffffff0
82 #define SCALER_DISPSTAT_DMA_IRQ_CLR 0x0000000f
83 #define SCALER_DISPSTAT_DMA_IRQ_MSB 31
84 #define SCALER_DISPSTAT_DMA_IRQ_LSB 4
85 #define SCALER_DISPSTAT_WR_IRQ_BITS 31:5
86 #define SCALER_DISPSTAT_WR_IRQ_SET 0xffffffe0
87 #define SCALER_DISPSTAT_WR_IRQ_CLR 0x0000001f
88 #define SCALER_DISPSTAT_WR_IRQ_MSB 31
89 #define SCALER_DISPSTAT_WR_IRQ_LSB 5
90 #define SCALER_DISPSTAT_RD_IRQ_BITS 31:6
91 #define SCALER_DISPSTAT_RD_IRQ_SET 0xffffffc0
92 #define SCALER_DISPSTAT_RD_IRQ_CLR 0x0000003f
93 #define SCALER_DISPSTAT_RD_IRQ_MSB 31
94 #define SCALER_DISPSTAT_RD_IRQ_LSB 6
95 #define SCALER_DISPSTAT_DMA_ERR_BIT2_BITS 31:7
96 #define SCALER_DISPSTAT_DMA_ERR_BIT2_SET 0xffffff80
97 #define SCALER_DISPSTAT_DMA_ERR_BIT2_CLR 0x0000007f
98 #define SCALER_DISPSTAT_DMA_ERR_BIT2_MSB 31
99 #define SCALER_DISPSTAT_DMA_ERR_BIT2_LSB 7
100 #define SCALER_DISPSTAT_DSP0_STATUS_BITS 13:8
101 #define SCALER_DISPSTAT_DSP0_STATUS_SET 0x00003f00
102 #define SCALER_DISPSTAT_DSP0_STATUS_CLR 0xffffc0ff
103 #define SCALER_DISPSTAT_DSP0_STATUS_MSB 13
104 #define SCALER_DISPSTAT_DSP0_STATUS_LSB 8
105 #define SCALER_DISPSTAT_DMA_ERR_BIT0_BITS 31:14
106 #define SCALER_DISPSTAT_DMA_ERR_BIT0_SET 0xffffc000
107 #define SCALER_DISPSTAT_DMA_ERR_BIT0_CLR 0x00003fff
108 #define SCALER_DISPSTAT_DMA_ERR_BIT0_MSB 31
109 #define SCALER_DISPSTAT_DMA_ERR_BIT0_LSB 14
110 #define SCALER_DISPSTAT_DMA_ERR_BIT1_BITS 31:15
111 #define SCALER_DISPSTAT_DMA_ERR_BIT1_SET 0xffff8000
112 #define SCALER_DISPSTAT_DMA_ERR_BIT1_CLR 0x00007fff
113 #define SCALER_DISPSTAT_DMA_ERR_BIT1_MSB 31
114 #define SCALER_DISPSTAT_DMA_ERR_BIT1_LSB 15
115 #define SCALER_DISPSTAT_DSP1_STATUS_BITS 21:16
116 #define SCALER_DISPSTAT_DSP1_STATUS_SET 0x003f0000
117 #define SCALER_DISPSTAT_DSP1_STATUS_CLR 0xffc0ffff
118 #define SCALER_DISPSTAT_DSP1_STATUS_MSB 21
119 #define SCALER_DISPSTAT_DSP1_STATUS_LSB 16
120 #define SCALER_DISPSTAT_DSP2_STATUS_BITS 29:24
121 #define SCALER_DISPSTAT_DSP2_STATUS_SET 0x3f000000
122 #define SCALER_DISPSTAT_DSP2_STATUS_CLR 0xc0ffffff
123 #define SCALER_DISPSTAT_DSP2_STATUS_MSB 29
124 #define SCALER_DISPSTAT_DSP2_STATUS_LSB 24
125 #define SCALER_DISPID HW_REGISTER_RW( 0x7e400008 )
126 #define SCALER_DISPID_MASK 0xffffffff
127 #define SCALER_DISPID_WIDTH 32
128 #define SCALER_DISPID_RESET 0x64647276
129 #define SCALER_DISPECTRL HW_REGISTER_RW( 0x7e40000c )
130 #define SCALER_DISPECTRL_MASK 0xffffffff
131 #define SCALER_DISPECTRL_WIDTH 32
132 #define SCALER_DISPECTRL_PANIC_CTRL_BITS 6:0
133 #define SCALER_DISPECTRL_PANIC_CTRL_SET 0x0000007f
134 #define SCALER_DISPECTRL_PANIC_CTRL_CLR 0xffffff80
135 #define SCALER_DISPECTRL_PANIC_CTRL_MSB 6
136 #define SCALER_DISPECTRL_PANIC_CTRL_LSB 0
137 #define SCALER_DISPECTRL_BUSY_STATUS_BITS 31:8
138 #define SCALER_DISPECTRL_BUSY_STATUS_SET 0xffffff00
139 #define SCALER_DISPECTRL_BUSY_STATUS_CLR 0x000000ff
140 #define SCALER_DISPECTRL_BUSY_STATUS_MSB 31
141 #define SCALER_DISPECTRL_BUSY_STATUS_LSB 8
142 #define SCALER_DISPECTRL_Y_BUSY_BITS 31:9
143 #define SCALER_DISPECTRL_Y_BUSY_SET 0xfffffe00
144 #define SCALER_DISPECTRL_Y_BUSY_CLR 0x000001ff
145 #define SCALER_DISPECTRL_Y_BUSY_MSB 31
146 #define SCALER_DISPECTRL_Y_BUSY_LSB 9
147 #define SCALER_DISPECTRL_CB_BUSY_BITS 31:10
148 #define SCALER_DISPECTRL_CB_BUSY_SET 0xfffffc00
149 #define SCALER_DISPECTRL_CB_BUSY_CLR 0x000003ff
150 #define SCALER_DISPECTRL_CB_BUSY_MSB 31
151 #define SCALER_DISPECTRL_CB_BUSY_LSB 10
152 #define SCALER_DISPECTRL_CR_BUSY_BITS 31:11
153 #define SCALER_DISPECTRL_CR_BUSY_SET 0xfffff800
154 #define SCALER_DISPECTRL_CR_BUSY_CLR 0x000007ff
155 #define SCALER_DISPECTRL_CR_BUSY_MSB 31
156 #define SCALER_DISPECTRL_CR_BUSY_LSB 11
157 #define SCALER_DISPECTRL_POSTED_STATUS_BITS 14:12
158 #define SCALER_DISPECTRL_POSTED_STATUS_SET 0x00007000
159 #define SCALER_DISPECTRL_POSTED_STATUS_CLR 0xffff8fff
160 #define SCALER_DISPECTRL_POSTED_STATUS_MSB 14
161 #define SCALER_DISPECTRL_POSTED_STATUS_LSB 12
162 #define SCALER_DISPECTRL_POSTED_CTRL_BITS 21:16
163 #define SCALER_DISPECTRL_POSTED_CTRL_SET 0x003f0000
164 #define SCALER_DISPECTRL_POSTED_CTRL_CLR 0xffc0ffff
165 #define SCALER_DISPECTRL_POSTED_CTRL_MSB 21
166 #define SCALER_DISPECTRL_POSTED_CTRL_LSB 16
167 #define SCALER_DISPECTRL_GT8_BURST_BITS 31:24
168 #define SCALER_DISPECTRL_GT8_BURST_SET 0xff000000
169 #define SCALER_DISPECTRL_GT8_BURST_CLR 0x00ffffff
170 #define SCALER_DISPECTRL_GT8_BURST_MSB 31
171 #define SCALER_DISPECTRL_GT8_BURST_LSB 24
172 #define SCALER_DISPECTRL_TWOD_SINGLE_BITS 31:25
173 #define SCALER_DISPECTRL_TWOD_SINGLE_SET 0xfe000000
174 #define SCALER_DISPECTRL_TWOD_SINGLE_CLR 0x01ffffff
175 #define SCALER_DISPECTRL_TWOD_SINGLE_MSB 31
176 #define SCALER_DISPECTRL_TWOD_SINGLE_LSB 25
177 #define SCALER_DISPECTRL_PROF_TYPE_BITS 27:26
178 #define SCALER_DISPECTRL_PROF_TYPE_SET 0x0c000000
179 #define SCALER_DISPECTRL_PROF_TYPE_CLR 0xf3ffffff
180 #define SCALER_DISPECTRL_PROF_TYPE_MSB 27
181 #define SCALER_DISPECTRL_PROF_TYPE_LSB 26
182 #define SCALER_DISPECTRL_Y_NE_CTRL_BITS 31:28
183 #define SCALER_DISPECTRL_Y_NE_CTRL_SET 0xf0000000
184 #define SCALER_DISPECTRL_Y_NE_CTRL_CLR 0x0fffffff
185 #define SCALER_DISPECTRL_Y_NE_CTRL_MSB 31
186 #define SCALER_DISPECTRL_Y_NE_CTRL_LSB 28
187 #define SCALER_DISPECTRL_CB_NE_CTRL_BITS 31:29
188 #define SCALER_DISPECTRL_CB_NE_CTRL_SET 0xe0000000
189 #define SCALER_DISPECTRL_CB_NE_CTRL_CLR 0x1fffffff
190 #define SCALER_DISPECTRL_CB_NE_CTRL_MSB 31
191 #define SCALER_DISPECTRL_CB_NE_CTRL_LSB 29
192 #define SCALER_DISPECTRL_CR_NE_CTRL_BITS 31:30
193 #define SCALER_DISPECTRL_CR_NE_CTRL_SET 0xc0000000
194 #define SCALER_DISPECTRL_CR_NE_CTRL_CLR 0x3fffffff
195 #define SCALER_DISPECTRL_CR_NE_CTRL_MSB 31
196 #define SCALER_DISPECTRL_CR_NE_CTRL_LSB 30
197 #define SCALER_DISPECTRL_SECURE_MODE_BITS 31:31
198 #define SCALER_DISPECTRL_SECURE_MODE_SET 0x80000000
199 #define SCALER_DISPECTRL_SECURE_MODE_CLR 0x7fffffff
200 #define SCALER_DISPECTRL_SECURE_MODE_MSB 31
201 #define SCALER_DISPECTRL_SECURE_MODE_LSB 31
202 #define SCALER_DISPPROF HW_REGISTER_RW( 0x7e400010 )
203 #define SCALER_DISPPROF_MASK 0xffffffff
204 #define SCALER_DISPPROF_WIDTH 32
205 #define SCALER_DISPDITHER HW_REGISTER_RW( 0x7e400014 )
206 #define SCALER_DISPDITHER_MASK 0xffffffff
207 #define SCALER_DISPDITHER_WIDTH 32
208 #define SCALER_DISPEOLN HW_REGISTER_RW( 0x7e400018 )
209 #define SCALER_DISPEOLN_MASK 0xffffffff
210 #define SCALER_DISPEOLN_WIDTH 32
211 #define SCALER_DISPLIST0 HW_REGISTER_RW( 0x7e400020 )
212 #define SCALER_DISPLIST0_MASK 0xffffffff
213 #define SCALER_DISPLIST0_WIDTH 32
214 #define SCALER_DISPLIST1 HW_REGISTER_RW( 0x7e400024 )
215 #define SCALER_DISPLIST1_MASK 0xffffffff
216 #define SCALER_DISPLIST1_WIDTH 32
217 #define SCALER_DISPLIST2 HW_REGISTER_RW( 0x7e400028 )
218 #define SCALER_DISPLIST2_MASK 0xffffffff
219 #define SCALER_DISPLIST2_WIDTH 32
220 #define SCALER_DISPLSTAT HW_REGISTER_RW( 0x7e40002c )
221 #define SCALER_DISPLSTAT_MASK 0xffffffff
222 #define SCALER_DISPLSTAT_WIDTH 32
223 #define SCALER_DISPLACT0 HW_REGISTER_RW( 0x7e400030 )
224 #define SCALER_DISPLACT0_MASK 0xffffffff
225 #define SCALER_DISPLACT0_WIDTH 32
226 #define SCALER_DISPLACT1 HW_REGISTER_RW( 0x7e400034 )
227 #define SCALER_DISPLACT1_MASK 0xffffffff
228 #define SCALER_DISPLACT1_WIDTH 32
229 #define SCALER_DISPLACT2 HW_REGISTER_RW( 0x7e400038 )
230 #define SCALER_DISPLACT2_MASK 0xffffffff
231 #define SCALER_DISPLACT2_WIDTH 32
232 #define SCALER_DISPCTRL0 HW_REGISTER_RW( 0x7e400040 )
233 #define SCALER_DISPCTRL0_MASK 0xffffffff
234 #define SCALER_DISPCTRL0_WIDTH 32
235 #define SCALER_DISPBKGND0 HW_REGISTER_RW( 0x7e400044 )
236 #define SCALER_DISPBKGND0_MASK 0xffffffff
237 #define SCALER_DISPBKGND0_WIDTH 32
238 #define SCALER_DISPSTAT0 HW_REGISTER_RW( 0x7e400048 )
239 #define SCALER_DISPSTAT0_MASK 0xffffffff
240 #define SCALER_DISPSTAT0_WIDTH 32
241 #define SCALER_DISPBASE0 HW_REGISTER_RW( 0x7e40004c )
242 #define SCALER_DISPBASE0_MASK 0xffffffff
243 #define SCALER_DISPBASE0_WIDTH 32
244 #define SCALER_DISPCTRL1 HW_REGISTER_RW( 0x7e400050 )
245 #define SCALER_DISPCTRL1_MASK 0xffffffff
246 #define SCALER_DISPCTRL1_WIDTH 32
247 #define SCALER_DISPBKGND1 HW_REGISTER_RW( 0x7e400054 )
248 #define SCALER_DISPBKGND1_MASK 0xffffffff
249 #define SCALER_DISPBKGND1_WIDTH 32
250 #define SCALER_DISPSTAT1 HW_REGISTER_RW( 0x7e400058 )
251 #define SCALER_DISPSTAT1_MASK 0xffffffff
252 #define SCALER_DISPSTAT1_WIDTH 32
253 #define SCALER_DISPBASE1 HW_REGISTER_RW( 0x7e40005c )
254 #define SCALER_DISPBASE1_MASK 0xffffffff
255 #define SCALER_DISPBASE1_WIDTH 32
256 #define SCALER_DISPCTRL2 HW_REGISTER_RW( 0x7e400060 )
257 #define SCALER_DISPCTRL2_MASK 0xffffffff
258 #define SCALER_DISPCTRL2_WIDTH 32
259 #define SCALER_DISPBKGND2 HW_REGISTER_RW( 0x7e400064 )
260 #define SCALER_DISPBKGND2_MASK 0xffffffff
261 #define SCALER_DISPBKGND2_WIDTH 32
262 #define SCALER_DISPSTAT2 HW_REGISTER_RW( 0x7e400068 )
263 #define SCALER_DISPSTAT2_MASK 0xffffffff
264 #define SCALER_DISPSTAT2_WIDTH 32
265 #define SCALER_DISPBASE2 HW_REGISTER_RW( 0x7e40006c )
266 #define SCALER_DISPBASE2_MASK 0xffffffff
267 #define SCALER_DISPBASE2_WIDTH 32
268 #define SCALER_DISPALPHA2 HW_REGISTER_RW( 0x7e400070 )
269 #define SCALER_DISPALPHA2_MASK 0xffffffff
270 #define SCALER_DISPALPHA2_WIDTH 32
271 #define SCALER_DISPGAMADR HW_REGISTER_RW( 0x7e400078 )
272 #define SCALER_DISPGAMADR_MASK 0xffffffff
273 #define SCALER_DISPGAMADR_WIDTH 32
274 #define SCALER_OLEDOFFS HW_REGISTER_RW( 0x7e400080 )
275 #define SCALER_OLEDOFFS_MASK 0xffffffff
276 #define SCALER_OLEDOFFS_WIDTH 32
277 #define SCALER_OLEDCOEF0 HW_REGISTER_RW( 0x7e400084 )
278 #define SCALER_OLEDCOEF0_MASK 0xffffffff
279 #define SCALER_OLEDCOEF0_WIDTH 32
280 #define SCALER_OLEDCOEF1 HW_REGISTER_RW( 0x7e400088 )
281 #define SCALER_OLEDCOEF1_MASK 0xffffffff
282 #define SCALER_OLEDCOEF1_WIDTH 32
283 #define SCALER_OLEDCOEF2 HW_REGISTER_RW( 0x7e40008c )
284 #define SCALER_OLEDCOEF2_MASK 0xffffffff
285 #define SCALER_OLEDCOEF2_WIDTH 32
286 #define SCALER_DISPSLAVE0 HW_REGISTER_RW( 0x7e4000c0 )
287 #define SCALER_DISPSLAVE0_MASK 0xffffffff
288 #define SCALER_DISPSLAVE0_WIDTH 32
289 #define SCALER_DISPSLAVE1 HW_REGISTER_RW( 0x7e4000c8 )
290 #define SCALER_DISPSLAVE1_MASK 0xffffffff
291 #define SCALER_DISPSLAVE1_WIDTH 32
292 #define SCALER_DISPSLAVE2 HW_REGISTER_RW( 0x7e4000d0 )
293 #define SCALER_DISPSLAVE2_MASK 0xffffffff
294 #define SCALER_DISPSLAVE2_WIDTH 32
295 #define SCALER_DISPGAMDAT HW_REGISTER_RW( 0x7e4000e0 )
296 #define SCALER_DISPGAMDAT_MASK 0xffffffff
297 #define SCALER_DISPGAMDAT_WIDTH 32
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