0cce5efd036ad7fb39fff9f26fd1b67a5cae15c5
[rpi-open-firmware.git] / bcm2708_chip / i2c_spi_slv.h
1 // This file was generated by the create_regs script
2 #define I2C_SPI_SLV_BASE 0x7e214000
3 #define I2C_SPI_SLV_APB_ID 0x73506783
4 #define I2C_SPI_SLV_DR HW_REGISTER_RW( 0x7e214000 )
5 #define I2C_SPI_SLV_DR_MASK 0xffff3fff
6 #define I2C_SPI_SLV_DR_WIDTH 32
7 #define I2C_SPI_SLV_DR_RESET 0x00120000
8 #define I2C_SPI_SLV_DR_DATA_BITS 7:0
9 #define I2C_SPI_SLV_DR_DATA_SET 0x000000ff
10 #define I2C_SPI_SLV_DR_DATA_CLR 0xffffff00
11 #define I2C_SPI_SLV_DR_DATA_MSB 7
12 #define I2C_SPI_SLV_DR_DATA_LSB 0
13 #define I2C_SPI_SLV_DR_OE_BITS 8:8
14 #define I2C_SPI_SLV_DR_OE_SET 0x00000100
15 #define I2C_SPI_SLV_DR_OE_CLR 0xfffffeff
16 #define I2C_SPI_SLV_DR_OE_MSB 8
17 #define I2C_SPI_SLV_DR_OE_LSB 8
18 #define I2C_SPI_SLV_DR_UE_BITS 9:9
19 #define I2C_SPI_SLV_DR_UE_SET 0x00000200
20 #define I2C_SPI_SLV_DR_UE_CLR 0xfffffdff
21 #define I2C_SPI_SLV_DR_UE_MSB 9
22 #define I2C_SPI_SLV_DR_UE_LSB 9
23 #define I2C_SPI_SLV_DR_TXDMAPREQ_BITS 10:10
24 #define I2C_SPI_SLV_DR_TXDMAPREQ_SET 0x00000400
25 #define I2C_SPI_SLV_DR_TXDMAPREQ_CLR 0xfffffbff
26 #define I2C_SPI_SLV_DR_TXDMAPREQ_MSB 10
27 #define I2C_SPI_SLV_DR_TXDMAPREQ_LSB 10
28 #define I2C_SPI_SLV_DR_TXDMABREQ_BITS 11:11
29 #define I2C_SPI_SLV_DR_TXDMABREQ_SET 0x00000800
30 #define I2C_SPI_SLV_DR_TXDMABREQ_CLR 0xfffff7ff
31 #define I2C_SPI_SLV_DR_TXDMABREQ_MSB 11
32 #define I2C_SPI_SLV_DR_TXDMABREQ_LSB 11
33 #define I2C_SPI_SLV_DR_RXDMAPREQ_BITS 12:12
34 #define I2C_SPI_SLV_DR_RXDMAPREQ_SET 0x00001000
35 #define I2C_SPI_SLV_DR_RXDMAPREQ_CLR 0xffffefff
36 #define I2C_SPI_SLV_DR_RXDMAPREQ_MSB 12
37 #define I2C_SPI_SLV_DR_RXDMAPREQ_LSB 12
38 #define I2C_SPI_SLV_DR_RXDMABREQ_BITS 13:13
39 #define I2C_SPI_SLV_DR_RXDMABREQ_SET 0x00002000
40 #define I2C_SPI_SLV_DR_RXDMABREQ_CLR 0xffffdfff
41 #define I2C_SPI_SLV_DR_RXDMABREQ_MSB 13
42 #define I2C_SPI_SLV_DR_RXDMABREQ_LSB 13
43 #define I2C_SPI_SLV_DR_TXBUSY_BITS 16:16
44 #define I2C_SPI_SLV_DR_TXBUSY_SET 0x00010000
45 #define I2C_SPI_SLV_DR_TXBUSY_CLR 0xfffeffff
46 #define I2C_SPI_SLV_DR_TXBUSY_MSB 16
47 #define I2C_SPI_SLV_DR_TXBUSY_LSB 16
48 #define I2C_SPI_SLV_DR_RXFE_BITS 17:17
49 #define I2C_SPI_SLV_DR_RXFE_SET 0x00020000
50 #define I2C_SPI_SLV_DR_RXFE_CLR 0xfffdffff
51 #define I2C_SPI_SLV_DR_RXFE_MSB 17
52 #define I2C_SPI_SLV_DR_RXFE_LSB 17
53 #define I2C_SPI_SLV_DR_TXFF_BITS 18:18
54 #define I2C_SPI_SLV_DR_TXFF_SET 0x00040000
55 #define I2C_SPI_SLV_DR_TXFF_CLR 0xfffbffff
56 #define I2C_SPI_SLV_DR_TXFF_MSB 18
57 #define I2C_SPI_SLV_DR_TXFF_LSB 18
58 #define I2C_SPI_SLV_DR_RXFF_BITS 19:19
59 #define I2C_SPI_SLV_DR_RXFF_SET 0x00080000
60 #define I2C_SPI_SLV_DR_RXFF_CLR 0xfff7ffff
61 #define I2C_SPI_SLV_DR_RXFF_MSB 19
62 #define I2C_SPI_SLV_DR_RXFF_LSB 19
63 #define I2C_SPI_SLV_DR_TXFE_BITS 20:20
64 #define I2C_SPI_SLV_DR_TXFE_SET 0x00100000
65 #define I2C_SPI_SLV_DR_TXFE_CLR 0xffefffff
66 #define I2C_SPI_SLV_DR_TXFE_MSB 20
67 #define I2C_SPI_SLV_DR_TXFE_LSB 20
68 #define I2C_SPI_SLV_DR_RXBUSY_BITS 21:21
69 #define I2C_SPI_SLV_DR_RXBUSY_SET 0x00200000
70 #define I2C_SPI_SLV_DR_RXBUSY_CLR 0xffdfffff
71 #define I2C_SPI_SLV_DR_RXBUSY_MSB 21
72 #define I2C_SPI_SLV_DR_RXBUSY_LSB 21
73 #define I2C_SPI_SLV_DR_TXFLEVEL_BITS 26:22
74 #define I2C_SPI_SLV_DR_TXFLEVEL_SET 0x07c00000
75 #define I2C_SPI_SLV_DR_TXFLEVEL_CLR 0xf83fffff
76 #define I2C_SPI_SLV_DR_TXFLEVEL_MSB 26
77 #define I2C_SPI_SLV_DR_TXFLEVEL_LSB 22
78 #define I2C_SPI_SLV_DR_RXFLEVEL_BITS 31:27
79 #define I2C_SPI_SLV_DR_RXFLEVEL_SET 0xf8000000
80 #define I2C_SPI_SLV_DR_RXFLEVEL_CLR 0x07ffffff
81 #define I2C_SPI_SLV_DR_RXFLEVEL_MSB 31
82 #define I2C_SPI_SLV_DR_RXFLEVEL_LSB 27
83 #define I2C_SPI_SLV_RSR HW_REGISTER_RW( 0x7e214004 )
84 #define I2C_SPI_SLV_RSR_MASK 0x0000003f
85 #define I2C_SPI_SLV_RSR_WIDTH 6
86 #define I2C_SPI_SLV_RSR_RESET 0000000000
87 #define I2C_SPI_SLV_RSR_OE_BITS 0:0
88 #define I2C_SPI_SLV_RSR_OE_SET 0x00000001
89 #define I2C_SPI_SLV_RSR_OE_CLR 0xfffffffe
90 #define I2C_SPI_SLV_RSR_OE_MSB 0
91 #define I2C_SPI_SLV_RSR_OE_LSB 0
92 #define I2C_SPI_SLV_RSR_UE_BITS 1:1
93 #define I2C_SPI_SLV_RSR_UE_SET 0x00000002
94 #define I2C_SPI_SLV_RSR_UE_CLR 0xfffffffd
95 #define I2C_SPI_SLV_RSR_UE_MSB 1
96 #define I2C_SPI_SLV_RSR_UE_LSB 1
97 #define I2C_SPI_SLV_RSR_TXDMAPREQ_BITS 2:2
98 #define I2C_SPI_SLV_RSR_TXDMAPREQ_SET 0x00000004
99 #define I2C_SPI_SLV_RSR_TXDMAPREQ_CLR 0xfffffffb
100 #define I2C_SPI_SLV_RSR_TXDMAPREQ_MSB 2
101 #define I2C_SPI_SLV_RSR_TXDMAPREQ_LSB 2
102 #define I2C_SPI_SLV_RSR_TXDMABREQ_BITS 3:3
103 #define I2C_SPI_SLV_RSR_TXDMABREQ_SET 0x00000008
104 #define I2C_SPI_SLV_RSR_TXDMABREQ_CLR 0xfffffff7
105 #define I2C_SPI_SLV_RSR_TXDMABREQ_MSB 3
106 #define I2C_SPI_SLV_RSR_TXDMABREQ_LSB 3
107 #define I2C_SPI_SLV_RSR_RXDMAPREQ_BITS 4:4
108 #define I2C_SPI_SLV_RSR_RXDMAPREQ_SET 0x00000010
109 #define I2C_SPI_SLV_RSR_RXDMAPREQ_CLR 0xffffffef
110 #define I2C_SPI_SLV_RSR_RXDMAPREQ_MSB 4
111 #define I2C_SPI_SLV_RSR_RXDMAPREQ_LSB 4
112 #define I2C_SPI_SLV_RSR_RXDMABREQ_BITS 5:5
113 #define I2C_SPI_SLV_RSR_RXDMABREQ_SET 0x00000020
114 #define I2C_SPI_SLV_RSR_RXDMABREQ_CLR 0xffffffdf
115 #define I2C_SPI_SLV_RSR_RXDMABREQ_MSB 5
116 #define I2C_SPI_SLV_RSR_RXDMABREQ_LSB 5
117 #define I2C_SPI_SLV_SLV HW_REGISTER_RW( 0x7e214008 )
118 #define I2C_SPI_SLV_SLV_MASK 0x0000007f
119 #define I2C_SPI_SLV_SLV_WIDTH 7
120 #define I2C_SPI_SLV_SLV_RESET 0000000000
121 #define I2C_SPI_SLV_SLV_ADDR_BITS 6:0
122 #define I2C_SPI_SLV_SLV_ADDR_SET 0x0000007f
123 #define I2C_SPI_SLV_SLV_ADDR_CLR 0xffffff80
124 #define I2C_SPI_SLV_SLV_ADDR_MSB 6
125 #define I2C_SPI_SLV_SLV_ADDR_LSB 0
126 #define I2C_SPI_SLV_CR HW_REGISTER_RW( 0x7e21400c )
127 #define I2C_SPI_SLV_CR_MASK 0x0001ffff
128 #define I2C_SPI_SLV_CR_WIDTH 17
129 #define I2C_SPI_SLV_CR_RESET 0000000000
130 #define I2C_SPI_SLV_CR_EN_BITS 0:0
131 #define I2C_SPI_SLV_CR_EN_SET 0x00000001
132 #define I2C_SPI_SLV_CR_EN_CLR 0xfffffffe
133 #define I2C_SPI_SLV_CR_EN_MSB 0
134 #define I2C_SPI_SLV_CR_EN_LSB 0
135 #define I2C_SPI_SLV_CR_SPI_BITS 1:1
136 #define I2C_SPI_SLV_CR_SPI_SET 0x00000002
137 #define I2C_SPI_SLV_CR_SPI_CLR 0xfffffffd
138 #define I2C_SPI_SLV_CR_SPI_MSB 1
139 #define I2C_SPI_SLV_CR_SPI_LSB 1
140 #define I2C_SPI_SLV_CR_I2C_BITS 2:2
141 #define I2C_SPI_SLV_CR_I2C_SET 0x00000004
142 #define I2C_SPI_SLV_CR_I2C_CLR 0xfffffffb
143 #define I2C_SPI_SLV_CR_I2C_MSB 2
144 #define I2C_SPI_SLV_CR_I2C_LSB 2
145 #define I2C_SPI_SLV_CR_CPHA_BITS 3:3
146 #define I2C_SPI_SLV_CR_CPHA_SET 0x00000008
147 #define I2C_SPI_SLV_CR_CPHA_CLR 0xfffffff7
148 #define I2C_SPI_SLV_CR_CPHA_MSB 3
149 #define I2C_SPI_SLV_CR_CPHA_LSB 3
150 #define I2C_SPI_SLV_CR_CPOL_BITS 4:4
151 #define I2C_SPI_SLV_CR_CPOL_SET 0x00000010
152 #define I2C_SPI_SLV_CR_CPOL_CLR 0xffffffef
153 #define I2C_SPI_SLV_CR_CPOL_MSB 4
154 #define I2C_SPI_SLV_CR_CPOL_LSB 4
155 #define I2C_SPI_SLV_CR_ENSTAT_BITS 5:5
156 #define I2C_SPI_SLV_CR_ENSTAT_SET 0x00000020
157 #define I2C_SPI_SLV_CR_ENSTAT_CLR 0xffffffdf
158 #define I2C_SPI_SLV_CR_ENSTAT_MSB 5
159 #define I2C_SPI_SLV_CR_ENSTAT_LSB 5
160 #define I2C_SPI_SLV_CR_ENCTRL_BITS 6:6
161 #define I2C_SPI_SLV_CR_ENCTRL_SET 0x00000040
162 #define I2C_SPI_SLV_CR_ENCTRL_CLR 0xffffffbf
163 #define I2C_SPI_SLV_CR_ENCTRL_MSB 6
164 #define I2C_SPI_SLV_CR_ENCTRL_LSB 6
165 #define I2C_SPI_SLV_CR_BRK_BITS 7:7
166 #define I2C_SPI_SLV_CR_BRK_SET 0x00000080
167 #define I2C_SPI_SLV_CR_BRK_CLR 0xffffff7f
168 #define I2C_SPI_SLV_CR_BRK_MSB 7
169 #define I2C_SPI_SLV_CR_BRK_LSB 7
170 #define I2C_SPI_SLV_CR_TXE_BITS 8:8
171 #define I2C_SPI_SLV_CR_TXE_SET 0x00000100
172 #define I2C_SPI_SLV_CR_TXE_CLR 0xfffffeff
173 #define I2C_SPI_SLV_CR_TXE_MSB 8
174 #define I2C_SPI_SLV_CR_TXE_LSB 8
175 #define I2C_SPI_SLV_CR_RXE_BITS 9:9
176 #define I2C_SPI_SLV_CR_RXE_SET 0x00000200
177 #define I2C_SPI_SLV_CR_RXE_CLR 0xfffffdff
178 #define I2C_SPI_SLV_CR_RXE_MSB 9
179 #define I2C_SPI_SLV_CR_RXE_LSB 9
180 #define I2C_SPI_SLV_CR_INV_RXF_BITS 10:10
181 #define I2C_SPI_SLV_CR_INV_RXF_SET 0x00000400
182 #define I2C_SPI_SLV_CR_INV_RXF_CLR 0xfffffbff
183 #define I2C_SPI_SLV_CR_INV_RXF_MSB 10
184 #define I2C_SPI_SLV_CR_INV_RXF_LSB 10
185 #define I2C_SPI_SLV_CR_TESTFIFO_BITS 11:11
186 #define I2C_SPI_SLV_CR_TESTFIFO_SET 0x00000800
187 #define I2C_SPI_SLV_CR_TESTFIFO_CLR 0xfffff7ff
188 #define I2C_SPI_SLV_CR_TESTFIFO_MSB 11
189 #define I2C_SPI_SLV_CR_TESTFIFO_LSB 11
190 #define I2C_SPI_SLV_CR_HOSTCTRLEN_BITS 12:12
191 #define I2C_SPI_SLV_CR_HOSTCTRLEN_SET 0x00001000
192 #define I2C_SPI_SLV_CR_HOSTCTRLEN_CLR 0xffffefff
193 #define I2C_SPI_SLV_CR_HOSTCTRLEN_MSB 12
194 #define I2C_SPI_SLV_CR_HOSTCTRLEN_LSB 12
195 #define I2C_SPI_SLV_CR_INV_TXF_BITS 13:13
196 #define I2C_SPI_SLV_CR_INV_TXF_SET 0x00002000
197 #define I2C_SPI_SLV_CR_INV_TXF_CLR 0xffffdfff
198 #define I2C_SPI_SLV_CR_INV_TXF_MSB 13
199 #define I2C_SPI_SLV_CR_INV_TXF_LSB 13
200 #define I2C_SPI_SLV_FR HW_REGISTER_RW( 0x7e214010 )
201 #define I2C_SPI_SLV_FR_MASK 0x0000ffff
202 #define I2C_SPI_SLV_FR_WIDTH 16
203 #define I2C_SPI_SLV_FR_RESET 0x00000012
204 #define I2C_SPI_SLV_FR_TXBUSY_BITS 0:0
205 #define I2C_SPI_SLV_FR_TXBUSY_SET 0x00000001
206 #define I2C_SPI_SLV_FR_TXBUSY_CLR 0xfffffffe
207 #define I2C_SPI_SLV_FR_TXBUSY_MSB 0
208 #define I2C_SPI_SLV_FR_TXBUSY_LSB 0
209 #define I2C_SPI_SLV_FR_RXFE_BITS 1:1
210 #define I2C_SPI_SLV_FR_RXFE_SET 0x00000002
211 #define I2C_SPI_SLV_FR_RXFE_CLR 0xfffffffd
212 #define I2C_SPI_SLV_FR_RXFE_MSB 1
213 #define I2C_SPI_SLV_FR_RXFE_LSB 1
214 #define I2C_SPI_SLV_FR_TXFF_BITS 2:2
215 #define I2C_SPI_SLV_FR_TXFF_SET 0x00000004
216 #define I2C_SPI_SLV_FR_TXFF_CLR 0xfffffffb
217 #define I2C_SPI_SLV_FR_TXFF_MSB 2
218 #define I2C_SPI_SLV_FR_TXFF_LSB 2
219 #define I2C_SPI_SLV_FR_RXFF_BITS 3:3
220 #define I2C_SPI_SLV_FR_RXFF_SET 0x00000008
221 #define I2C_SPI_SLV_FR_RXFF_CLR 0xfffffff7
222 #define I2C_SPI_SLV_FR_RXFF_MSB 3
223 #define I2C_SPI_SLV_FR_RXFF_LSB 3
224 #define I2C_SPI_SLV_FR_TXFE_BITS 4:4
225 #define I2C_SPI_SLV_FR_TXFE_SET 0x00000010
226 #define I2C_SPI_SLV_FR_TXFE_CLR 0xffffffef
227 #define I2C_SPI_SLV_FR_TXFE_MSB 4
228 #define I2C_SPI_SLV_FR_TXFE_LSB 4
229 #define I2C_SPI_SLV_FR_RXBUSY_BITS 5:5
230 #define I2C_SPI_SLV_FR_RXBUSY_SET 0x00000020
231 #define I2C_SPI_SLV_FR_RXBUSY_CLR 0xffffffdf
232 #define I2C_SPI_SLV_FR_RXBUSY_MSB 5
233 #define I2C_SPI_SLV_FR_RXBUSY_LSB 5
234 #define I2C_SPI_SLV_FR_TXFLEVEL_BITS 6:10
235 #define I2C_SPI_SLV_FR_TXFLEVEL_SET 0x00000000000
236 #define I2C_SPI_SLV_FR_TXFLEVEL_CLR 0xffffffff111
237 #define I2C_SPI_SLV_FR_TXFLEVEL_MSB 6
238 #define I2C_SPI_SLV_FR_TXFLEVEL_LSB 10
239 #define I2C_SPI_SLV_FR_RXFLEVEL_BITS 15:11
240 #define I2C_SPI_SLV_FR_RXFLEVEL_SET 0x0000f800
241 #define I2C_SPI_SLV_FR_RXFLEVEL_CLR 0xffff07ff
242 #define I2C_SPI_SLV_FR_RXFLEVEL_MSB 15
243 #define I2C_SPI_SLV_FR_RXFLEVEL_LSB 11
244 #define I2C_SPI_SLV_IFLS HW_REGISTER_RW( 0x7e214014 )
245 #define I2C_SPI_SLV_IFLS_MASK 0x00000fff
246 #define I2C_SPI_SLV_IFLS_WIDTH 12
247 #define I2C_SPI_SLV_IFLS_RESET 0x00000492
248 #define I2C_SPI_SLV_IFLS_TXIFLSEL_BITS 2:0
249 #define I2C_SPI_SLV_IFLS_TXIFLSEL_SET 0x00000007
250 #define I2C_SPI_SLV_IFLS_TXIFLSEL_CLR 0xfffffff8
251 #define I2C_SPI_SLV_IFLS_TXIFLSEL_MSB 2
252 #define I2C_SPI_SLV_IFLS_TXIFLSEL_LSB 0
253 #define I2C_SPI_SLV_IFLS_RXIFLSEL_BITS 5:3
254 #define I2C_SPI_SLV_IFLS_RXIFLSEL_SET 0x00000038
255 #define I2C_SPI_SLV_IFLS_RXIFLSEL_CLR 0xffffffc7
256 #define I2C_SPI_SLV_IFLS_RXIFLSEL_MSB 5
257 #define I2C_SPI_SLV_IFLS_RXIFLSEL_LSB 3
258 #define I2C_SPI_SLV_IFLS_TXIFPSEL_BITS 8:6
259 #define I2C_SPI_SLV_IFLS_TXIFPSEL_SET 0x000001c0
260 #define I2C_SPI_SLV_IFLS_TXIFPSEL_CLR 0xfffffe3f
261 #define I2C_SPI_SLV_IFLS_TXIFPSEL_MSB 8
262 #define I2C_SPI_SLV_IFLS_TXIFPSEL_LSB 6
263 #define I2C_SPI_SLV_IFLS_RXIFPSEL_BITS 11:9
264 #define I2C_SPI_SLV_IFLS_RXIFPSEL_SET 0x00000e00
265 #define I2C_SPI_SLV_IFLS_RXIFPSEL_CLR 0xfffff1ff
266 #define I2C_SPI_SLV_IFLS_RXIFPSEL_MSB 11
267 #define I2C_SPI_SLV_IFLS_RXIFPSEL_LSB 9
268 #define I2C_SPI_SLV_IMSC HW_REGISTER_RW( 0x7e214018 )
269 #define I2C_SPI_SLV_IMSC_MASK 0x0000000f
270 #define I2C_SPI_SLV_IMSC_WIDTH 4
271 #define I2C_SPI_SLV_IMSC_RESET 0000000000
272 #define I2C_SPI_SLV_IMSC_RXIM_BITS 0:0
273 #define I2C_SPI_SLV_IMSC_RXIM_SET 0x00000001
274 #define I2C_SPI_SLV_IMSC_RXIM_CLR 0xfffffffe
275 #define I2C_SPI_SLV_IMSC_RXIM_MSB 0
276 #define I2C_SPI_SLV_IMSC_RXIM_LSB 0
277 #define I2C_SPI_SLV_IMSC_TXIM_BITS 1:1
278 #define I2C_SPI_SLV_IMSC_TXIM_SET 0x00000002
279 #define I2C_SPI_SLV_IMSC_TXIM_CLR 0xfffffffd
280 #define I2C_SPI_SLV_IMSC_TXIM_MSB 1
281 #define I2C_SPI_SLV_IMSC_TXIM_LSB 1
282 #define I2C_SPI_SLV_IMSC_BEIM_BITS 2:2
283 #define I2C_SPI_SLV_IMSC_BEIM_SET 0x00000004
284 #define I2C_SPI_SLV_IMSC_BEIM_CLR 0xfffffffb
285 #define I2C_SPI_SLV_IMSC_BEIM_MSB 2
286 #define I2C_SPI_SLV_IMSC_BEIM_LSB 2
287 #define I2C_SPI_SLV_IMSC_OEIM_BITS 3:3
288 #define I2C_SPI_SLV_IMSC_OEIM_SET 0x00000008
289 #define I2C_SPI_SLV_IMSC_OEIM_CLR 0xfffffff7
290 #define I2C_SPI_SLV_IMSC_OEIM_MSB 3
291 #define I2C_SPI_SLV_IMSC_OEIM_LSB 3
292 #define I2C_SPI_SLV_RIS HW_REGISTER_RW( 0x7e21401c )
293 #define I2C_SPI_SLV_RIS_MASK 0x0000000f
294 #define I2C_SPI_SLV_RIS_WIDTH 4
295 #define I2C_SPI_SLV_RIS_RESET 0x00000002
296 #define I2C_SPI_SLV_RIS_RXRIS_BITS 0:0
297 #define I2C_SPI_SLV_RIS_RXRIS_SET 0x00000001
298 #define I2C_SPI_SLV_RIS_RXRIS_CLR 0xfffffffe
299 #define I2C_SPI_SLV_RIS_RXRIS_MSB 0
300 #define I2C_SPI_SLV_RIS_RXRIS_LSB 0
301 #define I2C_SPI_SLV_RIS_TXRIS_BITS 1:1
302 #define I2C_SPI_SLV_RIS_TXRIS_SET 0x00000002
303 #define I2C_SPI_SLV_RIS_TXRIS_CLR 0xfffffffd
304 #define I2C_SPI_SLV_RIS_TXRIS_MSB 1
305 #define I2C_SPI_SLV_RIS_TXRIS_LSB 1
306 #define I2C_SPI_SLV_RIS_BERIS_BITS 2:2
307 #define I2C_SPI_SLV_RIS_BERIS_SET 0x00000004
308 #define I2C_SPI_SLV_RIS_BERIS_CLR 0xfffffffb
309 #define I2C_SPI_SLV_RIS_BERIS_MSB 2
310 #define I2C_SPI_SLV_RIS_BERIS_LSB 2
311 #define I2C_SPI_SLV_RIS_OERIS_BITS 3:3
312 #define I2C_SPI_SLV_RIS_OERIS_SET 0x00000008
313 #define I2C_SPI_SLV_RIS_OERIS_CLR 0xfffffff7
314 #define I2C_SPI_SLV_RIS_OERIS_MSB 3
315 #define I2C_SPI_SLV_RIS_OERIS_LSB 3
316 #define I2C_SPI_SLV_MIS HW_REGISTER_RW( 0x7e214020 )
317 #define I2C_SPI_SLV_MIS_MASK 0x0000000f
318 #define I2C_SPI_SLV_MIS_WIDTH 4
319 #define I2C_SPI_SLV_MIS_RESET 0000000000
320 #define I2C_SPI_SLV_MIS_RXMIS_BITS 0:0
321 #define I2C_SPI_SLV_MIS_RXMIS_SET 0x00000001
322 #define I2C_SPI_SLV_MIS_RXMIS_CLR 0xfffffffe
323 #define I2C_SPI_SLV_MIS_RXMIS_MSB 0
324 #define I2C_SPI_SLV_MIS_RXMIS_LSB 0
325 #define I2C_SPI_SLV_MIS_TXMIS_BITS 1:1
326 #define I2C_SPI_SLV_MIS_TXMIS_SET 0x00000002
327 #define I2C_SPI_SLV_MIS_TXMIS_CLR 0xfffffffd
328 #define I2C_SPI_SLV_MIS_TXMIS_MSB 1
329 #define I2C_SPI_SLV_MIS_TXMIS_LSB 1
330 #define I2C_SPI_SLV_MIS_BEMIS_BITS 2:2
331 #define I2C_SPI_SLV_MIS_BEMIS_SET 0x00000004
332 #define I2C_SPI_SLV_MIS_BEMIS_CLR 0xfffffffb
333 #define I2C_SPI_SLV_MIS_BEMIS_MSB 2
334 #define I2C_SPI_SLV_MIS_BEMIS_LSB 2
335 #define I2C_SPI_SLV_MIS_OEMIS_BITS 3:3
336 #define I2C_SPI_SLV_MIS_OEMIS_SET 0x00000008
337 #define I2C_SPI_SLV_MIS_OEMIS_CLR 0xfffffff7
338 #define I2C_SPI_SLV_MIS_OEMIS_MSB 3
339 #define I2C_SPI_SLV_MIS_OEMIS_LSB 3
340 #define I2C_SPI_SLV_ICR HW_REGISTER_RW( 0x7e214024 )
341 #define I2C_SPI_SLV_ICR_MASK 0x0000000f
342 #define I2C_SPI_SLV_ICR_WIDTH 4
343 #define I2C_SPI_SLV_ICR_RESET 0000000000
344 #define I2C_SPI_SLV_ICR_RXIC_BITS 0:0
345 #define I2C_SPI_SLV_ICR_RXIC_SET 0x00000001
346 #define I2C_SPI_SLV_ICR_RXIC_CLR 0xfffffffe
347 #define I2C_SPI_SLV_ICR_RXIC_MSB 0
348 #define I2C_SPI_SLV_ICR_RXIC_LSB 0
349 #define I2C_SPI_SLV_ICR_TXIC_BITS 1:1
350 #define I2C_SPI_SLV_ICR_TXIC_SET 0x00000002
351 #define I2C_SPI_SLV_ICR_TXIC_CLR 0xfffffffd
352 #define I2C_SPI_SLV_ICR_TXIC_MSB 1
353 #define I2C_SPI_SLV_ICR_TXIC_LSB 1
354 #define I2C_SPI_SLV_ICR_BEIC_BITS 2:2
355 #define I2C_SPI_SLV_ICR_BEIC_SET 0x00000004
356 #define I2C_SPI_SLV_ICR_BEIC_CLR 0xfffffffb
357 #define I2C_SPI_SLV_ICR_BEIC_MSB 2
358 #define I2C_SPI_SLV_ICR_BEIC_LSB 2
359 #define I2C_SPI_SLV_ICR_OEIC_BITS 3:3
360 #define I2C_SPI_SLV_ICR_OEIC_SET 0x00000008
361 #define I2C_SPI_SLV_ICR_OEIC_CLR 0xfffffff7
362 #define I2C_SPI_SLV_ICR_OEIC_MSB 3
363 #define I2C_SPI_SLV_ICR_OEIC_LSB 3
364 #define I2C_SPI_SLV_DMACR HW_REGISTER_RW( 0x7e214028 )
365 #define I2C_SPI_SLV_DMACR_MASK 0x00000007
366 #define I2C_SPI_SLV_DMACR_WIDTH 3
367 #define I2C_SPI_SLV_DMACR_RESET 0000000000
368 #define I2C_SPI_SLV_DMACR_RXDMAE_BITS 0:0
369 #define I2C_SPI_SLV_DMACR_RXDMAE_SET 0x00000001
370 #define I2C_SPI_SLV_DMACR_RXDMAE_CLR 0xfffffffe
371 #define I2C_SPI_SLV_DMACR_RXDMAE_MSB 0
372 #define I2C_SPI_SLV_DMACR_RXDMAE_LSB 0
373 #define I2C_SPI_SLV_DMACR_TXDMAE_BITS 1:1
374 #define I2C_SPI_SLV_DMACR_TXDMAE_SET 0x00000002
375 #define I2C_SPI_SLV_DMACR_TXDMAE_CLR 0xfffffffd
376 #define I2C_SPI_SLV_DMACR_TXDMAE_MSB 1
377 #define I2C_SPI_SLV_DMACR_TXDMAE_LSB 1
378 #define I2C_SPI_SLV_DMACR_DMAONERR_BITS 2:2
379 #define I2C_SPI_SLV_DMACR_DMAONERR_SET 0x00000004
380 #define I2C_SPI_SLV_DMACR_DMAONERR_CLR 0xfffffffb
381 #define I2C_SPI_SLV_DMACR_DMAONERR_MSB 2
382 #define I2C_SPI_SLV_DMACR_DMAONERR_LSB 2
383 #define I2C_SPI_SLV_TDR HW_REGISTER_RW( 0x7e21402c )
384 #define I2C_SPI_SLV_TDR_MASK 0x000000ff
385 #define I2C_SPI_SLV_TDR_WIDTH 8
386 #define I2C_SPI_SLV_TDR_RESET 0000000000
387 #define I2C_SPI_SLV_TDR_DATA_BITS 7:0
388 #define I2C_SPI_SLV_TDR_DATA_SET 0x000000ff
389 #define I2C_SPI_SLV_TDR_DATA_CLR 0xffffff00
390 #define I2C_SPI_SLV_TDR_DATA_MSB 7
391 #define I2C_SPI_SLV_TDR_DATA_LSB 0
392 #define I2C_SPI_SLV_VCSTAT HW_REGISTER_RW( 0x7e214030 )
393 #define I2C_SPI_SLV_VCSTAT_MASK 0x0000000f
394 #define I2C_SPI_SLV_VCSTAT_WIDTH 4
395 #define I2C_SPI_SLV_VCSTAT_RESET 0000000000
396 #define I2C_SPI_SLV_VCSTAT_DATA_BITS 3:0
397 #define I2C_SPI_SLV_VCSTAT_DATA_SET 0x0000000f
398 #define I2C_SPI_SLV_VCSTAT_DATA_CLR 0xfffffff0
399 #define I2C_SPI_SLV_VCSTAT_DATA_MSB 3
400 #define I2C_SPI_SLV_VCSTAT_DATA_LSB 0
401 #define I2C_SPI_SLV_HCTRL HW_REGISTER_RW( 0x7e214034 )
402 #define I2C_SPI_SLV_HCTRL_MASK 0x000000ff
403 #define I2C_SPI_SLV_HCTRL_WIDTH 8
404 #define I2C_SPI_SLV_HCTRL_RESET 0000000000
405 #define I2C_SPI_SLV_HCTRL_DATA_BITS 7:0
406 #define I2C_SPI_SLV_HCTRL_DATA_SET 0x000000ff
407 #define I2C_SPI_SLV_HCTRL_DATA_CLR 0xffffff00
408 #define I2C_SPI_SLV_HCTRL_DATA_MSB 7
409 #define I2C_SPI_SLV_HCTRL_DATA_LSB 0
410 #define I2C_SPI_SLV_DEBUG1 HW_REGISTER_RW( 0x7e214038 )
411 #define I2C_SPI_SLV_DEBUG1_MASK 0x03ffffff
412 #define I2C_SPI_SLV_DEBUG1_WIDTH 26
413 #define I2C_SPI_SLV_DEBUG1_RESET 0x0000000e
414 #define I2C_SPI_SLV_DEBUG1_DATA_BITS 25:0
415 #define I2C_SPI_SLV_DEBUG1_DATA_SET 0x03ffffff
416 #define I2C_SPI_SLV_DEBUG1_DATA_CLR 0xfc000000
417 #define I2C_SPI_SLV_DEBUG1_DATA_MSB 25
418 #define I2C_SPI_SLV_DEBUG1_DATA_LSB 0
419 #define I2C_SPI_SLV_DEBUG2 HW_REGISTER_RW( 0x7e21403c )
420 #define I2C_SPI_SLV_DEBUG2_MASK 0x00ffffff
421 #define I2C_SPI_SLV_DEBUG2_WIDTH 24
422 #define I2C_SPI_SLV_DEBUG2_RESET 0x00400000
423 #define I2C_SPI_SLV_DEBUG2_DATA_BITS 23:0
424 #define I2C_SPI_SLV_DEBUG2_DATA_SET 0x00ffffff
425 #define I2C_SPI_SLV_DEBUG2_DATA_CLR 0xff000000
426 #define I2C_SPI_SLV_DEBUG2_DATA_MSB 23
427 #define I2C_SPI_SLV_DEBUG2_DATA_LSB 0
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