cd5e3012ee17bd997c4cf2453cc359bb17bb3f06
[rpi-open-firmware.git] / bcm2708_chip / intctrl0.h
1 // This file was generated by the create_regs script
2 #define IC0_BASE 0x7e002000
3 #define IC0_APB_ID 0x494e5445
4 #define IC0_C HW_REGISTER_RW( 0x7e002000 )
5 #define IC0_C_MASK 0x0000000f
6 #define IC0_C_WIDTH 4
7 #define IC0_C_RESET 0000000000
8 #define IC0_S HW_REGISTER_RO( 0x7e002004 )
9 #define IC0_S_MASK 0x073f073f
10 #define IC0_S_WIDTH 27
11 #define IC0_SRC0 HW_REGISTER_RO( 0x7e002008 )
12 #define IC0_SRC0_MASK 0xffffffff
13 #define IC0_SRC0_WIDTH 32
14 #define IC0_SRC1 HW_REGISTER_RO( 0x7e00200c )
15 #define IC0_SRC1_MASK 0xffffffff
16 #define IC0_SRC1_WIDTH 32
17 #define IC0_MASK0 HW_REGISTER_RW( 0x7e002010 )
18 #define IC0_MASK0_MASK 0x77777777
19 #define IC0_MASK0_WIDTH 31
20 #define IC0_MASK0_RESET 0000000000
21 #define IC0_MASK1 HW_REGISTER_RW( 0x7e002014 )
22 #define IC0_MASK1_MASK 0x77777777
23 #define IC0_MASK1_WIDTH 31
24 #define IC0_MASK1_RESET 0000000000
25 #define IC0_MASK2 HW_REGISTER_RW( 0x7e002018 )
26 #define IC0_MASK2_MASK 0x77777777
27 #define IC0_MASK2_WIDTH 31
28 #define IC0_MASK2_RESET 0000000000
29 #define IC0_MASK3 HW_REGISTER_RW( 0x7e00201c )
30 #define IC0_MASK3_MASK 0x77777777
31 #define IC0_MASK3_WIDTH 31
32 #define IC0_MASK3_RESET 0000000000
33 #define IC0_MASK4 HW_REGISTER_RW( 0x7e002020 )
34 #define IC0_MASK4_MASK 0x77777777
35 #define IC0_MASK4_WIDTH 31
36 #define IC0_MASK4_RESET 0000000000
37 #define IC0_MASK5 HW_REGISTER_RW( 0x7e002024 )
38 #define IC0_MASK5_MASK 0x77777777
39 #define IC0_MASK5_WIDTH 31
40 #define IC0_MASK5_RESET 0000000000
41 #define IC0_MASK6 HW_REGISTER_RW( 0x7e002028 )
42 #define IC0_MASK6_MASK 0x77777777
43 #define IC0_MASK6_WIDTH 31
44 #define IC0_MASK6_RESET 0000000000
45 #define IC0_MASK7 HW_REGISTER_RW( 0x7e00202c )
46 #define IC0_MASK7_MASK 0x77777777
47 #define IC0_MASK7_WIDTH 31
48 #define IC0_MASK7_RESET 0000000000
49 #define IC0_VADDR HW_REGISTER_RW( 0x7e002030 )
50 #define IC0_VADDR_MASK 0xfffffe00
51 #define IC0_VADDR_WIDTH 32
52 #define IC0_VADDR_RESET 0000000000
53 #define IC0_WAKEUP HW_REGISTER_RW( 0x7e002034 )
54 #define IC0_WAKEUP_MASK 0xfffffffe
55 #define IC0_WAKEUP_WIDTH 32
56 #define IC0_WAKEUP_RESET 0x10000000
57 #define IC0_PROFILE HW_REGISTER_RW( 0x7e002038 )
58 #define IC0_PROFILE_MASK 0x0000ffff
59 #define IC0_PROFILE_WIDTH 16
60 #define IC0_FORCE0 HW_REGISTER_RW( 0x7e002040 )
61 #define IC0_FORCE0_MASK 0xffffffff
62 #define IC0_FORCE0_WIDTH 32
63 #define IC0_FORCE0_RESET 0000000000
64 #define IC0_FORCE1 HW_REGISTER_RW( 0x7e002044 )
65 #define IC0_FORCE1_MASK 0xffffffff
66 #define IC0_FORCE1_WIDTH 32
67 #define IC0_FORCE1_RESET 0000000000
68 #define IC0_FORCE0_SET HW_REGISTER_RW( 0x7e002048 )
69 #define IC0_FORCE0_SET_MASK 0xffffffff
70 #define IC0_FORCE0_SET_WIDTH 32
71 #define IC0_FORCE0_SET_RESET 0000000000
72 #define IC0_FORCE1_SET HW_REGISTER_RW( 0x7e00204c )
73 #define IC0_FORCE1_SET_MASK 0xffffffff
74 #define IC0_FORCE1_SET_WIDTH 32
75 #define IC0_FORCE1_SET_RESET 0000000000
76 #define IC0_FORCE0_CLR HW_REGISTER_RW( 0x7e002050 )
77 #define IC0_FORCE0_CLR_MASK 0xffffffff
78 #define IC0_FORCE0_CLR_WIDTH 32
79 #define IC0_FORCE0_CLR_RESET 0000000000
80 #define IC0_FORCE1_CLR HW_REGISTER_RW( 0x7e002054 )
81 #define IC0_FORCE1_CLR_MASK 0xffffffff
82 #define IC0_FORCE1_CLR_WIDTH 32
83 #define IC0_FORCE1_CLR_RESET 0000000000
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