Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / israel_dsp_registers.h
1 /***************************************************************************
2 * Copyright (c) 1999-2005, Broadcom Corporation
3 * All Rights Reserved
4 * Confidential Property of Broadcom Corporation
5 *
6 *
7 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
8 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
9 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
10 *
11 * $brcm_Workfile: $
12 * $brcm_Revision: $
13 * $brcm_Date: $
14 *
15 * Module Description:
16 * DO NOT EDIT THIS FILE DIRECTLY
17 *
18 * This module was generated magically with RDB from a source description
19 * file. You must edit the source file for changes to be made to this file.
20 *
21 *
22 * Date: Generated on Mon Mar 28 16:48:45 2005
23 * MD5 Checksum ba913b07d554347688609e8e66f4943f
24 *
25 * Compiled with: RDB Utility combo_header.pl
26 * RDB Parser 3.0
27 * unknown unknown
28 * Perl Interpreter 5.006
29 * Operating System solaris
30 *
31 * Spec Versions: BG 01
32 * BVN_MFD 1
33 * CAP 1
34 * DSP_CTRL 03
35 * IN656 1
36 * ITFP 03
37 * LBG 1
38 * NET 1
39 * SCL 1
40 * VBI_DEC 03
41 * VD_TOP 5
42 * VIDEO_DEC 03
43 * VIP_CTRL 03
44 * VIP_L2 03
45 * VPP 03
46 *
47 * RDB Files: /projects/BCM7043/A0/work/gelias/bcm7043_a0/design/chip/rdb/bcm7043_a0.rdb
48 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vip_tops/rdb/vip_top_blockdef.rdb
49 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/cap/rdb/bvn_cap.rdb
50 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
51 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/mfd/rdb/bvn_mfd.rdb
52 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
53 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/scl/rdb/bvn_scl.rdb
54 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
55 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vpp/rdb/vpp.rdb
56 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
57 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/video_decoder/rdb/video_decoder_top.rdb
58 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/video_decoder/rdb/vd_major_revid.rdb
59 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/video_decoder/rdb/vd_minor_revid.rdb
60 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/656_dec/rdb/in656.rdb
61 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/656_dec/rdb/in656_revid.rdb
62 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/l2/rdb/vip_intr_ctrl2.rdb
63 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vnet/rdb/bvn_net.rdb
64 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/lbg/rdb/vip_lbg.rdb
65 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
66 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vbi_dec/rdb/vib_top.rdb
67 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vbi_dec/rdb/video_dec.rdb
68 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vbi_dec/rdb/vbi_dec.rdb
69 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/itfp/rdb/itfp.rdb
70 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
71 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vip_tops/rdb/vip_ctrl.rdb
72 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bsm/rdb/bg_top.rdb
73 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bsm/rdb/bg_ctrl.rdb
74 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/dsp/rdb/dsp_top.rdb
75 * /projects/BCM7043/A0/snapshot/bcm7043_a0/design/dsp/rdb/dsp_ctrl.rdb
76 *
77 * Revision History:
78 *
79 * $brcm_Log: $
80 *
81 ***************************************************************************/
82
83 #ifndef BCM7043_A0_DSP_REGISTERS_H__
84 #define BCM7043_A0_DSP_REGISTERS_H__
85
86 /***************************************************************************
87 *DSP_REGISTERS - DSP Internal
88 ***************************************************************************/
89 #define DSP_REGISTERS_UNIT_EXEC_FLAG 0x005e0000 /* Unit EXEC */
90 #define DSP_REGISTERS_UNIT_PROGRAM_COUNTER 0x005e0004 /* Unit Program Counter */
91 #define DSP_REGISTERS_DCT_BLOCKS_CBP 0x005e0008 /* Coded Block Pattern */
92 #define DSP_REGISTERS_NUM_OF_DCT0_COEFF 0x005e000c /* Non Zero Coeff in DCT-0 */
93 #define DSP_REGISTERS_NUM_OF_DCT1_COEFF 0x005e0010 /* Non Zero Coeff in DCT-1 */
94 #define DSP_REGISTERS_NUM_OF_DCT2_COEFF 0x005e0014 /* Non Zero Coeff in DCT-2 */
95 #define DSP_REGISTERS_NUM_OF_DCT3_COEFF 0x005e0018 /* Non Zero Coeff in DCT-3 */
96 #define DSP_REGISTERS_NUM_OF_DCT4_COEFF 0x005e001c /* Non Zero Coeff in DCT-4 */
97 #define DSP_REGISTERS_NUM_OF_DCT5_COEFF 0x005e0020 /* Non Zero Coeff in DCT-5 */
98 #define DSP_REGISTERS_SUM_OF_REGB_DCT0 0x005e0024 /* Summarize DCT-0 RB registers */
99 #define DSP_REGISTERS_SUM_OF_REGC_DCT0 0x005e0028 /* Summarize DCT-0 RC registers */
100 #define DSP_REGISTERS_SUM_OF_REGB_DCT1 0x005e002c /* Summarize DCT-1 RB registers */
101 #define DSP_REGISTERS_SUM_OF_REGC_DCT1 0x005e0030 /* Summarize DCT-1 RC registers */
102 #define DSP_REGISTERS_SUM_OF_REGB_DCT2 0x005e0034 /* Summarize DCT-2 RB registers */
103 #define DSP_REGISTERS_SUM_OF_REGC_DCT2 0x005e0038 /* Summarize DCT-2 RC registers */
104 #define DSP_REGISTERS_SUM_OF_REGB_DCT3 0x005e003c /* Summarize DCT-3 RB registers */
105 #define DSP_REGISTERS_SUM_OF_REGC_DCT3 0x005e0040 /* Summarize DCT-3 RC registers */
106 #define DSP_REGISTERS_SUM_OF_REGB_DCT4 0x005e0044 /* Summarize DCT-4 RB registers */
107 #define DSP_REGISTERS_SUM_OF_REGC_DCT4 0x005e0048 /* Summarize DCT-4 RC registers */
108 #define DSP_REGISTERS_SUM_OF_REGB_DCT5 0x005e004c /* Summarize DCT-5 RB registers */
109 #define DSP_REGISTERS_SUM_OF_REGC_DCT5 0x005e0050 /* Summarize DCT-5 RC registers */
110 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0 0x005e0054 /* MIN MAX Pixel value of DCT-0 */
111 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1 0x005e0058 /* MIN MAX Pixel value of DCT-1 */
112 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2 0x005e005c /* MIN MAX Pixel value of DCT-2 */
113 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3 0x005e0060 /* MIN MAX Pixel value of DCT-3 */
114 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4 0x005e0064 /* MIN MAX Pixel value of DCT-4 */
115 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5 0x005e0068 /* MIN MAX Pixel value of DCT-5 */
116 #define DSP_REGISTERS_REGISTER_R0 0x005e006c /* REGISTER_R0 - holds ARC calculation to controll DSP operation. */
117 #define DSP_REGISTERS_LOAD_PARAMETERS_41 0x005e0070 /* DESCRIPTOR1 - Loads DSP-Controller with Group 4 Parameters. */
118 #define DSP_REGISTERS_LOAD_PARAMETERS_42 0x005e0074 /* DESCRIPTOR2 - Loads DSP-Controller with Group 4 Parameters. */
119 #define DSP_REGISTERS_LOAD_PARAMETERS_43 0x005e0078 /* DESCRIPTOR3 - Loads DSP-Controller with Group 4 Parameters. */
120 #define DSP_REGISTERS_LOAD_PARAMETERS_44 0x005e007c /* DESCRIPTOR4 - Loads DSP-Controller with Group 4 Parameters. */
121 #define DSP_REGISTERS_LOAD_PARAMETERS_45 0x005e0080 /* DESCRIPTOR5 - Loads DSP-Controller with Group 4 Parameters. */
122 #define DSP_REGISTERS_INTERRUPT 0x005e0090 /* DSP INTERRUPTS. */
123 #define DSP_REGISTERS_MASK_INTERRUPT 0x005e0094 /* DSP MASK INTERRUPTS. */
124 #define DSP_REGISTERS_LOAD_PARAMETERS_0 0x005e00a0 /* LPAR0 - Loads DSP-Controller with Group 0 Parameters. */
125 #define DSP_REGISTERS_LOAD_PARAMETERS_1 0x005e00b0 /* LPAR1 - Loads DSP-Controller with Group 1 Parameters. */
126 #define DSP_REGISTERS_LOAD_PARAMETERS_2 0x005e00c0 /* LPAR2 - Loads DSP-Controller with Group 2 Parameters. */
127 #define DSP_REGISTERS_LOAD_PARAMETERS_3 0x005e00d0 /* LPAR3 - Loads DSP-Controller with Group 3 Parameters. */
128 #define DSP_REGISTERS_LOAD_PARAMETERS_4 0x005e00e0 /* LPAR4 - Loads DSP-Controller with Group 4 Parameters. */
129 #define DSP_REGISTERS_START_UNIT_PC 0x005e00f0 /* START DSP Operation */
130
131 /***************************************************************************
132 *UNIT_EXEC_FLAG - Unit EXEC
133 ***************************************************************************/
134 /* DSP_REGISTERS :: UNIT_EXEC_FLAG :: reserved0 [31:01] */
135 #define DSP_REGISTERS_UNIT_EXEC_FLAG_reserved0_MASK 0xfffffffe
136 #define DSP_REGISTERS_UNIT_EXEC_FLAG_reserved0_ALIGN 0
137 #define DSP_REGISTERS_UNIT_EXEC_FLAG_reserved0_BITS 31
138 #define DSP_REGISTERS_UNIT_EXEC_FLAG_reserved0_SHIFT 1
139
140 /* DSP_REGISTERS :: UNIT_EXEC_FLAG :: UNIT_EXEC [00:00] */
141 #define DSP_REGISTERS_UNIT_EXEC_FLAG_UNIT_EXEC_MASK 0x00000001
142 #define DSP_REGISTERS_UNIT_EXEC_FLAG_UNIT_EXEC_ALIGN 0
143 #define DSP_REGISTERS_UNIT_EXEC_FLAG_UNIT_EXEC_BITS 1
144 #define DSP_REGISTERS_UNIT_EXEC_FLAG_UNIT_EXEC_SHIFT 0
145
146 /***************************************************************************
147 *UNIT_PROGRAM_COUNTER - Unit Program Counter
148 ***************************************************************************/
149 /* DSP_REGISTERS :: UNIT_PROGRAM_COUNTER :: reserved0 [31:09] */
150 #define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_reserved0_MASK 0xfffffe00
151 #define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_reserved0_ALIGN 0
152 #define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_reserved0_BITS 23
153 #define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_reserved0_SHIFT 9
154
155 /* DSP_REGISTERS :: UNIT_PROGRAM_COUNTER :: UNIT_PC [08:00] */
156 #define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_UNIT_PC_MASK 0x000001ff
157 #define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_UNIT_PC_ALIGN 0
158 #define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_UNIT_PC_BITS 9
159 #define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_UNIT_PC_SHIFT 0
160
161 /***************************************************************************
162 *DCT_BLOCKS_CBP - Coded Block Pattern
163 ***************************************************************************/
164 /* DSP_REGISTERS :: DCT_BLOCKS_CBP :: reserved0 [31:06] */
165 #define DSP_REGISTERS_DCT_BLOCKS_CBP_reserved0_MASK 0xffffffc0
166 #define DSP_REGISTERS_DCT_BLOCKS_CBP_reserved0_ALIGN 0
167 #define DSP_REGISTERS_DCT_BLOCKS_CBP_reserved0_BITS 26
168 #define DSP_REGISTERS_DCT_BLOCKS_CBP_reserved0_SHIFT 6
169
170 /* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP5 [05:05] */
171 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP5_MASK 0x00000020
172 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP5_ALIGN 0
173 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP5_BITS 1
174 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP5_SHIFT 5
175
176 /* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP4 [04:04] */
177 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP4_MASK 0x00000010
178 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP4_ALIGN 0
179 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP4_BITS 1
180 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP4_SHIFT 4
181
182 /* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP3 [03:03] */
183 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP3_MASK 0x00000008
184 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP3_ALIGN 0
185 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP3_BITS 1
186 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP3_SHIFT 3
187
188 /* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP2 [02:02] */
189 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP2_MASK 0x00000004
190 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP2_ALIGN 0
191 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP2_BITS 1
192 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP2_SHIFT 2
193
194 /* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP1 [01:01] */
195 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP1_MASK 0x00000002
196 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP1_ALIGN 0
197 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP1_BITS 1
198 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP1_SHIFT 1
199
200 /* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP0 [00:00] */
201 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP0_MASK 0x00000001
202 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP0_ALIGN 0
203 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP0_BITS 1
204 #define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP0_SHIFT 0
205
206 /***************************************************************************
207 *NUM_OF_DCT0_COEFF - Non Zero Coeff in DCT-0
208 ***************************************************************************/
209 /* DSP_REGISTERS :: NUM_OF_DCT0_COEFF :: reserved0 [31:07] */
210 #define DSP_REGISTERS_NUM_OF_DCT0_COEFF_reserved0_MASK 0xffffff80
211 #define DSP_REGISTERS_NUM_OF_DCT0_COEFF_reserved0_ALIGN 0
212 #define DSP_REGISTERS_NUM_OF_DCT0_COEFF_reserved0_BITS 25
213 #define DSP_REGISTERS_NUM_OF_DCT0_COEFF_reserved0_SHIFT 7
214
215 /* DSP_REGISTERS :: NUM_OF_DCT0_COEFF :: NUM_OF_COEFF [06:00] */
216 #define DSP_REGISTERS_NUM_OF_DCT0_COEFF_NUM_OF_COEFF_MASK 0x0000007f
217 #define DSP_REGISTERS_NUM_OF_DCT0_COEFF_NUM_OF_COEFF_ALIGN 0
218 #define DSP_REGISTERS_NUM_OF_DCT0_COEFF_NUM_OF_COEFF_BITS 7
219 #define DSP_REGISTERS_NUM_OF_DCT0_COEFF_NUM_OF_COEFF_SHIFT 0
220
221 /***************************************************************************
222 *NUM_OF_DCT1_COEFF - Non Zero Coeff in DCT-1
223 ***************************************************************************/
224 /* DSP_REGISTERS :: NUM_OF_DCT1_COEFF :: reserved0 [31:07] */
225 #define DSP_REGISTERS_NUM_OF_DCT1_COEFF_reserved0_MASK 0xffffff80
226 #define DSP_REGISTERS_NUM_OF_DCT1_COEFF_reserved0_ALIGN 0
227 #define DSP_REGISTERS_NUM_OF_DCT1_COEFF_reserved0_BITS 25
228 #define DSP_REGISTERS_NUM_OF_DCT1_COEFF_reserved0_SHIFT 7
229
230 /* DSP_REGISTERS :: NUM_OF_DCT1_COEFF :: NUM_OF_COEFF [06:00] */
231 #define DSP_REGISTERS_NUM_OF_DCT1_COEFF_NUM_OF_COEFF_MASK 0x0000007f
232 #define DSP_REGISTERS_NUM_OF_DCT1_COEFF_NUM_OF_COEFF_ALIGN 0
233 #define DSP_REGISTERS_NUM_OF_DCT1_COEFF_NUM_OF_COEFF_BITS 7
234 #define DSP_REGISTERS_NUM_OF_DCT1_COEFF_NUM_OF_COEFF_SHIFT 0
235
236 /***************************************************************************
237 *NUM_OF_DCT2_COEFF - Non Zero Coeff in DCT-2
238 ***************************************************************************/
239 /* DSP_REGISTERS :: NUM_OF_DCT2_COEFF :: reserved0 [31:07] */
240 #define DSP_REGISTERS_NUM_OF_DCT2_COEFF_reserved0_MASK 0xffffff80
241 #define DSP_REGISTERS_NUM_OF_DCT2_COEFF_reserved0_ALIGN 0
242 #define DSP_REGISTERS_NUM_OF_DCT2_COEFF_reserved0_BITS 25
243 #define DSP_REGISTERS_NUM_OF_DCT2_COEFF_reserved0_SHIFT 7
244
245 /* DSP_REGISTERS :: NUM_OF_DCT2_COEFF :: NUM_OF_COEFF [06:00] */
246 #define DSP_REGISTERS_NUM_OF_DCT2_COEFF_NUM_OF_COEFF_MASK 0x0000007f
247 #define DSP_REGISTERS_NUM_OF_DCT2_COEFF_NUM_OF_COEFF_ALIGN 0
248 #define DSP_REGISTERS_NUM_OF_DCT2_COEFF_NUM_OF_COEFF_BITS 7
249 #define DSP_REGISTERS_NUM_OF_DCT2_COEFF_NUM_OF_COEFF_SHIFT 0
250
251 /***************************************************************************
252 *NUM_OF_DCT3_COEFF - Non Zero Coeff in DCT-3
253 ***************************************************************************/
254 /* DSP_REGISTERS :: NUM_OF_DCT3_COEFF :: reserved0 [31:07] */
255 #define DSP_REGISTERS_NUM_OF_DCT3_COEFF_reserved0_MASK 0xffffff80
256 #define DSP_REGISTERS_NUM_OF_DCT3_COEFF_reserved0_ALIGN 0
257 #define DSP_REGISTERS_NUM_OF_DCT3_COEFF_reserved0_BITS 25
258 #define DSP_REGISTERS_NUM_OF_DCT3_COEFF_reserved0_SHIFT 7
259
260 /* DSP_REGISTERS :: NUM_OF_DCT3_COEFF :: NUM_OF_COEFF [06:00] */
261 #define DSP_REGISTERS_NUM_OF_DCT3_COEFF_NUM_OF_COEFF_MASK 0x0000007f
262 #define DSP_REGISTERS_NUM_OF_DCT3_COEFF_NUM_OF_COEFF_ALIGN 0
263 #define DSP_REGISTERS_NUM_OF_DCT3_COEFF_NUM_OF_COEFF_BITS 7
264 #define DSP_REGISTERS_NUM_OF_DCT3_COEFF_NUM_OF_COEFF_SHIFT 0
265
266 /***************************************************************************
267 *NUM_OF_DCT4_COEFF - Non Zero Coeff in DCT-4
268 ***************************************************************************/
269 /* DSP_REGISTERS :: NUM_OF_DCT4_COEFF :: reserved0 [31:07] */
270 #define DSP_REGISTERS_NUM_OF_DCT4_COEFF_reserved0_MASK 0xffffff80
271 #define DSP_REGISTERS_NUM_OF_DCT4_COEFF_reserved0_ALIGN 0
272 #define DSP_REGISTERS_NUM_OF_DCT4_COEFF_reserved0_BITS 25
273 #define DSP_REGISTERS_NUM_OF_DCT4_COEFF_reserved0_SHIFT 7
274
275 /* DSP_REGISTERS :: NUM_OF_DCT4_COEFF :: NUM_OF_COEFF [06:00] */
276 #define DSP_REGISTERS_NUM_OF_DCT4_COEFF_NUM_OF_COEFF_MASK 0x0000007f
277 #define DSP_REGISTERS_NUM_OF_DCT4_COEFF_NUM_OF_COEFF_ALIGN 0
278 #define DSP_REGISTERS_NUM_OF_DCT4_COEFF_NUM_OF_COEFF_BITS 7
279 #define DSP_REGISTERS_NUM_OF_DCT4_COEFF_NUM_OF_COEFF_SHIFT 0
280
281 /***************************************************************************
282 *NUM_OF_DCT5_COEFF - Non Zero Coeff in DCT-5
283 ***************************************************************************/
284 /* DSP_REGISTERS :: NUM_OF_DCT5_COEFF :: reserved0 [31:07] */
285 #define DSP_REGISTERS_NUM_OF_DCT5_COEFF_reserved0_MASK 0xffffff80
286 #define DSP_REGISTERS_NUM_OF_DCT5_COEFF_reserved0_ALIGN 0
287 #define DSP_REGISTERS_NUM_OF_DCT5_COEFF_reserved0_BITS 25
288 #define DSP_REGISTERS_NUM_OF_DCT5_COEFF_reserved0_SHIFT 7
289
290 /* DSP_REGISTERS :: NUM_OF_DCT5_COEFF :: NUM_OF_COEFF [06:00] */
291 #define DSP_REGISTERS_NUM_OF_DCT5_COEFF_NUM_OF_COEFF_MASK 0x0000007f
292 #define DSP_REGISTERS_NUM_OF_DCT5_COEFF_NUM_OF_COEFF_ALIGN 0
293 #define DSP_REGISTERS_NUM_OF_DCT5_COEFF_NUM_OF_COEFF_BITS 7
294 #define DSP_REGISTERS_NUM_OF_DCT5_COEFF_NUM_OF_COEFF_SHIFT 0
295
296 /***************************************************************************
297 *SUM_OF_REGB_DCT0 - Summarize DCT-0 RB registers
298 ***************************************************************************/
299 /* DSP_REGISTERS :: SUM_OF_REGB_DCT0 :: SUM_OF_REGB [31:00] */
300 #define DSP_REGISTERS_SUM_OF_REGB_DCT0_SUM_OF_REGB_MASK 0xffffffff
301 #define DSP_REGISTERS_SUM_OF_REGB_DCT0_SUM_OF_REGB_ALIGN 0
302 #define DSP_REGISTERS_SUM_OF_REGB_DCT0_SUM_OF_REGB_BITS 32
303 #define DSP_REGISTERS_SUM_OF_REGB_DCT0_SUM_OF_REGB_SHIFT 0
304
305 /***************************************************************************
306 *SUM_OF_REGC_DCT0 - Summarize DCT-0 RC registers
307 ***************************************************************************/
308 /* DSP_REGISTERS :: SUM_OF_REGC_DCT0 :: SUM_OF_REGC [31:00] */
309 #define DSP_REGISTERS_SUM_OF_REGC_DCT0_SUM_OF_REGC_MASK 0xffffffff
310 #define DSP_REGISTERS_SUM_OF_REGC_DCT0_SUM_OF_REGC_ALIGN 0
311 #define DSP_REGISTERS_SUM_OF_REGC_DCT0_SUM_OF_REGC_BITS 32
312 #define DSP_REGISTERS_SUM_OF_REGC_DCT0_SUM_OF_REGC_SHIFT 0
313
314 /***************************************************************************
315 *SUM_OF_REGB_DCT1 - Summarize DCT-1 RB registers
316 ***************************************************************************/
317 /* DSP_REGISTERS :: SUM_OF_REGB_DCT1 :: SUM_OF_REGB [31:00] */
318 #define DSP_REGISTERS_SUM_OF_REGB_DCT1_SUM_OF_REGB_MASK 0xffffffff
319 #define DSP_REGISTERS_SUM_OF_REGB_DCT1_SUM_OF_REGB_ALIGN 0
320 #define DSP_REGISTERS_SUM_OF_REGB_DCT1_SUM_OF_REGB_BITS 32
321 #define DSP_REGISTERS_SUM_OF_REGB_DCT1_SUM_OF_REGB_SHIFT 0
322
323 /***************************************************************************
324 *SUM_OF_REGC_DCT1 - Summarize DCT-1 RC registers
325 ***************************************************************************/
326 /* DSP_REGISTERS :: SUM_OF_REGC_DCT1 :: SUM_OF_REGC [31:00] */
327 #define DSP_REGISTERS_SUM_OF_REGC_DCT1_SUM_OF_REGC_MASK 0xffffffff
328 #define DSP_REGISTERS_SUM_OF_REGC_DCT1_SUM_OF_REGC_ALIGN 0
329 #define DSP_REGISTERS_SUM_OF_REGC_DCT1_SUM_OF_REGC_BITS 32
330 #define DSP_REGISTERS_SUM_OF_REGC_DCT1_SUM_OF_REGC_SHIFT 0
331
332 /***************************************************************************
333 *SUM_OF_REGB_DCT2 - Summarize DCT-2 RB registers
334 ***************************************************************************/
335 /* DSP_REGISTERS :: SUM_OF_REGB_DCT2 :: SUM_OF_REGB [31:00] */
336 #define DSP_REGISTERS_SUM_OF_REGB_DCT2_SUM_OF_REGB_MASK 0xffffffff
337 #define DSP_REGISTERS_SUM_OF_REGB_DCT2_SUM_OF_REGB_ALIGN 0
338 #define DSP_REGISTERS_SUM_OF_REGB_DCT2_SUM_OF_REGB_BITS 32
339 #define DSP_REGISTERS_SUM_OF_REGB_DCT2_SUM_OF_REGB_SHIFT 0
340
341 /***************************************************************************
342 *SUM_OF_REGC_DCT2 - Summarize DCT-2 RC registers
343 ***************************************************************************/
344 /* DSP_REGISTERS :: SUM_OF_REGC_DCT2 :: SUM_OF_REGC [31:00] */
345 #define DSP_REGISTERS_SUM_OF_REGC_DCT2_SUM_OF_REGC_MASK 0xffffffff
346 #define DSP_REGISTERS_SUM_OF_REGC_DCT2_SUM_OF_REGC_ALIGN 0
347 #define DSP_REGISTERS_SUM_OF_REGC_DCT2_SUM_OF_REGC_BITS 32
348 #define DSP_REGISTERS_SUM_OF_REGC_DCT2_SUM_OF_REGC_SHIFT 0
349
350 /***************************************************************************
351 *SUM_OF_REGB_DCT3 - Summarize DCT-3 RB registers
352 ***************************************************************************/
353 /* DSP_REGISTERS :: SUM_OF_REGB_DCT3 :: SUM_OF_REGB [31:00] */
354 #define DSP_REGISTERS_SUM_OF_REGB_DCT3_SUM_OF_REGB_MASK 0xffffffff
355 #define DSP_REGISTERS_SUM_OF_REGB_DCT3_SUM_OF_REGB_ALIGN 0
356 #define DSP_REGISTERS_SUM_OF_REGB_DCT3_SUM_OF_REGB_BITS 32
357 #define DSP_REGISTERS_SUM_OF_REGB_DCT3_SUM_OF_REGB_SHIFT 0
358
359 /***************************************************************************
360 *SUM_OF_REGC_DCT3 - Summarize DCT-3 RC registers
361 ***************************************************************************/
362 /* DSP_REGISTERS :: SUM_OF_REGC_DCT3 :: SUM_OF_REGC [31:00] */
363 #define DSP_REGISTERS_SUM_OF_REGC_DCT3_SUM_OF_REGC_MASK 0xffffffff
364 #define DSP_REGISTERS_SUM_OF_REGC_DCT3_SUM_OF_REGC_ALIGN 0
365 #define DSP_REGISTERS_SUM_OF_REGC_DCT3_SUM_OF_REGC_BITS 32
366 #define DSP_REGISTERS_SUM_OF_REGC_DCT3_SUM_OF_REGC_SHIFT 0
367
368 /***************************************************************************
369 *SUM_OF_REGB_DCT4 - Summarize DCT-4 RB registers
370 ***************************************************************************/
371 /* DSP_REGISTERS :: SUM_OF_REGB_DCT4 :: SUM_OF_REGB [31:00] */
372 #define DSP_REGISTERS_SUM_OF_REGB_DCT4_SUM_OF_REGB_MASK 0xffffffff
373 #define DSP_REGISTERS_SUM_OF_REGB_DCT4_SUM_OF_REGB_ALIGN 0
374 #define DSP_REGISTERS_SUM_OF_REGB_DCT4_SUM_OF_REGB_BITS 32
375 #define DSP_REGISTERS_SUM_OF_REGB_DCT4_SUM_OF_REGB_SHIFT 0
376
377 /***************************************************************************
378 *SUM_OF_REGC_DCT4 - Summarize DCT-4 RC registers
379 ***************************************************************************/
380 /* DSP_REGISTERS :: SUM_OF_REGC_DCT4 :: SUM_OF_REGC [31:00] */
381 #define DSP_REGISTERS_SUM_OF_REGC_DCT4_SUM_OF_REGC_MASK 0xffffffff
382 #define DSP_REGISTERS_SUM_OF_REGC_DCT4_SUM_OF_REGC_ALIGN 0
383 #define DSP_REGISTERS_SUM_OF_REGC_DCT4_SUM_OF_REGC_BITS 32
384 #define DSP_REGISTERS_SUM_OF_REGC_DCT4_SUM_OF_REGC_SHIFT 0
385
386 /***************************************************************************
387 *SUM_OF_REGB_DCT5 - Summarize DCT-5 RB registers
388 ***************************************************************************/
389 /* DSP_REGISTERS :: SUM_OF_REGB_DCT5 :: SUM_OF_REGB [31:00] */
390 #define DSP_REGISTERS_SUM_OF_REGB_DCT5_SUM_OF_REGB_MASK 0xffffffff
391 #define DSP_REGISTERS_SUM_OF_REGB_DCT5_SUM_OF_REGB_ALIGN 0
392 #define DSP_REGISTERS_SUM_OF_REGB_DCT5_SUM_OF_REGB_BITS 32
393 #define DSP_REGISTERS_SUM_OF_REGB_DCT5_SUM_OF_REGB_SHIFT 0
394
395 /***************************************************************************
396 *SUM_OF_REGC_DCT5 - Summarize DCT-5 RC registers
397 ***************************************************************************/
398 /* DSP_REGISTERS :: SUM_OF_REGC_DCT5 :: SUM_OF_REGC [31:00] */
399 #define DSP_REGISTERS_SUM_OF_REGC_DCT5_SUM_OF_REGC_MASK 0xffffffff
400 #define DSP_REGISTERS_SUM_OF_REGC_DCT5_SUM_OF_REGC_ALIGN 0
401 #define DSP_REGISTERS_SUM_OF_REGC_DCT5_SUM_OF_REGC_BITS 32
402 #define DSP_REGISTERS_SUM_OF_REGC_DCT5_SUM_OF_REGC_SHIFT 0
403
404 /***************************************************************************
405 *MIN_MAX_PIXEL_DCT0 - MIN MAX Pixel value of DCT-0
406 ***************************************************************************/
407 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT0 :: reserved0 [31:18] */
408 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_reserved0_MASK 0xfffc0000
409 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_reserved0_ALIGN 0
410 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_reserved0_BITS 14
411 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_reserved0_SHIFT 18
412
413 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT0 :: MIN_PIXEL [17:09] */
414 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MIN_PIXEL_MASK 0x0003fe00
415 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MIN_PIXEL_ALIGN 0
416 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MIN_PIXEL_BITS 9
417 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MIN_PIXEL_SHIFT 9
418
419 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT0 :: MAX_PIXEL [08:00] */
420 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MAX_PIXEL_MASK 0x000001ff
421 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MAX_PIXEL_ALIGN 0
422 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MAX_PIXEL_BITS 9
423 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MAX_PIXEL_SHIFT 0
424
425 /***************************************************************************
426 *MIN_MAX_PIXEL_DCT1 - MIN MAX Pixel value of DCT-1
427 ***************************************************************************/
428 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT1 :: reserved0 [31:18] */
429 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_reserved0_MASK 0xfffc0000
430 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_reserved0_ALIGN 0
431 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_reserved0_BITS 14
432 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_reserved0_SHIFT 18
433
434 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT1 :: MIN_PIXEL [17:09] */
435 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MIN_PIXEL_MASK 0x0003fe00
436 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MIN_PIXEL_ALIGN 0
437 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MIN_PIXEL_BITS 9
438 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MIN_PIXEL_SHIFT 9
439
440 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT1 :: MAX_PIXEL [08:00] */
441 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MAX_PIXEL_MASK 0x000001ff
442 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MAX_PIXEL_ALIGN 0
443 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MAX_PIXEL_BITS 9
444 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MAX_PIXEL_SHIFT 0
445
446 /***************************************************************************
447 *MIN_MAX_PIXEL_DCT2 - MIN MAX Pixel value of DCT-2
448 ***************************************************************************/
449 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT2 :: reserved0 [31:18] */
450 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_reserved0_MASK 0xfffc0000
451 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_reserved0_ALIGN 0
452 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_reserved0_BITS 14
453 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_reserved0_SHIFT 18
454
455 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT2 :: MIN_PIXEL [17:09] */
456 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MIN_PIXEL_MASK 0x0003fe00
457 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MIN_PIXEL_ALIGN 0
458 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MIN_PIXEL_BITS 9
459 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MIN_PIXEL_SHIFT 9
460
461 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT2 :: MAX_PIXEL [08:00] */
462 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MAX_PIXEL_MASK 0x000001ff
463 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MAX_PIXEL_ALIGN 0
464 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MAX_PIXEL_BITS 9
465 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MAX_PIXEL_SHIFT 0
466
467 /***************************************************************************
468 *MIN_MAX_PIXEL_DCT3 - MIN MAX Pixel value of DCT-3
469 ***************************************************************************/
470 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT3 :: reserved0 [31:18] */
471 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_reserved0_MASK 0xfffc0000
472 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_reserved0_ALIGN 0
473 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_reserved0_BITS 14
474 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_reserved0_SHIFT 18
475
476 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT3 :: MIN_PIXEL [17:09] */
477 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MIN_PIXEL_MASK 0x0003fe00
478 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MIN_PIXEL_ALIGN 0
479 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MIN_PIXEL_BITS 9
480 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MIN_PIXEL_SHIFT 9
481
482 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT3 :: MAX_PIXEL [08:00] */
483 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MAX_PIXEL_MASK 0x000001ff
484 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MAX_PIXEL_ALIGN 0
485 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MAX_PIXEL_BITS 9
486 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MAX_PIXEL_SHIFT 0
487
488 /***************************************************************************
489 *MIN_MAX_PIXEL_DCT4 - MIN MAX Pixel value of DCT-4
490 ***************************************************************************/
491 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT4 :: reserved0 [31:18] */
492 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_reserved0_MASK 0xfffc0000
493 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_reserved0_ALIGN 0
494 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_reserved0_BITS 14
495 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_reserved0_SHIFT 18
496
497 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT4 :: MIN_PIXEL [17:09] */
498 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MIN_PIXEL_MASK 0x0003fe00
499 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MIN_PIXEL_ALIGN 0
500 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MIN_PIXEL_BITS 9
501 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MIN_PIXEL_SHIFT 9
502
503 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT4 :: MAX_PIXEL [08:00] */
504 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MAX_PIXEL_MASK 0x000001ff
505 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MAX_PIXEL_ALIGN 0
506 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MAX_PIXEL_BITS 9
507 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MAX_PIXEL_SHIFT 0
508
509 /***************************************************************************
510 *MIN_MAX_PIXEL_DCT5 - MIN MAX Pixel value of DCT-5
511 ***************************************************************************/
512 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT5 :: reserved0 [31:18] */
513 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_reserved0_MASK 0xfffc0000
514 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_reserved0_ALIGN 0
515 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_reserved0_BITS 14
516 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_reserved0_SHIFT 18
517
518 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT5 :: MIN_PIXEL [17:09] */
519 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MIN_PIXEL_MASK 0x0003fe00
520 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MIN_PIXEL_ALIGN 0
521 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MIN_PIXEL_BITS 9
522 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MIN_PIXEL_SHIFT 9
523
524 /* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT5 :: MAX_PIXEL [08:00] */
525 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MAX_PIXEL_MASK 0x000001ff
526 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MAX_PIXEL_ALIGN 0
527 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MAX_PIXEL_BITS 9
528 #define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MAX_PIXEL_SHIFT 0
529
530 /***************************************************************************
531 *REGISTER_R0 - REGISTER_R0 - holds ARC calculation to controll DSP operation.
532 ***************************************************************************/
533 /* DSP_REGISTERS :: REGISTER_R0 :: REG_R0 [31:00] */
534 #define DSP_REGISTERS_REGISTER_R0_REG_R0_MASK 0xffffffff
535 #define DSP_REGISTERS_REGISTER_R0_REG_R0_ALIGN 0
536 #define DSP_REGISTERS_REGISTER_R0_REG_R0_BITS 32
537 #define DSP_REGISTERS_REGISTER_R0_REG_R0_SHIFT 0
538
539 /***************************************************************************
540 *LOAD_PARAMETERS_41 - DESCRIPTOR1 - Loads DSP-Controller with Group 4 Parameters.
541 ***************************************************************************/
542 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: reserved0 [31:25] */
543 #define DSP_REGISTERS_LOAD_PARAMETERS_41_reserved0_MASK 0xfe000000
544 #define DSP_REGISTERS_LOAD_PARAMETERS_41_reserved0_ALIGN 0
545 #define DSP_REGISTERS_LOAD_PARAMETERS_41_reserved0_BITS 7
546 #define DSP_REGISTERS_LOAD_PARAMETERS_41_reserved0_SHIFT 25
547
548 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: LOAD_NEXT_DESC [24:24] */
549 #define DSP_REGISTERS_LOAD_PARAMETERS_41_LOAD_NEXT_DESC_MASK 0x01000000
550 #define DSP_REGISTERS_LOAD_PARAMETERS_41_LOAD_NEXT_DESC_ALIGN 0
551 #define DSP_REGISTERS_LOAD_PARAMETERS_41_LOAD_NEXT_DESC_BITS 1
552 #define DSP_REGISTERS_LOAD_PARAMETERS_41_LOAD_NEXT_DESC_SHIFT 24
553
554 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: BUS_TRANSACTION [23:18] */
555 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_TRANSACTION_MASK 0x00fc0000
556 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_TRANSACTION_ALIGN 0
557 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_TRANSACTION_BITS 6
558 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_TRANSACTION_SHIFT 18
559
560 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: BUS_WIDTH [17:16] */
561 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_MASK 0x00030000
562 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_ALIGN 0
563 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_BITS 2
564 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_SHIFT 16
565 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_NONE 0
566 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_CMB 1
567 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_R_INVR 2
568 #define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_Q 3
569
570 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: CR [15:15] */
571 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CR_MASK 0x00008000
572 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CR_ALIGN 0
573 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CR_BITS 1
574 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CR_SHIFT 15
575
576 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: CB [14:14] */
577 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CB_MASK 0x00004000
578 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CB_ALIGN 0
579 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CB_BITS 1
580 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CB_SHIFT 14
581
582 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: RECON_INVR_DATA [13:13] */
583 #define DSP_REGISTERS_LOAD_PARAMETERS_41_RECON_INVR_DATA_MASK 0x00002000
584 #define DSP_REGISTERS_LOAD_PARAMETERS_41_RECON_INVR_DATA_ALIGN 0
585 #define DSP_REGISTERS_LOAD_PARAMETERS_41_RECON_INVR_DATA_BITS 1
586 #define DSP_REGISTERS_LOAD_PARAMETERS_41_RECON_INVR_DATA_SHIFT 13
587
588 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: Q_FLAG [12:12] */
589 #define DSP_REGISTERS_LOAD_PARAMETERS_41_Q_FLAG_MASK 0x00001000
590 #define DSP_REGISTERS_LOAD_PARAMETERS_41_Q_FLAG_ALIGN 0
591 #define DSP_REGISTERS_LOAD_PARAMETERS_41_Q_FLAG_BITS 1
592 #define DSP_REGISTERS_LOAD_PARAMETERS_41_Q_FLAG_SHIFT 12
593
594 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: INVR_FLAG [11:11] */
595 #define DSP_REGISTERS_LOAD_PARAMETERS_41_INVR_FLAG_MASK 0x00000800
596 #define DSP_REGISTERS_LOAD_PARAMETERS_41_INVR_FLAG_ALIGN 0
597 #define DSP_REGISTERS_LOAD_PARAMETERS_41_INVR_FLAG_BITS 1
598 #define DSP_REGISTERS_LOAD_PARAMETERS_41_INVR_FLAG_SHIFT 11
599
600 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: R_FLAG [10:10] */
601 #define DSP_REGISTERS_LOAD_PARAMETERS_41_R_FLAG_MASK 0x00000400
602 #define DSP_REGISTERS_LOAD_PARAMETERS_41_R_FLAG_ALIGN 0
603 #define DSP_REGISTERS_LOAD_PARAMETERS_41_R_FLAG_BITS 1
604 #define DSP_REGISTERS_LOAD_PARAMETERS_41_R_FLAG_SHIFT 10
605
606 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: CMB_FLAG [09:09] */
607 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CMB_FLAG_MASK 0x00000200
608 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CMB_FLAG_ALIGN 0
609 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CMB_FLAG_BITS 1
610 #define DSP_REGISTERS_LOAD_PARAMETERS_41_CMB_FLAG_SHIFT 9
611
612 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: MEM_WA [08:06] */
613 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_WA_MASK 0x000001c0
614 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_WA_ALIGN 0
615 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_WA_BITS 3
616 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_WA_SHIFT 6
617
618 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: MEM_RA_1 [05:03] */
619 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_1_MASK 0x00000038
620 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_1_ALIGN 0
621 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_1_BITS 3
622 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_1_SHIFT 3
623
624 /* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: MEM_RA_0 [02:00] */
625 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_0_MASK 0x00000007
626 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_0_ALIGN 0
627 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_0_BITS 3
628 #define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_0_SHIFT 0
629
630 /***************************************************************************
631 *LOAD_PARAMETERS_42 - DESCRIPTOR2 - Loads DSP-Controller with Group 4 Parameters.
632 ***************************************************************************/
633 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: reserved0 [31:25] */
634 #define DSP_REGISTERS_LOAD_PARAMETERS_42_reserved0_MASK 0xfe000000
635 #define DSP_REGISTERS_LOAD_PARAMETERS_42_reserved0_ALIGN 0
636 #define DSP_REGISTERS_LOAD_PARAMETERS_42_reserved0_BITS 7
637 #define DSP_REGISTERS_LOAD_PARAMETERS_42_reserved0_SHIFT 25
638
639 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: LOAD_NEXT_DESC [24:24] */
640 #define DSP_REGISTERS_LOAD_PARAMETERS_42_LOAD_NEXT_DESC_MASK 0x01000000
641 #define DSP_REGISTERS_LOAD_PARAMETERS_42_LOAD_NEXT_DESC_ALIGN 0
642 #define DSP_REGISTERS_LOAD_PARAMETERS_42_LOAD_NEXT_DESC_BITS 1
643 #define DSP_REGISTERS_LOAD_PARAMETERS_42_LOAD_NEXT_DESC_SHIFT 24
644
645 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: BUS_TRANSACTION [23:18] */
646 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_TRANSACTION_MASK 0x00fc0000
647 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_TRANSACTION_ALIGN 0
648 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_TRANSACTION_BITS 6
649 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_TRANSACTION_SHIFT 18
650
651 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: BUS_WIDTH [17:16] */
652 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_MASK 0x00030000
653 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_ALIGN 0
654 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_BITS 2
655 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_SHIFT 16
656 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_NONE 0
657 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_CMB 1
658 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_R_INVR 2
659 #define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_Q 3
660
661 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: CR [15:15] */
662 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CR_MASK 0x00008000
663 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CR_ALIGN 0
664 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CR_BITS 1
665 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CR_SHIFT 15
666
667 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: CB [14:14] */
668 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CB_MASK 0x00004000
669 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CB_ALIGN 0
670 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CB_BITS 1
671 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CB_SHIFT 14
672
673 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: RECON_INVR_DATA [13:13] */
674 #define DSP_REGISTERS_LOAD_PARAMETERS_42_RECON_INVR_DATA_MASK 0x00002000
675 #define DSP_REGISTERS_LOAD_PARAMETERS_42_RECON_INVR_DATA_ALIGN 0
676 #define DSP_REGISTERS_LOAD_PARAMETERS_42_RECON_INVR_DATA_BITS 1
677 #define DSP_REGISTERS_LOAD_PARAMETERS_42_RECON_INVR_DATA_SHIFT 13
678
679 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: Q_FLAG [12:12] */
680 #define DSP_REGISTERS_LOAD_PARAMETERS_42_Q_FLAG_MASK 0x00001000
681 #define DSP_REGISTERS_LOAD_PARAMETERS_42_Q_FLAG_ALIGN 0
682 #define DSP_REGISTERS_LOAD_PARAMETERS_42_Q_FLAG_BITS 1
683 #define DSP_REGISTERS_LOAD_PARAMETERS_42_Q_FLAG_SHIFT 12
684
685 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: INVR_FLAG [11:11] */
686 #define DSP_REGISTERS_LOAD_PARAMETERS_42_INVR_FLAG_MASK 0x00000800
687 #define DSP_REGISTERS_LOAD_PARAMETERS_42_INVR_FLAG_ALIGN 0
688 #define DSP_REGISTERS_LOAD_PARAMETERS_42_INVR_FLAG_BITS 1
689 #define DSP_REGISTERS_LOAD_PARAMETERS_42_INVR_FLAG_SHIFT 11
690
691 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: R_FLAG [10:10] */
692 #define DSP_REGISTERS_LOAD_PARAMETERS_42_R_FLAG_MASK 0x00000400
693 #define DSP_REGISTERS_LOAD_PARAMETERS_42_R_FLAG_ALIGN 0
694 #define DSP_REGISTERS_LOAD_PARAMETERS_42_R_FLAG_BITS 1
695 #define DSP_REGISTERS_LOAD_PARAMETERS_42_R_FLAG_SHIFT 10
696
697 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: CMB_FLAG [09:09] */
698 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CMB_FLAG_MASK 0x00000200
699 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CMB_FLAG_ALIGN 0
700 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CMB_FLAG_BITS 1
701 #define DSP_REGISTERS_LOAD_PARAMETERS_42_CMB_FLAG_SHIFT 9
702
703 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: MEM_WA [08:06] */
704 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_WA_MASK 0x000001c0
705 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_WA_ALIGN 0
706 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_WA_BITS 3
707 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_WA_SHIFT 6
708
709 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: MEM_RA_1 [05:03] */
710 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_1_MASK 0x00000038
711 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_1_ALIGN 0
712 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_1_BITS 3
713 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_1_SHIFT 3
714
715 /* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: MEM_RA_0 [02:00] */
716 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_0_MASK 0x00000007
717 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_0_ALIGN 0
718 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_0_BITS 3
719 #define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_0_SHIFT 0
720
721 /***************************************************************************
722 *LOAD_PARAMETERS_43 - DESCRIPTOR3 - Loads DSP-Controller with Group 4 Parameters.
723 ***************************************************************************/
724 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: reserved0 [31:25] */
725 #define DSP_REGISTERS_LOAD_PARAMETERS_43_reserved0_MASK 0xfe000000
726 #define DSP_REGISTERS_LOAD_PARAMETERS_43_reserved0_ALIGN 0
727 #define DSP_REGISTERS_LOAD_PARAMETERS_43_reserved0_BITS 7
728 #define DSP_REGISTERS_LOAD_PARAMETERS_43_reserved0_SHIFT 25
729
730 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: LOAD_NEXT_DESC [24:24] */
731 #define DSP_REGISTERS_LOAD_PARAMETERS_43_LOAD_NEXT_DESC_MASK 0x01000000
732 #define DSP_REGISTERS_LOAD_PARAMETERS_43_LOAD_NEXT_DESC_ALIGN 0
733 #define DSP_REGISTERS_LOAD_PARAMETERS_43_LOAD_NEXT_DESC_BITS 1
734 #define DSP_REGISTERS_LOAD_PARAMETERS_43_LOAD_NEXT_DESC_SHIFT 24
735
736 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: BUS_TRANSACTION [23:18] */
737 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_TRANSACTION_MASK 0x00fc0000
738 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_TRANSACTION_ALIGN 0
739 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_TRANSACTION_BITS 6
740 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_TRANSACTION_SHIFT 18
741
742 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: BUS_WIDTH [17:16] */
743 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_MASK 0x00030000
744 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_ALIGN 0
745 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_BITS 2
746 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_SHIFT 16
747 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_NONE 0
748 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_CMB 1
749 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_R_INVR 2
750 #define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_Q 3
751
752 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: CR [15:15] */
753 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CR_MASK 0x00008000
754 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CR_ALIGN 0
755 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CR_BITS 1
756 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CR_SHIFT 15
757
758 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: CB [14:14] */
759 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CB_MASK 0x00004000
760 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CB_ALIGN 0
761 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CB_BITS 1
762 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CB_SHIFT 14
763
764 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: RECON_INVR_DATA [13:13] */
765 #define DSP_REGISTERS_LOAD_PARAMETERS_43_RECON_INVR_DATA_MASK 0x00002000
766 #define DSP_REGISTERS_LOAD_PARAMETERS_43_RECON_INVR_DATA_ALIGN 0
767 #define DSP_REGISTERS_LOAD_PARAMETERS_43_RECON_INVR_DATA_BITS 1
768 #define DSP_REGISTERS_LOAD_PARAMETERS_43_RECON_INVR_DATA_SHIFT 13
769
770 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: Q_FLAG [12:12] */
771 #define DSP_REGISTERS_LOAD_PARAMETERS_43_Q_FLAG_MASK 0x00001000
772 #define DSP_REGISTERS_LOAD_PARAMETERS_43_Q_FLAG_ALIGN 0
773 #define DSP_REGISTERS_LOAD_PARAMETERS_43_Q_FLAG_BITS 1
774 #define DSP_REGISTERS_LOAD_PARAMETERS_43_Q_FLAG_SHIFT 12
775
776 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: INVR_FLAG [11:11] */
777 #define DSP_REGISTERS_LOAD_PARAMETERS_43_INVR_FLAG_MASK 0x00000800
778 #define DSP_REGISTERS_LOAD_PARAMETERS_43_INVR_FLAG_ALIGN 0
779 #define DSP_REGISTERS_LOAD_PARAMETERS_43_INVR_FLAG_BITS 1
780 #define DSP_REGISTERS_LOAD_PARAMETERS_43_INVR_FLAG_SHIFT 11
781
782 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: R_FLAG [10:10] */
783 #define DSP_REGISTERS_LOAD_PARAMETERS_43_R_FLAG_MASK 0x00000400
784 #define DSP_REGISTERS_LOAD_PARAMETERS_43_R_FLAG_ALIGN 0
785 #define DSP_REGISTERS_LOAD_PARAMETERS_43_R_FLAG_BITS 1
786 #define DSP_REGISTERS_LOAD_PARAMETERS_43_R_FLAG_SHIFT 10
787
788 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: CMB_FLAG [09:09] */
789 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CMB_FLAG_MASK 0x00000200
790 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CMB_FLAG_ALIGN 0
791 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CMB_FLAG_BITS 1
792 #define DSP_REGISTERS_LOAD_PARAMETERS_43_CMB_FLAG_SHIFT 9
793
794 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: MEM_WA [08:06] */
795 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_WA_MASK 0x000001c0
796 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_WA_ALIGN 0
797 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_WA_BITS 3
798 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_WA_SHIFT 6
799
800 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: MEM_RA_1 [05:03] */
801 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_1_MASK 0x00000038
802 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_1_ALIGN 0
803 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_1_BITS 3
804 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_1_SHIFT 3
805
806 /* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: MEM_RA_0 [02:00] */
807 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_0_MASK 0x00000007
808 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_0_ALIGN 0
809 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_0_BITS 3
810 #define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_0_SHIFT 0
811
812 /***************************************************************************
813 *LOAD_PARAMETERS_44 - DESCRIPTOR4 - Loads DSP-Controller with Group 4 Parameters.
814 ***************************************************************************/
815 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: reserved0 [31:25] */
816 #define DSP_REGISTERS_LOAD_PARAMETERS_44_reserved0_MASK 0xfe000000
817 #define DSP_REGISTERS_LOAD_PARAMETERS_44_reserved0_ALIGN 0
818 #define DSP_REGISTERS_LOAD_PARAMETERS_44_reserved0_BITS 7
819 #define DSP_REGISTERS_LOAD_PARAMETERS_44_reserved0_SHIFT 25
820
821 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: LOAD_NEXT_DESC [24:24] */
822 #define DSP_REGISTERS_LOAD_PARAMETERS_44_LOAD_NEXT_DESC_MASK 0x01000000
823 #define DSP_REGISTERS_LOAD_PARAMETERS_44_LOAD_NEXT_DESC_ALIGN 0
824 #define DSP_REGISTERS_LOAD_PARAMETERS_44_LOAD_NEXT_DESC_BITS 1
825 #define DSP_REGISTERS_LOAD_PARAMETERS_44_LOAD_NEXT_DESC_SHIFT 24
826
827 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: BUS_TRANSACTION [23:18] */
828 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_TRANSACTION_MASK 0x00fc0000
829 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_TRANSACTION_ALIGN 0
830 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_TRANSACTION_BITS 6
831 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_TRANSACTION_SHIFT 18
832
833 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: BUS_WIDTH [17:16] */
834 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_MASK 0x00030000
835 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_ALIGN 0
836 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_BITS 2
837 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_SHIFT 16
838 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_NONE 0
839 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_CMB 1
840 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_R_INVR 2
841 #define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_Q 3
842
843 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: CR [15:15] */
844 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CR_MASK 0x00008000
845 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CR_ALIGN 0
846 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CR_BITS 1
847 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CR_SHIFT 15
848
849 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: CB [14:14] */
850 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CB_MASK 0x00004000
851 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CB_ALIGN 0
852 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CB_BITS 1
853 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CB_SHIFT 14
854
855 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: RECON_INVR_DATA [13:13] */
856 #define DSP_REGISTERS_LOAD_PARAMETERS_44_RECON_INVR_DATA_MASK 0x00002000
857 #define DSP_REGISTERS_LOAD_PARAMETERS_44_RECON_INVR_DATA_ALIGN 0
858 #define DSP_REGISTERS_LOAD_PARAMETERS_44_RECON_INVR_DATA_BITS 1
859 #define DSP_REGISTERS_LOAD_PARAMETERS_44_RECON_INVR_DATA_SHIFT 13
860
861 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: Q_FLAG [12:12] */
862 #define DSP_REGISTERS_LOAD_PARAMETERS_44_Q_FLAG_MASK 0x00001000
863 #define DSP_REGISTERS_LOAD_PARAMETERS_44_Q_FLAG_ALIGN 0
864 #define DSP_REGISTERS_LOAD_PARAMETERS_44_Q_FLAG_BITS 1
865 #define DSP_REGISTERS_LOAD_PARAMETERS_44_Q_FLAG_SHIFT 12
866
867 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: INVR_FLAG [11:11] */
868 #define DSP_REGISTERS_LOAD_PARAMETERS_44_INVR_FLAG_MASK 0x00000800
869 #define DSP_REGISTERS_LOAD_PARAMETERS_44_INVR_FLAG_ALIGN 0
870 #define DSP_REGISTERS_LOAD_PARAMETERS_44_INVR_FLAG_BITS 1
871 #define DSP_REGISTERS_LOAD_PARAMETERS_44_INVR_FLAG_SHIFT 11
872
873 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: R_FLAG [10:10] */
874 #define DSP_REGISTERS_LOAD_PARAMETERS_44_R_FLAG_MASK 0x00000400
875 #define DSP_REGISTERS_LOAD_PARAMETERS_44_R_FLAG_ALIGN 0
876 #define DSP_REGISTERS_LOAD_PARAMETERS_44_R_FLAG_BITS 1
877 #define DSP_REGISTERS_LOAD_PARAMETERS_44_R_FLAG_SHIFT 10
878
879 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: CMB_FLAG [09:09] */
880 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CMB_FLAG_MASK 0x00000200
881 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CMB_FLAG_ALIGN 0
882 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CMB_FLAG_BITS 1
883 #define DSP_REGISTERS_LOAD_PARAMETERS_44_CMB_FLAG_SHIFT 9
884
885 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: MEM_WA [08:06] */
886 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_WA_MASK 0x000001c0
887 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_WA_ALIGN 0
888 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_WA_BITS 3
889 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_WA_SHIFT 6
890
891 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: MEM_RA_1 [05:03] */
892 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_1_MASK 0x00000038
893 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_1_ALIGN 0
894 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_1_BITS 3
895 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_1_SHIFT 3
896
897 /* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: MEM_RA_0 [02:00] */
898 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_0_MASK 0x00000007
899 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_0_ALIGN 0
900 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_0_BITS 3
901 #define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_0_SHIFT 0
902
903 /***************************************************************************
904 *LOAD_PARAMETERS_45 - DESCRIPTOR5 - Loads DSP-Controller with Group 4 Parameters.
905 ***************************************************************************/
906 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: reserved0 [31:25] */
907 #define DSP_REGISTERS_LOAD_PARAMETERS_45_reserved0_MASK 0xfe000000
908 #define DSP_REGISTERS_LOAD_PARAMETERS_45_reserved0_ALIGN 0
909 #define DSP_REGISTERS_LOAD_PARAMETERS_45_reserved0_BITS 7
910 #define DSP_REGISTERS_LOAD_PARAMETERS_45_reserved0_SHIFT 25
911
912 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: LOAD_NEXT_DESC [24:24] */
913 #define DSP_REGISTERS_LOAD_PARAMETERS_45_LOAD_NEXT_DESC_MASK 0x01000000
914 #define DSP_REGISTERS_LOAD_PARAMETERS_45_LOAD_NEXT_DESC_ALIGN 0
915 #define DSP_REGISTERS_LOAD_PARAMETERS_45_LOAD_NEXT_DESC_BITS 1
916 #define DSP_REGISTERS_LOAD_PARAMETERS_45_LOAD_NEXT_DESC_SHIFT 24
917
918 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: BUS_TRANSACTION [23:18] */
919 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_TRANSACTION_MASK 0x00fc0000
920 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_TRANSACTION_ALIGN 0
921 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_TRANSACTION_BITS 6
922 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_TRANSACTION_SHIFT 18
923
924 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: BUS_WIDTH [17:16] */
925 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_MASK 0x00030000
926 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_ALIGN 0
927 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_BITS 2
928 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_SHIFT 16
929 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_NONE 0
930 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_CMB 1
931 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_R_INVR 2
932 #define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_Q 3
933
934 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: CR [15:15] */
935 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CR_MASK 0x00008000
936 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CR_ALIGN 0
937 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CR_BITS 1
938 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CR_SHIFT 15
939
940 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: CB [14:14] */
941 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CB_MASK 0x00004000
942 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CB_ALIGN 0
943 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CB_BITS 1
944 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CB_SHIFT 14
945
946 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: RECON_INVR_DATA [13:13] */
947 #define DSP_REGISTERS_LOAD_PARAMETERS_45_RECON_INVR_DATA_MASK 0x00002000
948 #define DSP_REGISTERS_LOAD_PARAMETERS_45_RECON_INVR_DATA_ALIGN 0
949 #define DSP_REGISTERS_LOAD_PARAMETERS_45_RECON_INVR_DATA_BITS 1
950 #define DSP_REGISTERS_LOAD_PARAMETERS_45_RECON_INVR_DATA_SHIFT 13
951
952 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: Q_FLAG [12:12] */
953 #define DSP_REGISTERS_LOAD_PARAMETERS_45_Q_FLAG_MASK 0x00001000
954 #define DSP_REGISTERS_LOAD_PARAMETERS_45_Q_FLAG_ALIGN 0
955 #define DSP_REGISTERS_LOAD_PARAMETERS_45_Q_FLAG_BITS 1
956 #define DSP_REGISTERS_LOAD_PARAMETERS_45_Q_FLAG_SHIFT 12
957
958 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: INVR_FLAG [11:11] */
959 #define DSP_REGISTERS_LOAD_PARAMETERS_45_INVR_FLAG_MASK 0x00000800
960 #define DSP_REGISTERS_LOAD_PARAMETERS_45_INVR_FLAG_ALIGN 0
961 #define DSP_REGISTERS_LOAD_PARAMETERS_45_INVR_FLAG_BITS 1
962 #define DSP_REGISTERS_LOAD_PARAMETERS_45_INVR_FLAG_SHIFT 11
963
964 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: R_FLAG [10:10] */
965 #define DSP_REGISTERS_LOAD_PARAMETERS_45_R_FLAG_MASK 0x00000400
966 #define DSP_REGISTERS_LOAD_PARAMETERS_45_R_FLAG_ALIGN 0
967 #define DSP_REGISTERS_LOAD_PARAMETERS_45_R_FLAG_BITS 1
968 #define DSP_REGISTERS_LOAD_PARAMETERS_45_R_FLAG_SHIFT 10
969
970 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: CMB_FLAG [09:09] */
971 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CMB_FLAG_MASK 0x00000200
972 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CMB_FLAG_ALIGN 0
973 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CMB_FLAG_BITS 1
974 #define DSP_REGISTERS_LOAD_PARAMETERS_45_CMB_FLAG_SHIFT 9
975
976 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: MEM_WA [08:06] */
977 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_WA_MASK 0x000001c0
978 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_WA_ALIGN 0
979 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_WA_BITS 3
980 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_WA_SHIFT 6
981
982 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: MEM_RA_1 [05:03] */
983 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_1_MASK 0x00000038
984 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_1_ALIGN 0
985 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_1_BITS 3
986 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_1_SHIFT 3
987
988 /* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: MEM_RA_0 [02:00] */
989 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_0_MASK 0x00000007
990 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_0_ALIGN 0
991 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_0_BITS 3
992 #define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_0_SHIFT 0
993
994 /***************************************************************************
995 *INTERRUPT - DSP INTERRUPTS.
996 ***************************************************************************/
997 /* DSP_REGISTERS :: INTERRUPT :: reserved0 [31:08] */
998 #define DSP_REGISTERS_INTERRUPT_reserved0_MASK 0xffffff00
999 #define DSP_REGISTERS_INTERRUPT_reserved0_ALIGN 0
1000 #define DSP_REGISTERS_INTERRUPT_reserved0_BITS 24
1001 #define DSP_REGISTERS_INTERRUPT_reserved0_SHIFT 8
1002
1003 /* DSP_REGISTERS :: INTERRUPT :: ERROR_MCROM_ADD [07:07] */
1004 #define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ADD_MASK 0x00000080
1005 #define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ADD_ALIGN 0
1006 #define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ADD_BITS 1
1007 #define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ADD_SHIFT 7
1008
1009 /* DSP_REGISTERS :: INTERRUPT :: ERROR_MCROM_ACK [06:06] */
1010 #define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ACK_MASK 0x00000040
1011 #define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ACK_ALIGN 0
1012 #define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ACK_BITS 1
1013 #define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ACK_SHIFT 6
1014
1015 /* DSP_REGISTERS :: INTERRUPT :: ERROR_CROM_ADD [05:05] */
1016 #define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ADD_MASK 0x00000020
1017 #define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ADD_ALIGN 0
1018 #define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ADD_BITS 1
1019 #define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ADD_SHIFT 5
1020
1021 /* DSP_REGISTERS :: INTERRUPT :: ERROR_CROM_ACK [04:04] */
1022 #define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ACK_MASK 0x00000010
1023 #define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ACK_ALIGN 0
1024 #define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ACK_BITS 1
1025 #define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ACK_SHIFT 4
1026
1027 /* DSP_REGISTERS :: INTERRUPT :: ERROR_BANK_ADD [03:03] */
1028 #define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ADD_MASK 0x00000008
1029 #define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ADD_ALIGN 0
1030 #define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ADD_BITS 1
1031 #define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ADD_SHIFT 3
1032
1033 /* DSP_REGISTERS :: INTERRUPT :: ERROR_BANK_ACK [02:02] */
1034 #define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ACK_MASK 0x00000004
1035 #define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ACK_ALIGN 0
1036 #define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ACK_BITS 1
1037 #define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ACK_SHIFT 2
1038
1039 /* DSP_REGISTERS :: INTERRUPT :: BANK_ERROR [01:01] */
1040 #define DSP_REGISTERS_INTERRUPT_BANK_ERROR_MASK 0x00000002
1041 #define DSP_REGISTERS_INTERRUPT_BANK_ERROR_ALIGN 0
1042 #define DSP_REGISTERS_INTERRUPT_BANK_ERROR_BITS 1
1043 #define DSP_REGISTERS_INTERRUPT_BANK_ERROR_SHIFT 1
1044
1045 /* DSP_REGISTERS :: INTERRUPT :: EXEC [00:00] */
1046 #define DSP_REGISTERS_INTERRUPT_EXEC_MASK 0x00000001
1047 #define DSP_REGISTERS_INTERRUPT_EXEC_ALIGN 0
1048 #define DSP_REGISTERS_INTERRUPT_EXEC_BITS 1
1049 #define DSP_REGISTERS_INTERRUPT_EXEC_SHIFT 0
1050
1051 /***************************************************************************
1052 *MASK_INTERRUPT - DSP MASK INTERRUPTS.
1053 ***************************************************************************/
1054 /* DSP_REGISTERS :: MASK_INTERRUPT :: reserved0 [31:08] */
1055 #define DSP_REGISTERS_MASK_INTERRUPT_reserved0_MASK 0xffffff00
1056 #define DSP_REGISTERS_MASK_INTERRUPT_reserved0_ALIGN 0
1057 #define DSP_REGISTERS_MASK_INTERRUPT_reserved0_BITS 24
1058 #define DSP_REGISTERS_MASK_INTERRUPT_reserved0_SHIFT 8
1059
1060 /* DSP_REGISTERS :: MASK_INTERRUPT :: MASK [07:00] */
1061 #define DSP_REGISTERS_MASK_INTERRUPT_MASK_MASK 0x000000ff
1062 #define DSP_REGISTERS_MASK_INTERRUPT_MASK_ALIGN 0
1063 #define DSP_REGISTERS_MASK_INTERRUPT_MASK_BITS 8
1064 #define DSP_REGISTERS_MASK_INTERRUPT_MASK_SHIFT 0
1065
1066 /***************************************************************************
1067 *LOAD_PARAMETERS_0 - LPAR0 - Loads DSP-Controller with Group 0 Parameters.
1068 ***************************************************************************/
1069 /* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: reserved0 [31:14] */
1070 #define DSP_REGISTERS_LOAD_PARAMETERS_0_reserved0_MASK 0xffffc000
1071 #define DSP_REGISTERS_LOAD_PARAMETERS_0_reserved0_ALIGN 0
1072 #define DSP_REGISTERS_LOAD_PARAMETERS_0_reserved0_BITS 18
1073 #define DSP_REGISTERS_LOAD_PARAMETERS_0_reserved0_SHIFT 14
1074
1075 /* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: CHOOSE_CLIP_PAIR [13:12] */
1076 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_MASK 0x00003000
1077 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_ALIGN 0
1078 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_BITS 2
1079 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_SHIFT 12
1080 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_CLIP_PAIR_0 0
1081 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_CLIP_PAIR_1 1
1082 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_CLIP_PAIR_2 2
1083 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_CLIP_PAIR_3 3
1084
1085 /* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: CLIP [11:11] */
1086 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_MASK 0x00000800
1087 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_ALIGN 0
1088 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_BITS 1
1089 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_SHIFT 11
1090 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_PIXEL_CLIP 0
1091 #define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_CLIP 1
1092
1093 /* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: MEM_WA [10:08] */
1094 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_WA_MASK 0x00000700
1095 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_WA_ALIGN 0
1096 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_WA_BITS 3
1097 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_WA_SHIFT 8
1098
1099 /* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: INC_MEM_RA [07:06] */
1100 #define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_MASK 0x000000c0
1101 #define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_ALIGN 0
1102 #define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_BITS 2
1103 #define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_SHIFT 6
1104 #define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_NO_INC 0
1105 #define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_ONE_INC 1
1106 #define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_TWO_INC 2
1107 #define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_FIELD_INC 3
1108
1109 /* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: MEM_RA_1 [05:03] */
1110 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_1_MASK 0x00000038
1111 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_1_ALIGN 0
1112 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_1_BITS 3
1113 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_1_SHIFT 3
1114
1115 /* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: MEM_RA_0 [02:00] */
1116 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_0_MASK 0x00000007
1117 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_0_ALIGN 0
1118 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_0_BITS 3
1119 #define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_0_SHIFT 0
1120
1121 /***************************************************************************
1122 *LOAD_PARAMETERS_1 - LPAR1 - Loads DSP-Controller with Group 1 Parameters.
1123 ***************************************************************************/
1124 /* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: reserved0 [31:12] */
1125 #define DSP_REGISTERS_LOAD_PARAMETERS_1_reserved0_MASK 0xfffff000
1126 #define DSP_REGISTERS_LOAD_PARAMETERS_1_reserved0_ALIGN 0
1127 #define DSP_REGISTERS_LOAD_PARAMETERS_1_reserved0_BITS 20
1128 #define DSP_REGISTERS_LOAD_PARAMETERS_1_reserved0_SHIFT 12
1129
1130 /* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: REGA_MUX [11:11] */
1131 #define DSP_REGISTERS_LOAD_PARAMETERS_1_REGA_MUX_MASK 0x00000800
1132 #define DSP_REGISTERS_LOAD_PARAMETERS_1_REGA_MUX_ALIGN 0
1133 #define DSP_REGISTERS_LOAD_PARAMETERS_1_REGA_MUX_BITS 1
1134 #define DSP_REGISTERS_LOAD_PARAMETERS_1_REGA_MUX_SHIFT 11
1135
1136 /* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: INC_MEM_WA [10:10] */
1137 #define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_MASK 0x00000400
1138 #define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_ALIGN 0
1139 #define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_BITS 1
1140 #define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_SHIFT 10
1141 #define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_ONE_INC 0
1142 #define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_FIELD_INC 1
1143
1144 /* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: FIELD [09:09] */
1145 #define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_MASK 0x00000200
1146 #define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_ALIGN 0
1147 #define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_BITS 1
1148 #define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_SHIFT 9
1149 #define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_DIS 0
1150 #define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_FIELD_MODE 1
1151
1152 /* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: CROM_INC [08:08] */
1153 #define DSP_REGISTERS_LOAD_PARAMETERS_1_CROM_INC_MASK 0x00000100
1154 #define DSP_REGISTERS_LOAD_PARAMETERS_1_CROM_INC_ALIGN 0
1155 #define DSP_REGISTERS_LOAD_PARAMETERS_1_CROM_INC_BITS 1
1156 #define DSP_REGISTERS_LOAD_PARAMETERS_1_CROM_INC_SHIFT 8
1157
1158 /* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: IQUANT [07:07] */
1159 #define DSP_REGISTERS_LOAD_PARAMETERS_1_IQUANT_MASK 0x00000080
1160 #define DSP_REGISTERS_LOAD_PARAMETERS_1_IQUANT_ALIGN 0
1161 #define DSP_REGISTERS_LOAD_PARAMETERS_1_IQUANT_BITS 1
1162 #define DSP_REGISTERS_LOAD_PARAMETERS_1_IQUANT_SHIFT 7
1163
1164 /* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: ROUND_REG_LEFT_SCALE [06:03] */
1165 #define DSP_REGISTERS_LOAD_PARAMETERS_1_ROUND_REG_LEFT_SCALE_MASK 0x00000078
1166 #define DSP_REGISTERS_LOAD_PARAMETERS_1_ROUND_REG_LEFT_SCALE_ALIGN 0
1167 #define DSP_REGISTERS_LOAD_PARAMETERS_1_ROUND_REG_LEFT_SCALE_BITS 4
1168 #define DSP_REGISTERS_LOAD_PARAMETERS_1_ROUND_REG_LEFT_SCALE_SHIFT 3
1169
1170 /* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: CHOOSE_ROUND_QUARTET [02:00] */
1171 #define DSP_REGISTERS_LOAD_PARAMETERS_1_CHOOSE_ROUND_QUARTET_MASK 0x00000007
1172 #define DSP_REGISTERS_LOAD_PARAMETERS_1_CHOOSE_ROUND_QUARTET_ALIGN 0
1173 #define DSP_REGISTERS_LOAD_PARAMETERS_1_CHOOSE_ROUND_QUARTET_BITS 3
1174 #define DSP_REGISTERS_LOAD_PARAMETERS_1_CHOOSE_ROUND_QUARTET_SHIFT 0
1175
1176 /***************************************************************************
1177 *LOAD_PARAMETERS_2 - LPAR2 - Loads DSP-Controller with Group 2 Parameters.
1178 ***************************************************************************/
1179 /* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: reserved0 [31:12] */
1180 #define DSP_REGISTERS_LOAD_PARAMETERS_2_reserved0_MASK 0xfffff000
1181 #define DSP_REGISTERS_LOAD_PARAMETERS_2_reserved0_ALIGN 0
1182 #define DSP_REGISTERS_LOAD_PARAMETERS_2_reserved0_BITS 20
1183 #define DSP_REGISTERS_LOAD_PARAMETERS_2_reserved0_SHIFT 12
1184
1185 /* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: REGISTER_TYPE [11:10] */
1186 #define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_TYPE_MASK 0x00000c00
1187 #define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_TYPE_ALIGN 0
1188 #define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_TYPE_BITS 2
1189 #define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_TYPE_SHIFT 10
1190
1191 /* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: REGISTER_GROUP [09:06] */
1192 #define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_GROUP_MASK 0x000003c0
1193 #define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_GROUP_ALIGN 0
1194 #define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_GROUP_BITS 4
1195 #define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_GROUP_SHIFT 6
1196
1197 /* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: LOAD [05:04] */
1198 #define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_MASK 0x00000030
1199 #define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_ALIGN 0
1200 #define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_BITS 2
1201 #define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_SHIFT 4
1202 #define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_LOAD_DIS 0
1203 #define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_LOAD_LUMA_CHROMA_SCALER 1
1204 #define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_LOAD_CLIP 2
1205 #define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_LOAD_ROUND_COEFF 3
1206
1207 /* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: CBP_CONT [03:02] */
1208 #define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_MASK 0x0000000c
1209 #define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_ALIGN 0
1210 #define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_BITS 2
1211 #define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_SHIFT 2
1212 #define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_REGULAR_CBP 0
1213 #define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_NO_DC_CBP 1
1214 #define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_NO_FIRST_LINE_COL_CBP 2
1215 #define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_NO_CBP 3
1216
1217 /* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: MPEG4 [01:01] */
1218 #define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG4_MASK 0x00000002
1219 #define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG4_ALIGN 0
1220 #define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG4_BITS 1
1221 #define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG4_SHIFT 1
1222
1223 /* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: MPEG1 [00:00] */
1224 #define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG1_MASK 0x00000001
1225 #define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG1_ALIGN 0
1226 #define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG1_BITS 1
1227 #define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG1_SHIFT 0
1228
1229 /***************************************************************************
1230 *LOAD_PARAMETERS_3 - LPAR3 - Loads DSP-Controller with Group 3 Parameters.
1231 ***************************************************************************/
1232 /* DSP_REGISTERS :: LOAD_PARAMETERS_3 :: reserved0 [31:07] */
1233 #define DSP_REGISTERS_LOAD_PARAMETERS_3_reserved0_MASK 0xffffff80
1234 #define DSP_REGISTERS_LOAD_PARAMETERS_3_reserved0_ALIGN 0
1235 #define DSP_REGISTERS_LOAD_PARAMETERS_3_reserved0_BITS 25
1236 #define DSP_REGISTERS_LOAD_PARAMETERS_3_reserved0_SHIFT 7
1237
1238 /* DSP_REGISTERS :: LOAD_PARAMETERS_3 :: MEM_WA [06:01] */
1239 #define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_WA_MASK 0x0000007e
1240 #define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_WA_ALIGN 0
1241 #define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_WA_BITS 6
1242 #define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_WA_SHIFT 1
1243
1244 /* DSP_REGISTERS :: LOAD_PARAMETERS_3 :: MEM_RA_SEL [00:00] */
1245 #define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_RA_SEL_MASK 0x00000001
1246 #define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_RA_SEL_ALIGN 0
1247 #define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_RA_SEL_BITS 1
1248 #define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_RA_SEL_SHIFT 0
1249
1250 /***************************************************************************
1251 *LOAD_PARAMETERS_4 - LPAR4 - Loads DSP-Controller with Group 4 Parameters.
1252 ***************************************************************************/
1253 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: reserved0 [31:25] */
1254 #define DSP_REGISTERS_LOAD_PARAMETERS_4_reserved0_MASK 0xfe000000
1255 #define DSP_REGISTERS_LOAD_PARAMETERS_4_reserved0_ALIGN 0
1256 #define DSP_REGISTERS_LOAD_PARAMETERS_4_reserved0_BITS 7
1257 #define DSP_REGISTERS_LOAD_PARAMETERS_4_reserved0_SHIFT 25
1258
1259 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: LOAD_NEXT_DESC [24:24] */
1260 #define DSP_REGISTERS_LOAD_PARAMETERS_4_LOAD_NEXT_DESC_MASK 0x01000000
1261 #define DSP_REGISTERS_LOAD_PARAMETERS_4_LOAD_NEXT_DESC_ALIGN 0
1262 #define DSP_REGISTERS_LOAD_PARAMETERS_4_LOAD_NEXT_DESC_BITS 1
1263 #define DSP_REGISTERS_LOAD_PARAMETERS_4_LOAD_NEXT_DESC_SHIFT 24
1264
1265 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: BUS_TRANSACTION [23:18] */
1266 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_TRANSACTION_MASK 0x00fc0000
1267 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_TRANSACTION_ALIGN 0
1268 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_TRANSACTION_BITS 6
1269 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_TRANSACTION_SHIFT 18
1270
1271 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: BUS_WIDTH [17:16] */
1272 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_MASK 0x00030000
1273 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_ALIGN 0
1274 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_BITS 2
1275 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_SHIFT 16
1276 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_NONE 0
1277 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_CMB 1
1278 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_R_INVR 2
1279 #define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_Q 3
1280
1281 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: CR [15:15] */
1282 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CR_MASK 0x00008000
1283 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CR_ALIGN 0
1284 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CR_BITS 1
1285 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CR_SHIFT 15
1286
1287 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: CB [14:14] */
1288 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CB_MASK 0x00004000
1289 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CB_ALIGN 0
1290 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CB_BITS 1
1291 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CB_SHIFT 14
1292
1293 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: RECON_INVR_DATA [13:13] */
1294 #define DSP_REGISTERS_LOAD_PARAMETERS_4_RECON_INVR_DATA_MASK 0x00002000
1295 #define DSP_REGISTERS_LOAD_PARAMETERS_4_RECON_INVR_DATA_ALIGN 0
1296 #define DSP_REGISTERS_LOAD_PARAMETERS_4_RECON_INVR_DATA_BITS 1
1297 #define DSP_REGISTERS_LOAD_PARAMETERS_4_RECON_INVR_DATA_SHIFT 13
1298
1299 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: Q_FLAG [12:12] */
1300 #define DSP_REGISTERS_LOAD_PARAMETERS_4_Q_FLAG_MASK 0x00001000
1301 #define DSP_REGISTERS_LOAD_PARAMETERS_4_Q_FLAG_ALIGN 0
1302 #define DSP_REGISTERS_LOAD_PARAMETERS_4_Q_FLAG_BITS 1
1303 #define DSP_REGISTERS_LOAD_PARAMETERS_4_Q_FLAG_SHIFT 12
1304
1305 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: INVR_FLAG [11:11] */
1306 #define DSP_REGISTERS_LOAD_PARAMETERS_4_INVR_FLAG_MASK 0x00000800
1307 #define DSP_REGISTERS_LOAD_PARAMETERS_4_INVR_FLAG_ALIGN 0
1308 #define DSP_REGISTERS_LOAD_PARAMETERS_4_INVR_FLAG_BITS 1
1309 #define DSP_REGISTERS_LOAD_PARAMETERS_4_INVR_FLAG_SHIFT 11
1310
1311 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: R_FLAG [10:10] */
1312 #define DSP_REGISTERS_LOAD_PARAMETERS_4_R_FLAG_MASK 0x00000400
1313 #define DSP_REGISTERS_LOAD_PARAMETERS_4_R_FLAG_ALIGN 0
1314 #define DSP_REGISTERS_LOAD_PARAMETERS_4_R_FLAG_BITS 1
1315 #define DSP_REGISTERS_LOAD_PARAMETERS_4_R_FLAG_SHIFT 10
1316
1317 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: CMB_FLAG [09:09] */
1318 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CMB_FLAG_MASK 0x00000200
1319 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CMB_FLAG_ALIGN 0
1320 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CMB_FLAG_BITS 1
1321 #define DSP_REGISTERS_LOAD_PARAMETERS_4_CMB_FLAG_SHIFT 9
1322
1323 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: MEM_WA [08:06] */
1324 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_WA_MASK 0x000001c0
1325 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_WA_ALIGN 0
1326 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_WA_BITS 3
1327 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_WA_SHIFT 6
1328
1329 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: MEM_RA_1 [05:03] */
1330 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_1_MASK 0x00000038
1331 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_1_ALIGN 0
1332 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_1_BITS 3
1333 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_1_SHIFT 3
1334
1335 /* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: MEM_RA_0 [02:00] */
1336 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_0_MASK 0x00000007
1337 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_0_ALIGN 0
1338 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_0_BITS 3
1339 #define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_0_SHIFT 0
1340
1341 /***************************************************************************
1342 *START_UNIT_PC - START DSP Operation
1343 ***************************************************************************/
1344 /* DSP_REGISTERS :: START_UNIT_PC :: reserved0 [31:09] */
1345 #define DSP_REGISTERS_START_UNIT_PC_reserved0_MASK 0xfffffe00
1346 #define DSP_REGISTERS_START_UNIT_PC_reserved0_ALIGN 0
1347 #define DSP_REGISTERS_START_UNIT_PC_reserved0_BITS 23
1348 #define DSP_REGISTERS_START_UNIT_PC_reserved0_SHIFT 9
1349
1350 /* DSP_REGISTERS :: START_UNIT_PC :: PROGRAM_COUNTER [08:00] */
1351 #define DSP_REGISTERS_START_UNIT_PC_PROGRAM_COUNTER_MASK 0x000001ff
1352 #define DSP_REGISTERS_START_UNIT_PC_PROGRAM_COUNTER_ALIGN 0
1353 #define DSP_REGISTERS_START_UNIT_PC_PROGRAM_COUNTER_BITS 9
1354 #define DSP_REGISTERS_START_UNIT_PC_PROGRAM_COUNTER_SHIFT 0
1355
1356 #endif /* #ifndef BCM7043_A0_DSP_REGISTERS_H__ */
1357
1358 /* End of File */
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