e8ed0e49976f2753e451220d09b6fcc03e3d9e6d
[rpi-open-firmware.git] / bcm2708_chip / jpeg_top.h
1 // This file was generated by the create_regs script
2 #define JP_BASE 0x7e005000
3 #define JP_APB_ID 0x4a504547
4 #define JP_CTRL HW_REGISTER_RW( 0x7e005000 )
5 #define JP_ICST HW_REGISTER_RW( 0x7e005004 )
6 #define JP_MCTRL HW_REGISTER_RW( 0x7e005008 )
7 #define JP_DCCTRL HW_REGISTER_RW( 0x7e00500c )
8 #define JP_CBA HW_REGISTER_RW( 0x7e005010 )
9 #define JP_NCB HW_REGISTER_RW( 0x7e005014 )
10 #define JP_SDA HW_REGISTER_RW( 0x7e005018 )
11 #define JP_NSB HW_REGISTER_RW( 0x7e00501c )
12 #define JP_SBO HW_REGISTER_RW( 0x7e005020 )
13 #define JP_MOP HW_REGISTER_RW( 0x7e005024 )
14 #define JP_HADDR HW_REGISTER_RW( 0x7e005028 )
15 #define JP_HWDATA HW_REGISTER_RW( 0x7e00502c )
16 #define JP_MADDR HW_REGISTER_RW( 0x7e005030 )
17 #define JP_MWDATA HW_REGISTER_RW( 0x7e005034 )
18 #define JP_OADDR HW_REGISTER_RW( 0x7e005038 )
19 #define JP_OWDATA HW_REGISTER_RW( 0x7e00503c )
20 #define JP_QADDR HW_REGISTER_RW( 0x7e005040 )
21 #define JP_QWDATA HW_REGISTER_RW( 0x7e005044 )
22 #define JP_QCTRL HW_REGISTER_RW( 0x7e005048 )
23 #define JP_C0BA HW_REGISTER_RW( 0x7e00504c )
24 #define JP_C1BA HW_REGISTER_RW( 0x7e005050 )
25 #define JP_C2BA HW_REGISTER_RW( 0x7e005054 )
26 #define JP_C0S HW_REGISTER_RW( 0x7e005058 )
27 #define JP_C1S HW_REGISTER_RW( 0x7e00505c )
28 #define JP_C2S HW_REGISTER_RW( 0x7e005060 )
29 #define JP_C0W HW_REGISTER_RW( 0x7e005064 )
30 #define JP_C1W HW_REGISTER_RW( 0x7e005068 )
31 #define JP_C2W HW_REGISTER_RW( 0x7e00506c )
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