Update to new mnemonics (thanks Julian)
[rpi-open-firmware.git] / bcm2708_chip / l2_cache_ctrl.h
1 // This file was generated by the create_regs script
2 #define L2_BASE 0x7ee01000
3 #define L2_APB_ID 0x4c324343
4 #define L2_CONT_OFF HW_REGISTER_RW( 0x7ee01000 )
5 #define L2_CONT_OFF_MASK 0x00ff0c3f
6 #define L2_CONT_OFF_WIDTH 24
7 #define L2_CONT_OFF_RESET 0000000000
8 #define L2_CONT_OFF_l2_flush_core_limit_BITS 23:20
9 #define L2_CONT_OFF_l2_flush_core_limit_SET 0x00f00000
10 #define L2_CONT_OFF_l2_flush_core_limit_CLR 0xff0fffff
11 #define L2_CONT_OFF_l2_flush_core_limit_MSB 23
12 #define L2_CONT_OFF_l2_flush_core_limit_LSB 20
13 #define L2_CONT_OFF_l2_flush_flush_limit_BITS 19:16
14 #define L2_CONT_OFF_l2_flush_flush_limit_SET 0x000f0000
15 #define L2_CONT_OFF_l2_flush_flush_limit_CLR 0xfff0ffff
16 #define L2_CONT_OFF_l2_flush_flush_limit_MSB 19
17 #define L2_CONT_OFF_l2_flush_flush_limit_LSB 16
18 #define L2_CONT_OFF_l2_standby_BITS 11:10
19 #define L2_CONT_OFF_l2_standby_SET 0x00000c00
20 #define L2_CONT_OFF_l2_standby_CLR 0xfffff3ff
21 #define L2_CONT_OFF_l2_standby_MSB 11
22 #define L2_CONT_OFF_l2_standby_LSB 10
23 #define L2_CONT_OFF_l2_enable_stats_BITS 5:5
24 #define L2_CONT_OFF_l2_enable_stats_SET 0x00000020
25 #define L2_CONT_OFF_l2_enable_stats_CLR 0xffffffdf
26 #define L2_CONT_OFF_l2_enable_stats_MSB 5
27 #define L2_CONT_OFF_l2_enable_stats_LSB 5
28 #define L2_CONT_OFF_l2_flush_mode_BITS 4:3
29 #define L2_CONT_OFF_l2_flush_mode_SET 0x00000018
30 #define L2_CONT_OFF_l2_flush_mode_CLR 0xffffffe7
31 #define L2_CONT_OFF_l2_flush_mode_MSB 4
32 #define L2_CONT_OFF_l2_flush_mode_LSB 3
33 #define L2_CONT_OFF_l2_flush_BITS 2:2
34 #define L2_CONT_OFF_l2_flush_SET 0x00000004
35 #define L2_CONT_OFF_l2_flush_CLR 0xfffffffb
36 #define L2_CONT_OFF_l2_flush_MSB 2
37 #define L2_CONT_OFF_l2_flush_LSB 2
38 #define L2_CONT_OFF_l2_no_wr_allocate_BITS 1:1
39 #define L2_CONT_OFF_l2_no_wr_allocate_SET 0x00000002
40 #define L2_CONT_OFF_l2_no_wr_allocate_CLR 0xfffffffd
41 #define L2_CONT_OFF_l2_no_wr_allocate_MSB 1
42 #define L2_CONT_OFF_l2_no_wr_allocate_LSB 1
43 #define L2_CONT_OFF_l2_disable_BITS 0:0
44 #define L2_CONT_OFF_l2_disable_SET 0x00000001
45 #define L2_CONT_OFF_l2_disable_CLR 0xfffffffe
46 #define L2_CONT_OFF_l2_disable_MSB 0
47 #define L2_CONT_OFF_l2_disable_LSB 0
48 #define L2_FLUSH_STA HW_REGISTER_RW( 0x7ee01004 )
49 #define L2_FLUSH_STA_MASK 0x0fffffe0
50 #define L2_FLUSH_STA_WIDTH 28
51 #define L2_FLUSH_STA_RESET 0000000000
52 #define L2_FLUSH_END HW_REGISTER_RW( 0x7ee01008 )
53 #define L2_FLUSH_END_MASK 0x0fffffe0
54 #define L2_FLUSH_END_WIDTH 28
55 #define L2_FLUSH_END_RESET 0x0fffffe0
56 #define L2_L2_ALIAS_EXCEPTION HW_REGISTER_RW( 0x7ee01080 )
57 #define L2_L2_ALIAS_EXCEPTION_RESET 0000000000
58 #define L2_L2_ALIAS_EXCEPTION_ID HW_REGISTER_RO( 0x7ee01084 )
59 #define L2_L2_ALIAS_EXCEPTION_ID_RESET 0000000000
60 #define L2_L2_ALIAS_EXCEPTION_ADDR HW_REGISTER_RO( 0x7ee01088 )
61 #define L2_L2_ALIAS_EXCEPTION_ADDR_RESET 0000000000
62 #define L2_RD_HITS HW_REGISTER_RW( 0x7ee01100 )
63 #define L2_RD_HITS_MASK 0xffffffff
64 #define L2_RD_HITS_WIDTH 32
65 #define L2_RD_MISSES HW_REGISTER_RO( 0x7ee01104 )
66 #define L2_RD_MISSES_MASK 0xffffffff
67 #define L2_RD_MISSES_WIDTH 32
68 #define L2_WR_HITS HW_REGISTER_RO( 0x7ee01108 )
69 #define L2_WR_HITS_MASK 0xffffffff
70 #define L2_WR_HITS_WIDTH 32
71 #define L2_WR_MISSES HW_REGISTER_RO( 0x7ee0110c )
72 #define L2_WR_MISSES_MASK 0xffffffff
73 #define L2_WR_MISSES_WIDTH 32
74 #define L2_WR_BACKS HW_REGISTER_RO( 0x7ee01110 )
75 #define L2_WR_BACKS_MASK 0xffffffff
76 #define L2_WR_BACKS_WIDTH 32
77 #define L2_IN_FLIGHT HW_REGISTER_RO( 0x7ee01114 )
78 #define L2_IN_FLIGHT_MASK 0x0000000f
79 #define L2_IN_FLIGHT_WIDTH 4
80 #define L2_STALLS HW_REGISTER_RO( 0x7ee0111c )
81 #define L2_STALLS_MASK 0xffffffff
82 #define L2_STALLS_WIDTH 32
83 #define L2_TAG_STALLS HW_REGISTER_RO( 0x7ee01120 )
84 #define L2_TAG_STALLS_MASK 0xffffffff
85 #define L2_TAG_STALLS_WIDTH 32
86 #define L2_SD_STALLS HW_REGISTER_RO( 0x7ee01124 )
87 #define L2_SD_STALLS_MASK 0xffffffff
88 #define L2_SD_STALLS_WIDTH 32
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