Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / mphi.h
1 // This file was generated by the create_regs script
2 #define MPHI_BASE 0x7e006000
3 #define MPHI_APB_ID 0x6d706869
4 #define MPHI_C0INDDA HW_REGISTER_RW( 0x7e006000 )
5 #define MPHI_C0INDDA_MASK 0xffffffff
6 #define MPHI_C0INDDA_WIDTH 32
7 #define MPHI_C0INDDA_START_BITS 31:0
8 #define MPHI_C0INDDA_START_SET 0xffffffff
9 #define MPHI_C0INDDA_START_CLR 0x00000000
10 #define MPHI_C0INDDA_START_MSB 31
11 #define MPHI_C0INDDA_START_LSB 0
12 #define MPHI_C0INDDA_START_RESET 0x0
13 #define MPHI_C0INDDB HW_REGISTER_RW( 0x7e006004 )
14 #define MPHI_C0INDDB_MASK 0xffffffff
15 #define MPHI_C0INDDB_WIDTH 32
16 #define MPHI_C0INDDB_MORUN_BITS 31:31
17 #define MPHI_C0INDDB_MORUN_SET 0x80000000
18 #define MPHI_C0INDDB_MORUN_CLR 0x7fffffff
19 #define MPHI_C0INDDB_MORUN_MSB 31
20 #define MPHI_C0INDDB_MORUN_LSB 31
21 #define MPHI_C0INDDB_MORUN_RESET 0x0
22 #define MPHI_C0INDDB_MENDINT_BITS 30:30
23 #define MPHI_C0INDDB_MENDINT_SET 0x40000000
24 #define MPHI_C0INDDB_MENDINT_CLR 0xbfffffff
25 #define MPHI_C0INDDB_MENDINT_MSB 30
26 #define MPHI_C0INDDB_MENDINT_LSB 30
27 #define MPHI_C0INDDB_MENDINT_RESET 0x0
28 #define MPHI_C0INDDB_TENDINT_BITS 29:29
29 #define MPHI_C0INDDB_TENDINT_SET 0x20000000
30 #define MPHI_C0INDDB_TENDINT_CLR 0xdfffffff
31 #define MPHI_C0INDDB_TENDINT_MSB 29
32 #define MPHI_C0INDDB_TENDINT_LSB 29
33 #define MPHI_C0INDDB_TENDINT_RESET 0x0
34 #define MPHI_C0INDDB_MTERM_BITS 28:28
35 #define MPHI_C0INDDB_MTERM_SET 0x10000000
36 #define MPHI_C0INDDB_MTERM_CLR 0xefffffff
37 #define MPHI_C0INDDB_MTERM_MSB 28
38 #define MPHI_C0INDDB_MTERM_LSB 28
39 #define MPHI_C0INDDB_MTERM_RESET 0x0
40 #define MPHI_C0INDDB_HANDLE_BITS 27:20
41 #define MPHI_C0INDDB_HANDLE_SET 0x0ff00000
42 #define MPHI_C0INDDB_HANDLE_CLR 0xf00fffff
43 #define MPHI_C0INDDB_HANDLE_MSB 27
44 #define MPHI_C0INDDB_HANDLE_LSB 20
45 #define MPHI_C0INDDB_HANDLE_RESET 0x0
46 #define MPHI_C0INDDB_LENGTH_BITS 19:0
47 #define MPHI_C0INDDB_LENGTH_SET 0x000fffff
48 #define MPHI_C0INDDB_LENGTH_CLR 0xfff00000
49 #define MPHI_C0INDDB_LENGTH_MSB 19
50 #define MPHI_C0INDDB_LENGTH_LSB 0
51 #define MPHI_C0INDDB_LENGTH_RESET 0x0
52 #define MPHI_C1INDDA HW_REGISTER_RW( 0x7e006008 )
53 #define MPHI_C1INDDA_MASK 0xffffffff
54 #define MPHI_C1INDDA_WIDTH 32
55 #define MPHI_C1INDDA_START_BITS 31:0
56 #define MPHI_C1INDDA_START_SET 0xffffffff
57 #define MPHI_C1INDDA_START_CLR 0x00000000
58 #define MPHI_C1INDDA_START_MSB 31
59 #define MPHI_C1INDDA_START_LSB 0
60 #define MPHI_C1INDDA_START_RESET 0x0
61 #define MPHI_C1INDDB HW_REGISTER_RW( 0x7e00600c )
62 #define MPHI_C1INDDB_MASK 0xffffffff
63 #define MPHI_C1INDDB_WIDTH 32
64 #define MPHI_C1INDDB_MORUN_BITS 31:31
65 #define MPHI_C1INDDB_MORUN_SET 0x80000000
66 #define MPHI_C1INDDB_MORUN_CLR 0x7fffffff
67 #define MPHI_C1INDDB_MORUN_MSB 31
68 #define MPHI_C1INDDB_MORUN_LSB 31
69 #define MPHI_C1INDDB_MORUN_RESET 0x0
70 #define MPHI_C1INDDB_MENDINT_BITS 30:30
71 #define MPHI_C1INDDB_MENDINT_SET 0x40000000
72 #define MPHI_C1INDDB_MENDINT_CLR 0xbfffffff
73 #define MPHI_C1INDDB_MENDINT_MSB 30
74 #define MPHI_C1INDDB_MENDINT_LSB 30
75 #define MPHI_C1INDDB_MENDINT_RESET 0x0
76 #define MPHI_C1INDDB_TENDINT_BITS 29:29
77 #define MPHI_C1INDDB_TENDINT_SET 0x20000000
78 #define MPHI_C1INDDB_TENDINT_CLR 0xdfffffff
79 #define MPHI_C1INDDB_TENDINT_MSB 29
80 #define MPHI_C1INDDB_TENDINT_LSB 29
81 #define MPHI_C1INDDB_TENDINT_RESET 0x0
82 #define MPHI_C1INDDB_MTERM_BITS 28:28
83 #define MPHI_C1INDDB_MTERM_SET 0x10000000
84 #define MPHI_C1INDDB_MTERM_CLR 0xefffffff
85 #define MPHI_C1INDDB_MTERM_MSB 28
86 #define MPHI_C1INDDB_MTERM_LSB 28
87 #define MPHI_C1INDDB_MTERM_RESET 0x0
88 #define MPHI_C1INDDB_HANDLE_BITS 27:20
89 #define MPHI_C1INDDB_HANDLE_SET 0x0ff00000
90 #define MPHI_C1INDDB_HANDLE_CLR 0xf00fffff
91 #define MPHI_C1INDDB_HANDLE_MSB 27
92 #define MPHI_C1INDDB_HANDLE_LSB 20
93 #define MPHI_C1INDDB_HANDLE_RESET 0x0
94 #define MPHI_C1INDDB_LENGTH_BITS 19:0
95 #define MPHI_C1INDDB_LENGTH_SET 0x000fffff
96 #define MPHI_C1INDDB_LENGTH_CLR 0xfff00000
97 #define MPHI_C1INDDB_LENGTH_MSB 19
98 #define MPHI_C1INDDB_LENGTH_LSB 0
99 #define MPHI_C1INDDB_LENGTH_RESET 0x0
100 #define MPHI_C0INDS HW_REGISTER_RW( 0x7e006010 )
101 #define MPHI_C0INDS_MASK 0xdfffffff
102 #define MPHI_C0INDS_WIDTH 32
103 #define MPHI_C0INDS_DISCARD_BITS 31:31
104 #define MPHI_C0INDS_DISCARD_SET 0x80000000
105 #define MPHI_C0INDS_DISCARD_CLR 0x7fffffff
106 #define MPHI_C0INDS_DISCARD_MSB 31
107 #define MPHI_C0INDS_DISCARD_LSB 31
108 #define MPHI_C0INDS_DISCARD_RESET 0x0
109 #define MPHI_C0INDS_VALID_BITS 30:30
110 #define MPHI_C0INDS_VALID_SET 0x40000000
111 #define MPHI_C0INDS_VALID_CLR 0xbfffffff
112 #define MPHI_C0INDS_VALID_MSB 30
113 #define MPHI_C0INDS_VALID_LSB 30
114 #define MPHI_C0INDS_VALID_RESET 0x0
115 #define MPHI_C0INDS_HANDLE_BITS 28:21
116 #define MPHI_C0INDS_HANDLE_SET 0x1fe00000
117 #define MPHI_C0INDS_HANDLE_CLR 0xe01fffff
118 #define MPHI_C0INDS_HANDLE_MSB 28
119 #define MPHI_C0INDS_HANDLE_LSB 21
120 #define MPHI_C0INDS_HANDLE_RESET 0x0
121 #define MPHI_C0INDS_WORDS_BITS 20:0
122 #define MPHI_C0INDS_WORDS_SET 0x001fffff
123 #define MPHI_C0INDS_WORDS_CLR 0xffe00000
124 #define MPHI_C0INDS_WORDS_MSB 20
125 #define MPHI_C0INDS_WORDS_LSB 0
126 #define MPHI_C0INDS_WORDS_RESET 0x0
127 #define MPHI_C1INDS HW_REGISTER_RW( 0x7e006014 )
128 #define MPHI_C1INDS_MASK 0xdfffffff
129 #define MPHI_C1INDS_WIDTH 32
130 #define MPHI_C1INDS_DISCARD_BITS 31:31
131 #define MPHI_C1INDS_DISCARD_SET 0x80000000
132 #define MPHI_C1INDS_DISCARD_CLR 0x7fffffff
133 #define MPHI_C1INDS_DISCARD_MSB 31
134 #define MPHI_C1INDS_DISCARD_LSB 31
135 #define MPHI_C1INDS_DISCARD_RESET 0x0
136 #define MPHI_C1INDS_VALID_BITS 30:30
137 #define MPHI_C1INDS_VALID_SET 0x40000000
138 #define MPHI_C1INDS_VALID_CLR 0xbfffffff
139 #define MPHI_C1INDS_VALID_MSB 30
140 #define MPHI_C1INDS_VALID_LSB 30
141 #define MPHI_C1INDS_VALID_RESET 0x0
142 #define MPHI_C1INDS_HANDLE_BITS 28:21
143 #define MPHI_C1INDS_HANDLE_SET 0x1fe00000
144 #define MPHI_C1INDS_HANDLE_CLR 0xe01fffff
145 #define MPHI_C1INDS_HANDLE_MSB 28
146 #define MPHI_C1INDS_HANDLE_LSB 21
147 #define MPHI_C1INDS_HANDLE_RESET 0x0
148 #define MPHI_C1INDS_WORDS_BITS 20:0
149 #define MPHI_C1INDS_WORDS_SET 0x001fffff
150 #define MPHI_C1INDS_WORDS_CLR 0xffe00000
151 #define MPHI_C1INDS_WORDS_MSB 20
152 #define MPHI_C1INDS_WORDS_LSB 0
153 #define MPHI_C1INDS_WORDS_RESET 0x0
154 #define MPHI_C0INDCF HW_REGISTER_RW( 0x7e006018 )
155 #define MPHI_C0INDCF_MASK 0xffffffff
156 #define MPHI_C0INDCF_WIDTH 32
157 #define MPHI_C0INDCF_EMPTY_BITS 31:31
158 #define MPHI_C0INDCF_EMPTY_SET 0x80000000
159 #define MPHI_C0INDCF_EMPTY_CLR 0x7fffffff
160 #define MPHI_C0INDCF_EMPTY_MSB 31
161 #define MPHI_C0INDCF_EMPTY_LSB 31
162 #define MPHI_C0INDCF_EMPTY_RESET 0x0
163 #define MPHI_C0INDCF_LENERR_BITS 30:30
164 #define MPHI_C0INDCF_LENERR_SET 0x40000000
165 #define MPHI_C0INDCF_LENERR_CLR 0xbfffffff
166 #define MPHI_C0INDCF_LENERR_MSB 30
167 #define MPHI_C0INDCF_LENERR_LSB 30
168 #define MPHI_C0INDCF_LENERR_RESET 0x0
169 #define MPHI_C0INDCF_ORUN_BITS 29:29
170 #define MPHI_C0INDCF_ORUN_SET 0x20000000
171 #define MPHI_C0INDCF_ORUN_CLR 0xdfffffff
172 #define MPHI_C0INDCF_ORUN_MSB 29
173 #define MPHI_C0INDCF_ORUN_LSB 29
174 #define MPHI_C0INDCF_ORUN_RESET 0x0
175 #define MPHI_C0INDCF_MTERM_BITS 28:28
176 #define MPHI_C0INDCF_MTERM_SET 0x10000000
177 #define MPHI_C0INDCF_MTERM_CLR 0xefffffff
178 #define MPHI_C0INDCF_MTERM_MSB 28
179 #define MPHI_C0INDCF_MTERM_LSB 28
180 #define MPHI_C0INDCF_MTERM_RESET 0x0
181 #define MPHI_C0INDCF_HANDLE_BITS 27:20
182 #define MPHI_C0INDCF_HANDLE_SET 0x0ff00000
183 #define MPHI_C0INDCF_HANDLE_CLR 0xf00fffff
184 #define MPHI_C0INDCF_HANDLE_MSB 27
185 #define MPHI_C0INDCF_HANDLE_LSB 20
186 #define MPHI_C0INDCF_HANDLE_RESET 0x0
187 #define MPHI_C0INDCF_LENGTH_BITS 19:0
188 #define MPHI_C0INDCF_LENGTH_SET 0x000fffff
189 #define MPHI_C0INDCF_LENGTH_CLR 0xfff00000
190 #define MPHI_C0INDCF_LENGTH_MSB 19
191 #define MPHI_C0INDCF_LENGTH_LSB 0
192 #define MPHI_C0INDCF_LENGTH_RESET 0x0
193 #define MPHI_C1INDCF HW_REGISTER_RW( 0x7e00601c )
194 #define MPHI_C1INDCF_MASK 0xffffffff
195 #define MPHI_C1INDCF_WIDTH 32
196 #define MPHI_C1INDCF_EMPTY_BITS 31:31
197 #define MPHI_C1INDCF_EMPTY_SET 0x80000000
198 #define MPHI_C1INDCF_EMPTY_CLR 0x7fffffff
199 #define MPHI_C1INDCF_EMPTY_MSB 31
200 #define MPHI_C1INDCF_EMPTY_LSB 31
201 #define MPHI_C1INDCF_EMPTY_RESET 0x0
202 #define MPHI_C1INDCF_LENERR_BITS 30:30
203 #define MPHI_C1INDCF_LENERR_SET 0x40000000
204 #define MPHI_C1INDCF_LENERR_CLR 0xbfffffff
205 #define MPHI_C1INDCF_LENERR_MSB 30
206 #define MPHI_C1INDCF_LENERR_LSB 30
207 #define MPHI_C1INDCF_LENERR_RESET 0x0
208 #define MPHI_C1INDCF_ORUN_BITS 29:29
209 #define MPHI_C1INDCF_ORUN_SET 0x20000000
210 #define MPHI_C1INDCF_ORUN_CLR 0xdfffffff
211 #define MPHI_C1INDCF_ORUN_MSB 29
212 #define MPHI_C1INDCF_ORUN_LSB 29
213 #define MPHI_C1INDCF_ORUN_RESET 0x0
214 #define MPHI_C1INDCF_MTERM_BITS 28:28
215 #define MPHI_C1INDCF_MTERM_SET 0x10000000
216 #define MPHI_C1INDCF_MTERM_CLR 0xefffffff
217 #define MPHI_C1INDCF_MTERM_MSB 28
218 #define MPHI_C1INDCF_MTERM_LSB 28
219 #define MPHI_C1INDCF_MTERM_RESET 0x0
220 #define MPHI_C1INDCF_HANDLE_BITS 27:20
221 #define MPHI_C1INDCF_HANDLE_SET 0x0ff00000
222 #define MPHI_C1INDCF_HANDLE_CLR 0xf00fffff
223 #define MPHI_C1INDCF_HANDLE_MSB 27
224 #define MPHI_C1INDCF_HANDLE_LSB 20
225 #define MPHI_C1INDCF_HANDLE_RESET 0x0
226 #define MPHI_C1INDCF_LENGTH_BITS 19:0
227 #define MPHI_C1INDCF_LENGTH_SET 0x000fffff
228 #define MPHI_C1INDCF_LENGTH_CLR 0xfff00000
229 #define MPHI_C1INDCF_LENGTH_MSB 19
230 #define MPHI_C1INDCF_LENGTH_LSB 0
231 #define MPHI_C1INDCF_LENGTH_RESET 0x0
232 #define MPHI_C0INDFS HW_REGISTER_RW( 0x7e006020 )
233 #define MPHI_C0INDFS_MASK 0xffffffff
234 #define MPHI_C0INDFS_WIDTH 32
235 #define MPHI_C0INDFS_CFIFOLVL_BITS 31:16
236 #define MPHI_C0INDFS_CFIFOLVL_SET 0xffff0000
237 #define MPHI_C0INDFS_CFIFOLVL_CLR 0x0000ffff
238 #define MPHI_C0INDFS_CFIFOLVL_MSB 31
239 #define MPHI_C0INDFS_CFIFOLVL_LSB 16
240 #define MPHI_C0INDFS_CFIFOLVL_RESET 0x0
241 #define MPHI_C0INDFS_DFIFOLVL_BITS 15:0
242 #define MPHI_C0INDFS_DFIFOLVL_SET 0x0000ffff
243 #define MPHI_C0INDFS_DFIFOLVL_CLR 0xffff0000
244 #define MPHI_C0INDFS_DFIFOLVL_MSB 15
245 #define MPHI_C0INDFS_DFIFOLVL_LSB 0
246 #define MPHI_C0INDFS_DFIFOLVL_RESET 0x0
247 #define MPHI_C1INDFS HW_REGISTER_RW( 0x7e006024 )
248 #define MPHI_C1INDFS_MASK 0xffffffff
249 #define MPHI_C1INDFS_WIDTH 32
250 #define MPHI_C1INDFS_CFIFOLVL_BITS 31:16
251 #define MPHI_C1INDFS_CFIFOLVL_SET 0xffff0000
252 #define MPHI_C1INDFS_CFIFOLVL_CLR 0x0000ffff
253 #define MPHI_C1INDFS_CFIFOLVL_MSB 31
254 #define MPHI_C1INDFS_CFIFOLVL_LSB 16
255 #define MPHI_C1INDFS_CFIFOLVL_RESET 0x0
256 #define MPHI_C1INDFS_DFIFOLVL_BITS 15:0
257 #define MPHI_C1INDFS_DFIFOLVL_SET 0x0000ffff
258 #define MPHI_C1INDFS_DFIFOLVL_CLR 0xffff0000
259 #define MPHI_C1INDFS_DFIFOLVL_MSB 15
260 #define MPHI_C1INDFS_DFIFOLVL_LSB 0
261 #define MPHI_C1INDFS_DFIFOLVL_RESET 0x0
262 #define MPHI_OUTDDA HW_REGISTER_RW( 0x7e006028 )
263 #define MPHI_OUTDDA_MASK 0xffffffff
264 #define MPHI_OUTDDA_WIDTH 32
265 #define MPHI_OUTDDA_START_BITS 31:0
266 #define MPHI_OUTDDA_START_SET 0xffffffff
267 #define MPHI_OUTDDA_START_CLR 0x00000000
268 #define MPHI_OUTDDA_START_MSB 31
269 #define MPHI_OUTDDA_START_LSB 0
270 #define MPHI_OUTDDA_START_RESET 0x0
271 #define MPHI_OUTDDB HW_REGISTER_RW( 0x7e00602c )
272 #define MPHI_OUTDDB_MASK 0x3fffffff
273 #define MPHI_OUTDDB_WIDTH 30
274 #define MPHI_OUTDDB_TENDINT_BITS 29:29
275 #define MPHI_OUTDDB_TENDINT_SET 0x20000000
276 #define MPHI_OUTDDB_TENDINT_CLR 0xdfffffff
277 #define MPHI_OUTDDB_TENDINT_MSB 29
278 #define MPHI_OUTDDB_TENDINT_LSB 29
279 #define MPHI_OUTDDB_TENDINT_RESET 0x0
280 #define MPHI_OUTDDB_CHANNEL_BITS 28:28
281 #define MPHI_OUTDDB_CHANNEL_SET 0x10000000
282 #define MPHI_OUTDDB_CHANNEL_CLR 0xefffffff
283 #define MPHI_OUTDDB_CHANNEL_MSB 28
284 #define MPHI_OUTDDB_CHANNEL_LSB 28
285 #define MPHI_OUTDDB_CHANNEL_RESET 0x0
286 #define MPHI_OUTDDB_HANDLE_BITS 27:20
287 #define MPHI_OUTDDB_HANDLE_SET 0x0ff00000
288 #define MPHI_OUTDDB_HANDLE_CLR 0xf00fffff
289 #define MPHI_OUTDDB_HANDLE_MSB 27
290 #define MPHI_OUTDDB_HANDLE_LSB 20
291 #define MPHI_OUTDDB_HANDLE_RESET 0x0
292 #define MPHI_OUTDDB_LENGTH_BITS 19:0
293 #define MPHI_OUTDDB_LENGTH_SET 0x000fffff
294 #define MPHI_OUTDDB_LENGTH_CLR 0xfff00000
295 #define MPHI_OUTDDB_LENGTH_MSB 19
296 #define MPHI_OUTDDB_LENGTH_LSB 0
297 #define MPHI_OUTDDB_LENGTH_RESET 0x0
298 #define MPHI_OUTDS HW_REGISTER_RW( 0x7e006030 )
299 #define MPHI_OUTDS_MASK 0x5fffffff
300 #define MPHI_OUTDS_WIDTH 31
301 #define MPHI_OUTDS_VALID_BITS 30:30
302 #define MPHI_OUTDS_VALID_SET 0x40000000
303 #define MPHI_OUTDS_VALID_CLR 0xbfffffff
304 #define MPHI_OUTDS_VALID_MSB 30
305 #define MPHI_OUTDS_VALID_LSB 30
306 #define MPHI_OUTDS_VALID_RESET 0x0
307 #define MPHI_OUTDS_HANDLE_BITS 28:21
308 #define MPHI_OUTDS_HANDLE_SET 0x1fe00000
309 #define MPHI_OUTDS_HANDLE_CLR 0xe01fffff
310 #define MPHI_OUTDS_HANDLE_MSB 28
311 #define MPHI_OUTDS_HANDLE_LSB 21
312 #define MPHI_OUTDS_HANDLE_RESET 0x0
313 #define MPHI_OUTDS_WORDS_BITS 20:0
314 #define MPHI_OUTDS_WORDS_SET 0x001fffff
315 #define MPHI_OUTDS_WORDS_CLR 0xffe00000
316 #define MPHI_OUTDS_WORDS_MSB 20
317 #define MPHI_OUTDS_WORDS_LSB 0
318 #define MPHI_OUTDS_WORDS_RESET 0x0
319 #define MPHI_OUTDFS HW_REGISTER_RW( 0x7e006034 )
320 #define MPHI_OUTDFS_MASK 0xffffffff
321 #define MPHI_OUTDFS_WIDTH 32
322 #define MPHI_OUTDFS_DFIFOLVL_BITS 15:0
323 #define MPHI_OUTDFS_DFIFOLVL_SET 0x0000ffff
324 #define MPHI_OUTDFS_DFIFOLVL_CLR 0xffff0000
325 #define MPHI_OUTDFS_DFIFOLVL_MSB 15
326 #define MPHI_OUTDFS_DFIFOLVL_LSB 0
327 #define MPHI_OUTDFS_DFIFOLVL_RESET 0x0
328 #define MPHI_MINFS HW_REGISTER_RW( 0x7e006038 )
329 #define MPHI_MINFS_MASK 0xbfffffff
330 #define MPHI_MINFS_WIDTH 32
331 #define MPHI_MINFS_OFLOW_BITS 31:31
332 #define MPHI_MINFS_OFLOW_SET 0x80000000
333 #define MPHI_MINFS_OFLOW_CLR 0x7fffffff
334 #define MPHI_MINFS_OFLOW_MSB 31
335 #define MPHI_MINFS_OFLOW_LSB 31
336 #define MPHI_MINFS_OFLOW_RESET 0x0
337 #define MPHI_MINFS_RPTR_BITS 29:20
338 #define MPHI_MINFS_RPTR_SET 0x3ff00000
339 #define MPHI_MINFS_RPTR_CLR 0xc00fffff
340 #define MPHI_MINFS_RPTR_MSB 29
341 #define MPHI_MINFS_RPTR_LSB 20
342 #define MPHI_MINFS_RPTR_RESET 0x0
343 #define MPHI_MINFS_WPTR_BITS 19:10
344 #define MPHI_MINFS_WPTR_SET 0x000ffc00
345 #define MPHI_MINFS_WPTR_CLR 0xfff003ff
346 #define MPHI_MINFS_WPTR_MSB 19
347 #define MPHI_MINFS_WPTR_LSB 10
348 #define MPHI_MINFS_WPTR_RESET 0x0
349 #define MPHI_MINFS_LEVEL_BITS 9:0
350 #define MPHI_MINFS_LEVEL_SET 0x000003ff
351 #define MPHI_MINFS_LEVEL_CLR 0xfffffc00
352 #define MPHI_MINFS_LEVEL_MSB 9
353 #define MPHI_MINFS_LEVEL_LSB 0
354 #define MPHI_MINFS_LEVEL_RESET 0x0
355 #define MPHI_MOUTFS HW_REGISTER_RW( 0x7e00603c )
356 #define MPHI_MOUTFS_MASK 0xbfffffff
357 #define MPHI_MOUTFS_WIDTH 32
358 #define MPHI_MOUTFS_UFLOW_BITS 31:31
359 #define MPHI_MOUTFS_UFLOW_SET 0x80000000
360 #define MPHI_MOUTFS_UFLOW_CLR 0x7fffffff
361 #define MPHI_MOUTFS_UFLOW_MSB 31
362 #define MPHI_MOUTFS_UFLOW_LSB 31
363 #define MPHI_MOUTFS_UFLOW_RESET 0x0
364 #define MPHI_MOUTFS_RPTR_BITS 29:20
365 #define MPHI_MOUTFS_RPTR_SET 0x3ff00000
366 #define MPHI_MOUTFS_RPTR_CLR 0xc00fffff
367 #define MPHI_MOUTFS_RPTR_MSB 29
368 #define MPHI_MOUTFS_RPTR_LSB 20
369 #define MPHI_MOUTFS_RPTR_RESET 0x0
370 #define MPHI_MOUTFS_WPTR_BITS 19:10
371 #define MPHI_MOUTFS_WPTR_SET 0x000ffc00
372 #define MPHI_MOUTFS_WPTR_CLR 0xfff003ff
373 #define MPHI_MOUTFS_WPTR_MSB 19
374 #define MPHI_MOUTFS_WPTR_LSB 10
375 #define MPHI_MOUTFS_WPTR_RESET 0x0
376 #define MPHI_MOUTFS_LEVEL_BITS 9:0
377 #define MPHI_MOUTFS_LEVEL_SET 0x000003ff
378 #define MPHI_MOUTFS_LEVEL_CLR 0xfffffc00
379 #define MPHI_MOUTFS_LEVEL_MSB 9
380 #define MPHI_MOUTFS_LEVEL_LSB 0
381 #define MPHI_MOUTFS_LEVEL_RESET 0x0
382 #define MPHI_AXIPRIV HW_REGISTER_RW( 0x7e006040 )
383 #define MPHI_AXIPRIV_MASK 0x00000177
384 #define MPHI_AXIPRIV_WIDTH 9
385 #define MPHI_AXIPRIV_HSPECEN_BITS 8:8
386 #define MPHI_AXIPRIV_HSPECEN_SET 0x00000100
387 #define MPHI_AXIPRIV_HSPECEN_CLR 0xfffffeff
388 #define MPHI_AXIPRIV_HSPECEN_MSB 8
389 #define MPHI_AXIPRIV_HSPECEN_LSB 8
390 #define MPHI_AXIPRIV_HSPECEN_RESET 0x0
391 #define MPHI_AXIPRIV_RXPROT_BITS 6:4
392 #define MPHI_AXIPRIV_RXPROT_SET 0x00000070
393 #define MPHI_AXIPRIV_RXPROT_CLR 0xffffff8f
394 #define MPHI_AXIPRIV_RXPROT_MSB 6
395 #define MPHI_AXIPRIV_RXPROT_LSB 4
396 #define MPHI_AXIPRIV_RXPROT_RESET 0x2
397 #define MPHI_AXIPRIV_TXPROT_BITS 2:0
398 #define MPHI_AXIPRIV_TXPROT_SET 0x00000007
399 #define MPHI_AXIPRIV_TXPROT_CLR 0xfffffff8
400 #define MPHI_AXIPRIV_TXPROT_MSB 2
401 #define MPHI_AXIPRIV_TXPROT_LSB 0
402 #define MPHI_AXIPRIV_TXPROT_RESET 0x2
403 #define MPHI_RXAXICFG HW_REGISTER_RW( 0x7e006044 )
404 #define MPHI_RXAXICFG_MASK 0x0001ffff
405 #define MPHI_RXAXICFG_WIDTH 17
406 #define MPHI_RXAXICFG_INTHRESH_BITS 16:8
407 #define MPHI_RXAXICFG_INTHRESH_SET 0x0001ff00
408 #define MPHI_RXAXICFG_INTHRESH_CLR 0xfffe00ff
409 #define MPHI_RXAXICFG_INTHRESH_MSB 16
410 #define MPHI_RXAXICFG_INTHRESH_LSB 8
411 #define MPHI_RXAXICFG_INTHRESH_RESET 0x0
412 #define MPHI_RXAXICFG_RXPPRIO_BITS 7:4
413 #define MPHI_RXAXICFG_RXPPRIO_SET 0x000000f0
414 #define MPHI_RXAXICFG_RXPPRIO_CLR 0xffffff0f
415 #define MPHI_RXAXICFG_RXPPRIO_MSB 7
416 #define MPHI_RXAXICFG_RXPPRIO_LSB 4
417 #define MPHI_RXAXICFG_RXPPRIO_RESET 0x0
418 #define MPHI_RXAXICFG_RXNPRIO_BITS 3:0
419 #define MPHI_RXAXICFG_RXNPRIO_SET 0x0000000f
420 #define MPHI_RXAXICFG_RXNPRIO_CLR 0xfffffff0
421 #define MPHI_RXAXICFG_RXNPRIO_MSB 3
422 #define MPHI_RXAXICFG_RXNPRIO_LSB 0
423 #define MPHI_RXAXICFG_RXNPRIO_RESET 0x0
424 #define MPHI_TXAXICFG HW_REGISTER_RW( 0x7e006048 )
425 #define MPHI_TXAXICFG_MASK 0x0001ffff
426 #define MPHI_TXAXICFG_WIDTH 17
427 #define MPHI_TXAXICFG_INTHRESH_BITS 16:8
428 #define MPHI_TXAXICFG_INTHRESH_SET 0x0001ff00
429 #define MPHI_TXAXICFG_INTHRESH_CLR 0xfffe00ff
430 #define MPHI_TXAXICFG_INTHRESH_MSB 16
431 #define MPHI_TXAXICFG_INTHRESH_LSB 8
432 #define MPHI_TXAXICFG_INTHRESH_RESET 0x0
433 #define MPHI_TXAXICFG_TXPPRIO_BITS 7:4
434 #define MPHI_TXAXICFG_TXPPRIO_SET 0x000000f0
435 #define MPHI_TXAXICFG_TXPPRIO_CLR 0xffffff0f
436 #define MPHI_TXAXICFG_TXPPRIO_MSB 7
437 #define MPHI_TXAXICFG_TXPPRIO_LSB 4
438 #define MPHI_TXAXICFG_TXPPRIO_RESET 0x0
439 #define MPHI_TXAXICFG_TXNPRIO_BITS 3:0
440 #define MPHI_TXAXICFG_TXNPRIO_SET 0x0000000f
441 #define MPHI_TXAXICFG_TXNPRIO_CLR 0xfffffff0
442 #define MPHI_TXAXICFG_TXNPRIO_MSB 3
443 #define MPHI_TXAXICFG_TXNPRIO_LSB 0
444 #define MPHI_TXAXICFG_TXNPRIO_RESET 0x0
445 #define MPHI_CTRL HW_REGISTER_RW( 0x7e00604c )
446 #define MPHI_CTRL_MASK 0x88031111
447 #define MPHI_CTRL_WIDTH 32
448 #define MPHI_CTRL_ENABLE_BITS 31:31
449 #define MPHI_CTRL_ENABLE_SET 0x80000000
450 #define MPHI_CTRL_ENABLE_CLR 0x7fffffff
451 #define MPHI_CTRL_ENABLE_MSB 31
452 #define MPHI_CTRL_ENABLE_LSB 31
453 #define MPHI_CTRL_ENABLE_RESET 0x0
454 #define MPHI_CTRL_STBY_BITS 27:27
455 #define MPHI_CTRL_STBY_SET 0x08000000
456 #define MPHI_CTRL_STBY_CLR 0xf7ffffff
457 #define MPHI_CTRL_STBY_MSB 27
458 #define MPHI_CTRL_STBY_LSB 27
459 #define MPHI_CTRL_STBY_RESET 0x1
460 #define MPHI_CTRL_SOFT_RST_DNE_BITS 17:17
461 #define MPHI_CTRL_SOFT_RST_DNE_SET 0x00020000
462 #define MPHI_CTRL_SOFT_RST_DNE_CLR 0xfffdffff
463 #define MPHI_CTRL_SOFT_RST_DNE_MSB 17
464 #define MPHI_CTRL_SOFT_RST_DNE_LSB 17
465 #define MPHI_CTRL_SOFT_RST_DNE_RESET 0x0
466 #define MPHI_CTRL_REQ_SOFT_RST_BITS 16:16
467 #define MPHI_CTRL_REQ_SOFT_RST_SET 0x00010000
468 #define MPHI_CTRL_REQ_SOFT_RST_CLR 0xfffeffff
469 #define MPHI_CTRL_REQ_SOFT_RST_MSB 16
470 #define MPHI_CTRL_REQ_SOFT_RST_LSB 16
471 #define MPHI_CTRL_REQ_SOFT_RST_RESET 0x0
472 #define MPHI_CTRL_EIGHTBIT_BITS 12:12
473 #define MPHI_CTRL_EIGHTBIT_SET 0x00001000
474 #define MPHI_CTRL_EIGHTBIT_CLR 0xffffefff
475 #define MPHI_CTRL_EIGHTBIT_MSB 12
476 #define MPHI_CTRL_EIGHTBIT_LSB 12
477 #define MPHI_CTRL_EIGHTBIT_RESET 0x1
478 #define MPHI_CTRL_INVERT_BITS 8:8
479 #define MPHI_CTRL_INVERT_SET 0x00000100
480 #define MPHI_CTRL_INVERT_CLR 0xfffffeff
481 #define MPHI_CTRL_INVERT_MSB 8
482 #define MPHI_CTRL_INVERT_LSB 8
483 #define MPHI_CTRL_INVERT_RESET 0x0
484 #define MPHI_CTRL_DIRECT_BITS 4:4
485 #define MPHI_CTRL_DIRECT_SET 0x00000010
486 #define MPHI_CTRL_DIRECT_CLR 0xffffffef
487 #define MPHI_CTRL_DIRECT_MSB 4
488 #define MPHI_CTRL_DIRECT_LSB 4
489 #define MPHI_CTRL_DIRECT_RESET 0x0
490 #define MPHI_CTRL_HATVAL_BITS 0:0
491 #define MPHI_CTRL_HATVAL_SET 0x00000001
492 #define MPHI_CTRL_HATVAL_CLR 0xfffffffe
493 #define MPHI_CTRL_HATVAL_MSB 0
494 #define MPHI_CTRL_HATVAL_LSB 0
495 #define MPHI_CTRL_HATVAL_RESET 0x0
496 #define MPHI_INTSTAT HW_REGISTER_RW( 0x7e006050 )
497 #define MPHI_INTSTAT_MASK 0xf9111111
498 #define MPHI_INTSTAT_WIDTH 32
499 #define MPHI_INTSTAT_HSTEND_BITS 31:31
500 #define MPHI_INTSTAT_HSTEND_SET 0x80000000
501 #define MPHI_INTSTAT_HSTEND_CLR 0x7fffffff
502 #define MPHI_INTSTAT_HSTEND_MSB 31
503 #define MPHI_INTSTAT_HSTEND_LSB 31
504 #define MPHI_INTSTAT_HSTEND_RESET 0x0
505 #define MPHI_INTSTAT_HSDISC_BITS 30:30
506 #define MPHI_INTSTAT_HSDISC_SET 0x40000000
507 #define MPHI_INTSTAT_HSDISC_CLR 0xbfffffff
508 #define MPHI_INTSTAT_HSDISC_MSB 30
509 #define MPHI_INTSTAT_HSDISC_LSB 30
510 #define MPHI_INTSTAT_HSDISC_RESET 0x0
511 #define MPHI_INTSTAT_IMFOFLW_BITS 29:29
512 #define MPHI_INTSTAT_IMFOFLW_SET 0x20000000
513 #define MPHI_INTSTAT_IMFOFLW_CLR 0xdfffffff
514 #define MPHI_INTSTAT_IMFOFLW_MSB 29
515 #define MPHI_INTSTAT_IMFOFLW_LSB 29
516 #define MPHI_INTSTAT_IMFOFLW_RESET 0x0
517 #define MPHI_INTSTAT_OMFUFLW_BITS 28:28
518 #define MPHI_INTSTAT_OMFUFLW_SET 0x10000000
519 #define MPHI_INTSTAT_OMFUFLW_CLR 0xefffffff
520 #define MPHI_INTSTAT_OMFUFLW_MSB 28
521 #define MPHI_INTSTAT_OMFUFLW_LSB 28
522 #define MPHI_INTSTAT_OMFUFLW_RESET 0x0
523 #define MPHI_INTSTAT_HSDCFOFLW_BITS 27:27
524 #define MPHI_INTSTAT_HSDCFOFLW_SET 0x08000000
525 #define MPHI_INTSTAT_HSDCFOFLW_CLR 0xf7ffffff
526 #define MPHI_INTSTAT_HSDCFOFLW_MSB 27
527 #define MPHI_INTSTAT_HSDCFOFLW_LSB 27
528 #define MPHI_INTSTAT_HSDCFOFLW_RESET 0x0
529 #define MPHI_INTSTAT_RX1DISC_BITS 24:24
530 #define MPHI_INTSTAT_RX1DISC_SET 0x01000000
531 #define MPHI_INTSTAT_RX1DISC_CLR 0xfeffffff
532 #define MPHI_INTSTAT_RX1DISC_MSB 24
533 #define MPHI_INTSTAT_RX1DISC_LSB 24
534 #define MPHI_INTSTAT_RX1DISC_RESET 0x0
535 #define MPHI_INTSTAT_RX0DISC_BITS 20:20
536 #define MPHI_INTSTAT_RX0DISC_SET 0x00100000
537 #define MPHI_INTSTAT_RX0DISC_CLR 0xffefffff
538 #define MPHI_INTSTAT_RX0DISC_MSB 20
539 #define MPHI_INTSTAT_RX0DISC_LSB 20
540 #define MPHI_INTSTAT_RX0DISC_RESET 0x0
541 #define MPHI_INTSTAT_TXEND_BITS 16:16
542 #define MPHI_INTSTAT_TXEND_SET 0x00010000
543 #define MPHI_INTSTAT_TXEND_CLR 0xfffeffff
544 #define MPHI_INTSTAT_TXEND_MSB 16
545 #define MPHI_INTSTAT_TXEND_LSB 16
546 #define MPHI_INTSTAT_TXEND_RESET 0x0
547 #define MPHI_INTSTAT_RX1TEND_BITS 12:12
548 #define MPHI_INTSTAT_RX1TEND_SET 0x00001000
549 #define MPHI_INTSTAT_RX1TEND_CLR 0xffffefff
550 #define MPHI_INTSTAT_RX1TEND_MSB 12
551 #define MPHI_INTSTAT_RX1TEND_LSB 12
552 #define MPHI_INTSTAT_RX1TEND_RESET 0x0
553 #define MPHI_INTSTAT_RX1MEND_BITS 8:8
554 #define MPHI_INTSTAT_RX1MEND_SET 0x00000100
555 #define MPHI_INTSTAT_RX1MEND_CLR 0xfffffeff
556 #define MPHI_INTSTAT_RX1MEND_MSB 8
557 #define MPHI_INTSTAT_RX1MEND_LSB 8
558 #define MPHI_INTSTAT_RX1MEND_RESET 0x0
559 #define MPHI_INTSTAT_RX0TEND_BITS 4:4
560 #define MPHI_INTSTAT_RX0TEND_SET 0x00000010
561 #define MPHI_INTSTAT_RX0TEND_CLR 0xffffffef
562 #define MPHI_INTSTAT_RX0TEND_MSB 4
563 #define MPHI_INTSTAT_RX0TEND_LSB 4
564 #define MPHI_INTSTAT_RX0TEND_RESET 0x0
565 #define MPHI_INTSTAT_RX0MEND_BITS 0:0
566 #define MPHI_INTSTAT_RX0MEND_SET 0x00000001
567 #define MPHI_INTSTAT_RX0MEND_CLR 0xfffffffe
568 #define MPHI_INTSTAT_RX0MEND_MSB 0
569 #define MPHI_INTSTAT_RX0MEND_LSB 0
570 #define MPHI_INTSTAT_RX0MEND_RESET 0x0
571 #define MPHI_VERSION HW_REGISTER_RO( 0x7e006054 )
572 #define MPHI_VERSION_MASK 0xffffffff
573 #define MPHI_VERSION_WIDTH 32
574 #define MPHI_INTCTRL HW_REGISTER_RW( 0x7e006058 )
575 #define MPHI_INTCTRL_MASK 0x00111111
576 #define MPHI_INTCTRL_WIDTH 21
577 #define MPHI_INTCTRL_HSDCOFLW_BITS 20:20
578 #define MPHI_INTCTRL_HSDCOFLW_SET 0x00100000
579 #define MPHI_INTCTRL_HSDCOFLW_CLR 0xffefffff
580 #define MPHI_INTCTRL_HSDCOFLW_MSB 20
581 #define MPHI_INTCTRL_HSDCOFLW_LSB 20
582 #define MPHI_INTCTRL_HSDCOFLW_RESET 0x0
583 #define MPHI_INTCTRL_HSDISC_BITS 16:16
584 #define MPHI_INTCTRL_HSDISC_SET 0x00010000
585 #define MPHI_INTCTRL_HSDISC_CLR 0xfffeffff
586 #define MPHI_INTCTRL_HSDISC_MSB 16
587 #define MPHI_INTCTRL_HSDISC_LSB 16
588 #define MPHI_INTCTRL_HSDISC_RESET 0x0
589 #define MPHI_INTCTRL_OMFUFLW_BITS 12:12
590 #define MPHI_INTCTRL_OMFUFLW_SET 0x00001000
591 #define MPHI_INTCTRL_OMFUFLW_CLR 0xffffefff
592 #define MPHI_INTCTRL_OMFUFLW_MSB 12
593 #define MPHI_INTCTRL_OMFUFLW_LSB 12
594 #define MPHI_INTCTRL_OMFUFLW_RESET 0x0
595 #define MPHI_INTCTRL_IMFOFLW_BITS 8:8
596 #define MPHI_INTCTRL_IMFOFLW_SET 0x00000100
597 #define MPHI_INTCTRL_IMFOFLW_CLR 0xfffffeff
598 #define MPHI_INTCTRL_IMFOFLW_MSB 8
599 #define MPHI_INTCTRL_IMFOFLW_LSB 8
600 #define MPHI_INTCTRL_IMFOFLW_RESET 0x0
601 #define MPHI_INTCTRL_RX1DISC_BITS 4:4
602 #define MPHI_INTCTRL_RX1DISC_SET 0x00000010
603 #define MPHI_INTCTRL_RX1DISC_CLR 0xffffffef
604 #define MPHI_INTCTRL_RX1DISC_MSB 4
605 #define MPHI_INTCTRL_RX1DISC_LSB 4
606 #define MPHI_INTCTRL_RX1DISC_RESET 0x0
607 #define MPHI_INTCTRL_RX0DISC_BITS 0:0
608 #define MPHI_INTCTRL_RX0DISC_SET 0x00000001
609 #define MPHI_INTCTRL_RX0DISC_CLR 0xfffffffe
610 #define MPHI_INTCTRL_RX0DISC_MSB 0
611 #define MPHI_INTCTRL_RX0DISC_LSB 0
612 #define MPHI_INTCTRL_RX0DISC_RESET 0x0
613 #define MPHI_HSINDCF HW_REGISTER_RW( 0x7e00605c )
614 #define MPHI_HSINDCF_MASK 0xdfffffff
615 #define MPHI_HSINDCF_WIDTH 32
616 #define MPHI_HSINDCF_EMPTY_BITS 31:31
617 #define MPHI_HSINDCF_EMPTY_SET 0x80000000
618 #define MPHI_HSINDCF_EMPTY_CLR 0x7fffffff
619 #define MPHI_HSINDCF_EMPTY_MSB 31
620 #define MPHI_HSINDCF_EMPTY_LSB 31
621 #define MPHI_HSINDCF_EMPTY_RESET 0x0
622 #define MPHI_HSINDCF_LENERR_BITS 30:30
623 #define MPHI_HSINDCF_LENERR_SET 0x40000000
624 #define MPHI_HSINDCF_LENERR_CLR 0xbfffffff
625 #define MPHI_HSINDCF_LENERR_MSB 30
626 #define MPHI_HSINDCF_LENERR_LSB 30
627 #define MPHI_HSINDCF_LENERR_RESET 0x0
628 #define MPHI_HSINDCF_MTERM_BITS 28:28
629 #define MPHI_HSINDCF_MTERM_SET 0x10000000
630 #define MPHI_HSINDCF_MTERM_CLR 0xefffffff
631 #define MPHI_HSINDCF_MTERM_MSB 28
632 #define MPHI_HSINDCF_MTERM_LSB 28
633 #define MPHI_HSINDCF_MTERM_RESET 0x0
634 #define MPHI_HSINDCF_HANDLE_BITS 27:20
635 #define MPHI_HSINDCF_HANDLE_SET 0x0ff00000
636 #define MPHI_HSINDCF_HANDLE_CLR 0xf00fffff
637 #define MPHI_HSINDCF_HANDLE_MSB 27
638 #define MPHI_HSINDCF_HANDLE_LSB 20
639 #define MPHI_HSINDCF_HANDLE_RESET 0x0
640 #define MPHI_HSINDCF_LENGTH_BITS 19:0
641 #define MPHI_HSINDCF_LENGTH_SET 0x000fffff
642 #define MPHI_HSINDCF_LENGTH_CLR 0xfff00000
643 #define MPHI_HSINDCF_LENGTH_MSB 19
644 #define MPHI_HSINDCF_LENGTH_LSB 0
645 #define MPHI_HSINDCF_LENGTH_RESET 0x0
646 #define MPHI_HSINDS HW_REGISTER_RW( 0x7e006060 )
647 #define MPHI_HSINDS_MASK 0xdfffffff
648 #define MPHI_HSINDS_WIDTH 32
649 #define MPHI_HSINDS_DISCARD_BITS 31:31
650 #define MPHI_HSINDS_DISCARD_SET 0x80000000
651 #define MPHI_HSINDS_DISCARD_CLR 0x7fffffff
652 #define MPHI_HSINDS_DISCARD_MSB 31
653 #define MPHI_HSINDS_DISCARD_LSB 31
654 #define MPHI_HSINDS_DISCARD_RESET 0x0
655 #define MPHI_HSINDS_VALID_BITS 30:30
656 #define MPHI_HSINDS_VALID_SET 0x40000000
657 #define MPHI_HSINDS_VALID_CLR 0xbfffffff
658 #define MPHI_HSINDS_VALID_MSB 30
659 #define MPHI_HSINDS_VALID_LSB 30
660 #define MPHI_HSINDS_VALID_RESET 0x0
661 #define MPHI_HSINDS_HANDLE_BITS 28:21
662 #define MPHI_HSINDS_HANDLE_SET 0x1fe00000
663 #define MPHI_HSINDS_HANDLE_CLR 0xe01fffff
664 #define MPHI_HSINDS_HANDLE_MSB 28
665 #define MPHI_HSINDS_HANDLE_LSB 21
666 #define MPHI_HSINDS_HANDLE_RESET 0x0
667 #define MPHI_HSINDS_WORDS_BITS 20:0
668 #define MPHI_HSINDS_WORDS_SET 0x001fffff
669 #define MPHI_HSINDS_WORDS_CLR 0xffe00000
670 #define MPHI_HSINDS_WORDS_MSB 20
671 #define MPHI_HSINDS_WORDS_LSB 0
672 #define MPHI_HSINDS_WORDS_RESET 0x0
673 #define MPHI_HSINDDA HW_REGISTER_RW( 0x7e006064 )
674 #define MPHI_HSINDDA_MASK 0xffffffff
675 #define MPHI_HSINDDA_WIDTH 32
676 #define MPHI_HSINDDA_START_BITS 31:0
677 #define MPHI_HSINDDA_START_SET 0xffffffff
678 #define MPHI_HSINDDA_START_CLR 0x00000000
679 #define MPHI_HSINDDA_START_MSB 31
680 #define MPHI_HSINDDA_START_LSB 0
681 #define MPHI_HSINDDA_START_RESET 0x0
682 #define MPHI_HSINDDB HW_REGISTER_RW( 0x7e006068 )
683 #define MPHI_HSINDDB_MASK 0x2fffffff
684 #define MPHI_HSINDDB_WIDTH 30
685 #define MPHI_HSINDDB_TENDINT_BITS 29:29
686 #define MPHI_HSINDDB_TENDINT_SET 0x20000000
687 #define MPHI_HSINDDB_TENDINT_CLR 0xdfffffff
688 #define MPHI_HSINDDB_TENDINT_MSB 29
689 #define MPHI_HSINDDB_TENDINT_LSB 29
690 #define MPHI_HSINDDB_TENDINT_RESET 0x0
691 #define MPHI_HSINDDB_HANDLE_BITS 27:20
692 #define MPHI_HSINDDB_HANDLE_SET 0x0ff00000
693 #define MPHI_HSINDDB_HANDLE_CLR 0xf00fffff
694 #define MPHI_HSINDDB_HANDLE_MSB 27
695 #define MPHI_HSINDDB_HANDLE_LSB 20
696 #define MPHI_HSINDDB_HANDLE_RESET 0x0
697 #define MPHI_HSINDDB_LENGTH_BITS 19:0
698 #define MPHI_HSINDDB_LENGTH_SET 0x000fffff
699 #define MPHI_HSINDDB_LENGTH_CLR 0xfff00000
700 #define MPHI_HSINDDB_LENGTH_MSB 19
701 #define MPHI_HSINDDB_LENGTH_LSB 0
702 #define MPHI_HSINDDB_LENGTH_RESET 0x0
703 #define MPHI_HSINDFS HW_REGISTER_RW( 0x7e00606c )
704 #define MPHI_HSINDFS_MASK 0xffff0001
705 #define MPHI_HSINDFS_WIDTH 32
706 #define MPHI_HSINDFS_CFIFOLVL_BITS 31:16
707 #define MPHI_HSINDFS_CFIFOLVL_SET 0xffff0000
708 #define MPHI_HSINDFS_CFIFOLVL_CLR 0x0000ffff
709 #define MPHI_HSINDFS_CFIFOLVL_MSB 31
710 #define MPHI_HSINDFS_CFIFOLVL_LSB 16
711 #define MPHI_HSINDFS_CFIFOLVL_RESET 0x0
712 #define MPHI_HSINDFS_DFIFOLVL_BITS 0:0
713 #define MPHI_HSINDFS_DFIFOLVL_SET 0x00000001
714 #define MPHI_HSINDFS_DFIFOLVL_CLR 0xfffffffe
715 #define MPHI_HSINDFS_DFIFOLVL_MSB 0
716 #define MPHI_HSINDFS_DFIFOLVL_LSB 0
717 #define MPHI_HSINDFS_DFIFOLVL_RESET 0x0
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