Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / multicore_sync.h
1 // This file was generated by the create_regs script
2 #define MS_BASE 0x7e000000
3 #define MS_APB_ID 0x4d554c54
4 #define MS_SEMA_0 HW_REGISTER_RW( 0x7e000000 )
5 #define MS_SEMA_0_MASK 0x00000001
6 #define MS_SEMA_0_WIDTH 1
7 #define MS_SEMA_0_RESET 0000000000
8 #define MS_SEMA_0_MASK_BITS 0:0
9 #define MS_SEMA_0_MASK_SET 0x00000001
10 #define MS_SEMA_0_MASK_CLR 0xfffffffe
11 #define MS_SEMA_0_MASK_MSB 0
12 #define MS_SEMA_0_MASK_LSB 0
13 #define MS_SEMA_1 HW_REGISTER_RW( 0x7e000004 )
14 #define MS_SEMA_1_MASK 0x00000001
15 #define MS_SEMA_1_WIDTH 1
16 #define MS_SEMA_1_RESET 0000000000
17 #define MS_SEMA_1_MASK_BITS 0:0
18 #define MS_SEMA_1_MASK_SET 0x00000001
19 #define MS_SEMA_1_MASK_CLR 0xfffffffe
20 #define MS_SEMA_1_MASK_MSB 0
21 #define MS_SEMA_1_MASK_LSB 0
22 #define MS_SEMA_2 HW_REGISTER_RW( 0x7e000008 )
23 #define MS_SEMA_2_MASK 0x00000001
24 #define MS_SEMA_2_WIDTH 1
25 #define MS_SEMA_2_RESET 0000000000
26 #define MS_SEMA_2_MASK_BITS 0:0
27 #define MS_SEMA_2_MASK_SET 0x00000001
28 #define MS_SEMA_2_MASK_CLR 0xfffffffe
29 #define MS_SEMA_2_MASK_MSB 0
30 #define MS_SEMA_2_MASK_LSB 0
31 #define MS_SEMA_3 HW_REGISTER_RW( 0x7e00000c )
32 #define MS_SEMA_3_MASK 0x00000001
33 #define MS_SEMA_3_WIDTH 1
34 #define MS_SEMA_3_RESET 0000000000
35 #define MS_SEMA_3_MASK_BITS 0:0
36 #define MS_SEMA_3_MASK_SET 0x00000001
37 #define MS_SEMA_3_MASK_CLR 0xfffffffe
38 #define MS_SEMA_3_MASK_MSB 0
39 #define MS_SEMA_3_MASK_LSB 0
40 #define MS_SEMA_4 HW_REGISTER_RW( 0x7e000010 )
41 #define MS_SEMA_4_MASK 0x00000001
42 #define MS_SEMA_4_WIDTH 1
43 #define MS_SEMA_4_RESET 0000000000
44 #define MS_SEMA_4_MASK_BITS 0:0
45 #define MS_SEMA_4_MASK_SET 0x00000001
46 #define MS_SEMA_4_MASK_CLR 0xfffffffe
47 #define MS_SEMA_4_MASK_MSB 0
48 #define MS_SEMA_4_MASK_LSB 0
49 #define MS_SEMA_5 HW_REGISTER_RW( 0x7e000014 )
50 #define MS_SEMA_5_MASK 0x00000001
51 #define MS_SEMA_5_WIDTH 1
52 #define MS_SEMA_5_RESET 0000000000
53 #define MS_SEMA_5_MASK_BITS 0:0
54 #define MS_SEMA_5_MASK_SET 0x00000001
55 #define MS_SEMA_5_MASK_CLR 0xfffffffe
56 #define MS_SEMA_5_MASK_MSB 0
57 #define MS_SEMA_5_MASK_LSB 0
58 #define MS_SEMA_6 HW_REGISTER_RW( 0x7e000018 )
59 #define MS_SEMA_6_MASK 0x00000001
60 #define MS_SEMA_6_WIDTH 1
61 #define MS_SEMA_6_RESET 0000000000
62 #define MS_SEMA_6_MASK_BITS 0:0
63 #define MS_SEMA_6_MASK_SET 0x00000001
64 #define MS_SEMA_6_MASK_CLR 0xfffffffe
65 #define MS_SEMA_6_MASK_MSB 0
66 #define MS_SEMA_6_MASK_LSB 0
67 #define MS_SEMA_7 HW_REGISTER_RW( 0x7e00001c )
68 #define MS_SEMA_7_MASK 0x00000001
69 #define MS_SEMA_7_WIDTH 1
70 #define MS_SEMA_7_RESET 0000000000
71 #define MS_SEMA_7_MASK_BITS 0:0
72 #define MS_SEMA_7_MASK_SET 0x00000001
73 #define MS_SEMA_7_MASK_CLR 0xfffffffe
74 #define MS_SEMA_7_MASK_MSB 0
75 #define MS_SEMA_7_MASK_LSB 0
76 #define MS_SEMA_8 HW_REGISTER_RW( 0x7e000020 )
77 #define MS_SEMA_8_MASK 0x00000001
78 #define MS_SEMA_8_WIDTH 1
79 #define MS_SEMA_8_RESET 0000000000
80 #define MS_SEMA_8_MASK_BITS 0:0
81 #define MS_SEMA_8_MASK_SET 0x00000001
82 #define MS_SEMA_8_MASK_CLR 0xfffffffe
83 #define MS_SEMA_8_MASK_MSB 0
84 #define MS_SEMA_8_MASK_LSB 0
85 #define MS_SEMA_9 HW_REGISTER_RW( 0x7e000024 )
86 #define MS_SEMA_9_MASK 0x00000001
87 #define MS_SEMA_9_WIDTH 1
88 #define MS_SEMA_9_RESET 0000000000
89 #define MS_SEMA_9_MASK_BITS 0:0
90 #define MS_SEMA_9_MASK_SET 0x00000001
91 #define MS_SEMA_9_MASK_CLR 0xfffffffe
92 #define MS_SEMA_9_MASK_MSB 0
93 #define MS_SEMA_9_MASK_LSB 0
94 #define MS_SEMA_10 HW_REGISTER_RW( 0x7e000028 )
95 #define MS_SEMA_10_MASK 0x00000001
96 #define MS_SEMA_10_WIDTH 1
97 #define MS_SEMA_10_RESET 0000000000
98 #define MS_SEMA_10_MASK_BITS 0:0
99 #define MS_SEMA_10_MASK_SET 0x00000001
100 #define MS_SEMA_10_MASK_CLR 0xfffffffe
101 #define MS_SEMA_10_MASK_MSB 0
102 #define MS_SEMA_10_MASK_LSB 0
103 #define MS_SEMA_11 HW_REGISTER_RW( 0x7e00002c )
104 #define MS_SEMA_11_MASK 0x00000001
105 #define MS_SEMA_11_WIDTH 1
106 #define MS_SEMA_11_RESET 0000000000
107 #define MS_SEMA_11_MASK_BITS 0:0
108 #define MS_SEMA_11_MASK_SET 0x00000001
109 #define MS_SEMA_11_MASK_CLR 0xfffffffe
110 #define MS_SEMA_11_MASK_MSB 0
111 #define MS_SEMA_11_MASK_LSB 0
112 #define MS_SEMA_12 HW_REGISTER_RW( 0x7e000030 )
113 #define MS_SEMA_12_MASK 0x00000001
114 #define MS_SEMA_12_WIDTH 1
115 #define MS_SEMA_12_RESET 0000000000
116 #define MS_SEMA_12_MASK_BITS 0:0
117 #define MS_SEMA_12_MASK_SET 0x00000001
118 #define MS_SEMA_12_MASK_CLR 0xfffffffe
119 #define MS_SEMA_12_MASK_MSB 0
120 #define MS_SEMA_12_MASK_LSB 0
121 #define MS_SEMA_13 HW_REGISTER_RW( 0x7e000034 )
122 #define MS_SEMA_13_MASK 0x00000001
123 #define MS_SEMA_13_WIDTH 1
124 #define MS_SEMA_13_RESET 0000000000
125 #define MS_SEMA_13_MASK_BITS 0:0
126 #define MS_SEMA_13_MASK_SET 0x00000001
127 #define MS_SEMA_13_MASK_CLR 0xfffffffe
128 #define MS_SEMA_13_MASK_MSB 0
129 #define MS_SEMA_13_MASK_LSB 0
130 #define MS_SEMA_14 HW_REGISTER_RW( 0x7e000038 )
131 #define MS_SEMA_14_MASK 0x00000001
132 #define MS_SEMA_14_WIDTH 1
133 #define MS_SEMA_14_RESET 0000000000
134 #define MS_SEMA_14_MASK_BITS 0:0
135 #define MS_SEMA_14_MASK_SET 0x00000001
136 #define MS_SEMA_14_MASK_CLR 0xfffffffe
137 #define MS_SEMA_14_MASK_MSB 0
138 #define MS_SEMA_14_MASK_LSB 0
139 #define MS_SEMA_15 HW_REGISTER_RW( 0x7e00003c )
140 #define MS_SEMA_15_MASK 0x00000001
141 #define MS_SEMA_15_WIDTH 1
142 #define MS_SEMA_15_RESET 0000000000
143 #define MS_SEMA_15_MASK_BITS 0:0
144 #define MS_SEMA_15_MASK_SET 0x00000001
145 #define MS_SEMA_15_MASK_CLR 0xfffffffe
146 #define MS_SEMA_15_MASK_MSB 0
147 #define MS_SEMA_15_MASK_LSB 0
148 #define MS_SEMA_16 HW_REGISTER_RW( 0x7e000040 )
149 #define MS_SEMA_16_MASK 0x00000001
150 #define MS_SEMA_16_WIDTH 1
151 #define MS_SEMA_16_RESET 0000000000
152 #define MS_SEMA_16_MASK_BITS 0:0
153 #define MS_SEMA_16_MASK_SET 0x00000001
154 #define MS_SEMA_16_MASK_CLR 0xfffffffe
155 #define MS_SEMA_16_MASK_MSB 0
156 #define MS_SEMA_16_MASK_LSB 0
157 #define MS_SEMA_17 HW_REGISTER_RW( 0x7e000044 )
158 #define MS_SEMA_17_MASK 0x00000001
159 #define MS_SEMA_17_WIDTH 1
160 #define MS_SEMA_17_RESET 0000000000
161 #define MS_SEMA_17_MASK_BITS 0:0
162 #define MS_SEMA_17_MASK_SET 0x00000001
163 #define MS_SEMA_17_MASK_CLR 0xfffffffe
164 #define MS_SEMA_17_MASK_MSB 0
165 #define MS_SEMA_17_MASK_LSB 0
166 #define MS_SEMA_18 HW_REGISTER_RW( 0x7e000048 )
167 #define MS_SEMA_18_MASK 0x00000001
168 #define MS_SEMA_18_WIDTH 1
169 #define MS_SEMA_18_RESET 0000000000
170 #define MS_SEMA_18_MASK_BITS 0:0
171 #define MS_SEMA_18_MASK_SET 0x00000001
172 #define MS_SEMA_18_MASK_CLR 0xfffffffe
173 #define MS_SEMA_18_MASK_MSB 0
174 #define MS_SEMA_18_MASK_LSB 0
175 #define MS_SEMA_19 HW_REGISTER_RW( 0x7e00004c )
176 #define MS_SEMA_19_MASK 0x00000001
177 #define MS_SEMA_19_WIDTH 1
178 #define MS_SEMA_19_RESET 0000000000
179 #define MS_SEMA_19_MASK_BITS 0:0
180 #define MS_SEMA_19_MASK_SET 0x00000001
181 #define MS_SEMA_19_MASK_CLR 0xfffffffe
182 #define MS_SEMA_19_MASK_MSB 0
183 #define MS_SEMA_19_MASK_LSB 0
184 #define MS_SEMA_20 HW_REGISTER_RW( 0x7e000050 )
185 #define MS_SEMA_20_MASK 0x00000001
186 #define MS_SEMA_20_WIDTH 1
187 #define MS_SEMA_20_RESET 0000000000
188 #define MS_SEMA_20_MASK_BITS 0:0
189 #define MS_SEMA_20_MASK_SET 0x00000001
190 #define MS_SEMA_20_MASK_CLR 0xfffffffe
191 #define MS_SEMA_20_MASK_MSB 0
192 #define MS_SEMA_20_MASK_LSB 0
193 #define MS_SEMA_21 HW_REGISTER_RW( 0x7e000054 )
194 #define MS_SEMA_21_MASK 0x00000001
195 #define MS_SEMA_21_WIDTH 1
196 #define MS_SEMA_21_RESET 0000000000
197 #define MS_SEMA_21_MASK_BITS 0:0
198 #define MS_SEMA_21_MASK_SET 0x00000001
199 #define MS_SEMA_21_MASK_CLR 0xfffffffe
200 #define MS_SEMA_21_MASK_MSB 0
201 #define MS_SEMA_21_MASK_LSB 0
202 #define MS_SEMA_22 HW_REGISTER_RW( 0x7e000058 )
203 #define MS_SEMA_22_MASK 0x00000001
204 #define MS_SEMA_22_WIDTH 1
205 #define MS_SEMA_22_RESET 0000000000
206 #define MS_SEMA_22_MASK_BITS 0:0
207 #define MS_SEMA_22_MASK_SET 0x00000001
208 #define MS_SEMA_22_MASK_CLR 0xfffffffe
209 #define MS_SEMA_22_MASK_MSB 0
210 #define MS_SEMA_22_MASK_LSB 0
211 #define MS_SEMA_23 HW_REGISTER_RW( 0x7e00005c )
212 #define MS_SEMA_23_MASK 0x00000001
213 #define MS_SEMA_23_WIDTH 1
214 #define MS_SEMA_23_RESET 0000000000
215 #define MS_SEMA_23_MASK_BITS 0:0
216 #define MS_SEMA_23_MASK_SET 0x00000001
217 #define MS_SEMA_23_MASK_CLR 0xfffffffe
218 #define MS_SEMA_23_MASK_MSB 0
219 #define MS_SEMA_23_MASK_LSB 0
220 #define MS_SEMA_24 HW_REGISTER_RW( 0x7e000060 )
221 #define MS_SEMA_24_MASK 0x00000001
222 #define MS_SEMA_24_WIDTH 1
223 #define MS_SEMA_24_RESET 0000000000
224 #define MS_SEMA_24_MASK_BITS 0:0
225 #define MS_SEMA_24_MASK_SET 0x00000001
226 #define MS_SEMA_24_MASK_CLR 0xfffffffe
227 #define MS_SEMA_24_MASK_MSB 0
228 #define MS_SEMA_24_MASK_LSB 0
229 #define MS_SEMA_25 HW_REGISTER_RW( 0x7e000064 )
230 #define MS_SEMA_25_MASK 0x00000001
231 #define MS_SEMA_25_WIDTH 1
232 #define MS_SEMA_25_RESET 0000000000
233 #define MS_SEMA_25_MASK_BITS 0:0
234 #define MS_SEMA_25_MASK_SET 0x00000001
235 #define MS_SEMA_25_MASK_CLR 0xfffffffe
236 #define MS_SEMA_25_MASK_MSB 0
237 #define MS_SEMA_25_MASK_LSB 0
238 #define MS_SEMA_26 HW_REGISTER_RW( 0x7e000068 )
239 #define MS_SEMA_26_MASK 0x00000001
240 #define MS_SEMA_26_WIDTH 1
241 #define MS_SEMA_26_RESET 0000000000
242 #define MS_SEMA_26_MASK_BITS 0:0
243 #define MS_SEMA_26_MASK_SET 0x00000001
244 #define MS_SEMA_26_MASK_CLR 0xfffffffe
245 #define MS_SEMA_26_MASK_MSB 0
246 #define MS_SEMA_26_MASK_LSB 0
247 #define MS_SEMA_27 HW_REGISTER_RW( 0x7e00006c )
248 #define MS_SEMA_27_MASK 0x00000001
249 #define MS_SEMA_27_WIDTH 1
250 #define MS_SEMA_27_RESET 0000000000
251 #define MS_SEMA_27_MASK_BITS 0:0
252 #define MS_SEMA_27_MASK_SET 0x00000001
253 #define MS_SEMA_27_MASK_CLR 0xfffffffe
254 #define MS_SEMA_27_MASK_MSB 0
255 #define MS_SEMA_27_MASK_LSB 0
256 #define MS_SEMA_28 HW_REGISTER_RW( 0x7e000070 )
257 #define MS_SEMA_28_MASK 0x00000001
258 #define MS_SEMA_28_WIDTH 1
259 #define MS_SEMA_28_RESET 0000000000
260 #define MS_SEMA_28_MASK_BITS 0:0
261 #define MS_SEMA_28_MASK_SET 0x00000001
262 #define MS_SEMA_28_MASK_CLR 0xfffffffe
263 #define MS_SEMA_28_MASK_MSB 0
264 #define MS_SEMA_28_MASK_LSB 0
265 #define MS_SEMA_29 HW_REGISTER_RW( 0x7e000074 )
266 #define MS_SEMA_29_MASK 0x00000001
267 #define MS_SEMA_29_WIDTH 1
268 #define MS_SEMA_29_RESET 0000000000
269 #define MS_SEMA_29_MASK_BITS 0:0
270 #define MS_SEMA_29_MASK_SET 0x00000001
271 #define MS_SEMA_29_MASK_CLR 0xfffffffe
272 #define MS_SEMA_29_MASK_MSB 0
273 #define MS_SEMA_29_MASK_LSB 0
274 #define MS_SEMA_30 HW_REGISTER_RW( 0x7e000078 )
275 #define MS_SEMA_30_MASK 0x00000001
276 #define MS_SEMA_30_WIDTH 1
277 #define MS_SEMA_30_RESET 0000000000
278 #define MS_SEMA_30_MASK_BITS 0:0
279 #define MS_SEMA_30_MASK_SET 0x00000001
280 #define MS_SEMA_30_MASK_CLR 0xfffffffe
281 #define MS_SEMA_30_MASK_MSB 0
282 #define MS_SEMA_30_MASK_LSB 0
283 #define MS_SEMA_31 HW_REGISTER_RW( 0x7e00007c )
284 #define MS_SEMA_31_MASK 0x00000001
285 #define MS_SEMA_31_WIDTH 1
286 #define MS_SEMA_31_RESET 0000000000
287 #define MS_SEMA_31_MASK_BITS 0:0
288 #define MS_SEMA_31_MASK_SET 0x00000001
289 #define MS_SEMA_31_MASK_CLR 0xfffffffe
290 #define MS_SEMA_31_MASK_MSB 0
291 #define MS_SEMA_31_MASK_LSB 0
292 #define MS_STATUS HW_REGISTER_RO( 0x7e000080 )
293 #define MS_STATUS_MASK 0xffffffff
294 #define MS_STATUS_WIDTH 32
295 #define MS_STATUS_RESET 0000000000
296 #define MS_STATUS_STATUS_BITS 31:0
297 #define MS_STATUS_STATUS_SET 0xffffffff
298 #define MS_STATUS_STATUS_CLR 0x00000000
299 #define MS_STATUS_STATUS_MSB 31
300 #define MS_STATUS_STATUS_LSB 0
301 #define MS_IREQ_0 HW_REGISTER_RW( 0x7e000084 )
302 #define MS_IREQ_0_MASK 0xffffffff
303 #define MS_IREQ_0_WIDTH 32
304 #define MS_IREQ_0_RESET 0000000000
305 #define MS_IREQ_0_IREQ_0_BITS 31:0
306 #define MS_IREQ_0_IREQ_0_SET 0xffffffff
307 #define MS_IREQ_0_IREQ_0_CLR 0x00000000
308 #define MS_IREQ_0_IREQ_0_MSB 31
309 #define MS_IREQ_0_IREQ_0_LSB 0
310 #define MS_IREQ_1 HW_REGISTER_RW( 0x7e000088 )
311 #define MS_IREQ_1_MASK 0xffffffff
312 #define MS_IREQ_1_WIDTH 32
313 #define MS_IREQ_1_RESET 0000000000
314 #define MS_IREQ_1_IREQ_1_BITS 31:0
315 #define MS_IREQ_1_IREQ_1_SET 0xffffffff
316 #define MS_IREQ_1_IREQ_1_CLR 0x00000000
317 #define MS_IREQ_1_IREQ_1_MSB 31
318 #define MS_IREQ_1_IREQ_1_LSB 0
319 #define MS_ICSET_0 HW_REGISTER_RW( 0x7e000090 )
320 #define MS_ICSET_0_MASK 0x00000001
321 #define MS_ICSET_0_WIDTH 1
322 #define MS_ICSET_0_RESET 0000000000
323 #define MS_ICSET_0_ICSET_0_BITS 0:0
324 #define MS_ICSET_0_ICSET_0_SET 0x00000001
325 #define MS_ICSET_0_ICSET_0_CLR 0xfffffffe
326 #define MS_ICSET_0_ICSET_0_MSB 0
327 #define MS_ICSET_0_ICSET_0_LSB 0
328 #define MS_ICSET_1 HW_REGISTER_RW( 0x7e000094 )
329 #define MS_ICSET_1_MASK 0x00000001
330 #define MS_ICSET_1_WIDTH 1
331 #define MS_ICSET_1_RESET 0000000000
332 #define MS_ICSET_1_ICSET_1_BITS 0:0
333 #define MS_ICSET_1_ICSET_1_SET 0x00000001
334 #define MS_ICSET_1_ICSET_1_CLR 0xfffffffe
335 #define MS_ICSET_1_ICSET_1_MSB 0
336 #define MS_ICSET_1_ICSET_1_LSB 0
337 #define MS_ICCLR_0 HW_REGISTER_RW( 0x7e000098 )
338 #define MS_ICCLR_0_MASK 0x00000001
339 #define MS_ICCLR_0_WIDTH 1
340 #define MS_ICCLR_0_RESET 0000000000
341 #define MS_ICCLR_0_ICCLR_0_BITS 0:0
342 #define MS_ICCLR_0_ICCLR_0_SET 0x00000001
343 #define MS_ICCLR_0_ICCLR_0_CLR 0xfffffffe
344 #define MS_ICCLR_0_ICCLR_0_MSB 0
345 #define MS_ICCLR_0_ICCLR_0_LSB 0
346 #define MS_ICCLR_1 HW_REGISTER_RW( 0x7e00009c )
347 #define MS_ICCLR_1_MASK 0x00000001
348 #define MS_ICCLR_1_WIDTH 1
349 #define MS_ICCLR_1_RESET 0000000000
350 #define MS_ICCLR_1_ICCLR_1_BITS 0:0
351 #define MS_ICCLR_1_ICCLR_1_SET 0x00000001
352 #define MS_ICCLR_1_ICCLR_1_CLR 0xfffffffe
353 #define MS_ICCLR_1_ICCLR_1_MSB 0
354 #define MS_ICCLR_1_ICCLR_1_LSB 0
355 #define MS_MBOX_0 HW_REGISTER_RW( 0x7e0000a0 )
356 #define MS_MBOX_0_MASK 0xffffffff
357 #define MS_MBOX_0_WIDTH 32
358 #define MS_MBOX_0_RESET 0000000000
359 #define MS_MBOX_0_MBOX_BITS 31:0
360 #define MS_MBOX_0_MBOX_SET 0xffffffff
361 #define MS_MBOX_0_MBOX_CLR 0x00000000
362 #define MS_MBOX_0_MBOX_MSB 31
363 #define MS_MBOX_0_MBOX_LSB 0
364 #define MS_MBOX_1 HW_REGISTER_RW( 0x7e0000a4 )
365 #define MS_MBOX_1_MASK 0xffffffff
366 #define MS_MBOX_1_WIDTH 32
367 #define MS_MBOX_1_RESET 0000000000
368 #define MS_MBOX_1_MBOX_BITS 31:0
369 #define MS_MBOX_1_MBOX_SET 0xffffffff
370 #define MS_MBOX_1_MBOX_CLR 0x00000000
371 #define MS_MBOX_1_MBOX_MSB 31
372 #define MS_MBOX_1_MBOX_LSB 0
373 #define MS_MBOX_2 HW_REGISTER_RW( 0x7e0000a8 )
374 #define MS_MBOX_2_MASK 0xffffffff
375 #define MS_MBOX_2_WIDTH 32
376 #define MS_MBOX_2_RESET 0000000000
377 #define MS_MBOX_2_MBOX_BITS 31:0
378 #define MS_MBOX_2_MBOX_SET 0xffffffff
379 #define MS_MBOX_2_MBOX_CLR 0x00000000
380 #define MS_MBOX_2_MBOX_MSB 31
381 #define MS_MBOX_2_MBOX_LSB 0
382 #define MS_MBOX_3 HW_REGISTER_RW( 0x7e0000ac )
383 #define MS_MBOX_3_MASK 0xffffffff
384 #define MS_MBOX_3_WIDTH 32
385 #define MS_MBOX_3_RESET 0000000000
386 #define MS_MBOX_3_MBOX_BITS 31:0
387 #define MS_MBOX_3_MBOX_SET 0xffffffff
388 #define MS_MBOX_3_MBOX_CLR 0x00000000
389 #define MS_MBOX_3_MBOX_MSB 31
390 #define MS_MBOX_3_MBOX_LSB 0
391 #define MS_MBOX_4 HW_REGISTER_RW( 0x7e0000b0 )
392 #define MS_MBOX_4_MASK 0xffffffff
393 #define MS_MBOX_4_WIDTH 32
394 #define MS_MBOX_4_RESET 0000000000
395 #define MS_MBOX_4_MBOX_BITS 31:0
396 #define MS_MBOX_4_MBOX_SET 0xffffffff
397 #define MS_MBOX_4_MBOX_CLR 0x00000000
398 #define MS_MBOX_4_MBOX_MSB 31
399 #define MS_MBOX_4_MBOX_LSB 0
400 #define MS_MBOX_5 HW_REGISTER_RW( 0x7e0000b4 )
401 #define MS_MBOX_5_MASK 0xffffffff
402 #define MS_MBOX_5_WIDTH 32
403 #define MS_MBOX_5_RESET 0000000000
404 #define MS_MBOX_5_MBOX_BITS 31:0
405 #define MS_MBOX_5_MBOX_SET 0xffffffff
406 #define MS_MBOX_5_MBOX_CLR 0x00000000
407 #define MS_MBOX_5_MBOX_MSB 31
408 #define MS_MBOX_5_MBOX_LSB 0
409 #define MS_MBOX_6 HW_REGISTER_RW( 0x7e0000b8 )
410 #define MS_MBOX_6_MASK 0xffffffff
411 #define MS_MBOX_6_WIDTH 32
412 #define MS_MBOX_6_RESET 0000000000
413 #define MS_MBOX_6_MBOX_BITS 31:0
414 #define MS_MBOX_6_MBOX_SET 0xffffffff
415 #define MS_MBOX_6_MBOX_CLR 0x00000000
416 #define MS_MBOX_6_MBOX_MSB 31
417 #define MS_MBOX_6_MBOX_LSB 0
418 #define MS_MBOX_7 HW_REGISTER_RW( 0x7e0000bc )
419 #define MS_MBOX_7_MASK 0xffffffff
420 #define MS_MBOX_7_WIDTH 32
421 #define MS_MBOX_7_RESET 0000000000
422 #define MS_MBOX_7_MBOX_BITS 31:0
423 #define MS_MBOX_7_MBOX_SET 0xffffffff
424 #define MS_MBOX_7_MBOX_CLR 0x00000000
425 #define MS_MBOX_7_MBOX_MSB 31
426 #define MS_MBOX_7_MBOX_LSB 0
427 #define MS_VPUSEMA_0 HW_REGISTER_RW( 0x7e0000c0 )
428 #define MS_VPUSEMA_0_VPUSEMA_0_BITS 0:0
429 #define MS_VPUSEMA_0_VPUSEMA_0_SET 0x00000001
430 #define MS_VPUSEMA_0_VPUSEMA_0_CLR 0xfffffffe
431 #define MS_VPUSEMA_0_VPUSEMA_0_MSB 0
432 #define MS_VPUSEMA_0_VPUSEMA_0_LSB 0
433 #define MS_VPUSEMA_1 HW_REGISTER_RW( 0x7e0000c4 )
434 #define MS_VPUSEMA_1_VPUSEMA_1_BITS 0:0
435 #define MS_VPUSEMA_1_VPUSEMA_1_SET 0x00000001
436 #define MS_VPUSEMA_1_VPUSEMA_1_CLR 0xfffffffe
437 #define MS_VPUSEMA_1_VPUSEMA_1_MSB 0
438 #define MS_VPUSEMA_1_VPUSEMA_1_LSB 0
439 #define MS_VPU_STAT HW_REGISTER_RO( 0x7e0000c8 )
440 #define MS_VPU_STAT_MASK 0x00ff00ff
441 #define MS_VPU_STAT_WIDTH 24
442 #define MS_VPU_STAT_VPU_STAT_BITS 0:0
443 #define MS_VPU_STAT_VPU_STAT_SET 0x00000001
444 #define MS_VPU_STAT_VPU_STAT_CLR 0xfffffffe
445 #define MS_VPU_STAT_VPU_STAT_MSB 0
446 #define MS_VPU_STAT_VPU_STAT_LSB 0
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