Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / pcm.h
1 // This file was generated by the create_regs script
2 #define PCM_BASE 0x7e203000
3 #define PCM_CS_A HW_REGISTER_RW( 0x7e203000 )
4 #define PCM_CS_A_MASK 0x03ffe3ff
5 #define PCM_CS_A_WIDTH 26
6 #define PCM_CS_A_RESET 0000000000
7 #define PCM_CS_A_STBY_BITS 25:25
8 #define PCM_CS_A_STBY_SET 0x02000000
9 #define PCM_CS_A_STBY_CLR 0xfdffffff
10 #define PCM_CS_A_STBY_MSB 25
11 #define PCM_CS_A_STBY_LSB 25
12 #define PCM_CS_A_SYNC_BITS 24:24
13 #define PCM_CS_A_SYNC_SET 0x01000000
14 #define PCM_CS_A_SYNC_CLR 0xfeffffff
15 #define PCM_CS_A_SYNC_MSB 24
16 #define PCM_CS_A_SYNC_LSB 24
17 #define PCM_CS_A_RXSEX_BITS 23:23
18 #define PCM_CS_A_RXSEX_SET 0x00800000
19 #define PCM_CS_A_RXSEX_CLR 0xff7fffff
20 #define PCM_CS_A_RXSEX_MSB 23
21 #define PCM_CS_A_RXSEX_LSB 23
22 #define PCM_CS_A_RXF_BITS 22:22
23 #define PCM_CS_A_RXF_SET 0x00400000
24 #define PCM_CS_A_RXF_CLR 0xffbfffff
25 #define PCM_CS_A_RXF_MSB 22
26 #define PCM_CS_A_RXF_LSB 22
27 #define PCM_CS_A_TXE_BITS 21:21
28 #define PCM_CS_A_TXE_SET 0x00200000
29 #define PCM_CS_A_TXE_CLR 0xffdfffff
30 #define PCM_CS_A_TXE_MSB 21
31 #define PCM_CS_A_TXE_LSB 21
32 #define PCM_CS_A_RXD_BITS 20:20
33 #define PCM_CS_A_RXD_SET 0x00100000
34 #define PCM_CS_A_RXD_CLR 0xffefffff
35 #define PCM_CS_A_RXD_MSB 20
36 #define PCM_CS_A_RXD_LSB 20
37 #define PCM_CS_A_TXD_BITS 19:19
38 #define PCM_CS_A_TXD_SET 0x00080000
39 #define PCM_CS_A_TXD_CLR 0xfff7ffff
40 #define PCM_CS_A_TXD_MSB 19
41 #define PCM_CS_A_TXD_LSB 19
42 #define PCM_CS_A_RXR_BITS 18:18
43 #define PCM_CS_A_RXR_SET 0x00040000
44 #define PCM_CS_A_RXR_CLR 0xfffbffff
45 #define PCM_CS_A_RXR_MSB 18
46 #define PCM_CS_A_RXR_LSB 18
47 #define PCM_CS_A_TXW_BITS 17:17
48 #define PCM_CS_A_TXW_SET 0x00020000
49 #define PCM_CS_A_TXW_CLR 0xfffdffff
50 #define PCM_CS_A_TXW_MSB 17
51 #define PCM_CS_A_TXW_LSB 17
52 #define PCM_CS_A_RXERR_BITS 16:16
53 #define PCM_CS_A_RXERR_SET 0x00010000
54 #define PCM_CS_A_RXERR_CLR 0xfffeffff
55 #define PCM_CS_A_RXERR_MSB 16
56 #define PCM_CS_A_RXERR_LSB 16
57 #define PCM_CS_A_TXERR_BITS 15:15
58 #define PCM_CS_A_TXERR_SET 0x00008000
59 #define PCM_CS_A_TXERR_CLR 0xffff7fff
60 #define PCM_CS_A_TXERR_MSB 15
61 #define PCM_CS_A_TXERR_LSB 15
62 #define PCM_CS_A_RXSYNC_BITS 14:14
63 #define PCM_CS_A_RXSYNC_SET 0x00004000
64 #define PCM_CS_A_RXSYNC_CLR 0xffffbfff
65 #define PCM_CS_A_RXSYNC_MSB 14
66 #define PCM_CS_A_RXSYNC_LSB 14
67 #define PCM_CS_A_TXSYNC_BITS 13:13
68 #define PCM_CS_A_TXSYNC_SET 0x00002000
69 #define PCM_CS_A_TXSYNC_CLR 0xffffdfff
70 #define PCM_CS_A_TXSYNC_MSB 13
71 #define PCM_CS_A_TXSYNC_LSB 13
72 #define PCM_CS_A_DMAEN_BITS 9:9
73 #define PCM_CS_A_DMAEN_SET 0x00000200
74 #define PCM_CS_A_DMAEN_CLR 0xfffffdff
75 #define PCM_CS_A_DMAEN_MSB 9
76 #define PCM_CS_A_DMAEN_LSB 9
77 #define PCM_CS_A_RXTHR_BITS 8:7
78 #define PCM_CS_A_RXTHR_SET 0x00000180
79 #define PCM_CS_A_RXTHR_CLR 0xfffffe7f
80 #define PCM_CS_A_RXTHR_MSB 8
81 #define PCM_CS_A_RXTHR_LSB 7
82 #define PCM_CS_A_TXTHR_BITS 6:5
83 #define PCM_CS_A_TXTHR_SET 0x00000060
84 #define PCM_CS_A_TXTHR_CLR 0xffffff9f
85 #define PCM_CS_A_TXTHR_MSB 6
86 #define PCM_CS_A_TXTHR_LSB 5
87 #define PCM_CS_A_RXCLR_BITS 4:4
88 #define PCM_CS_A_RXCLR_SET 0x00000010
89 #define PCM_CS_A_RXCLR_CLR 0xffffffef
90 #define PCM_CS_A_RXCLR_MSB 4
91 #define PCM_CS_A_RXCLR_LSB 4
92 #define PCM_CS_A_TXCLR_BITS 3:3
93 #define PCM_CS_A_TXCLR_SET 0x00000008
94 #define PCM_CS_A_TXCLR_CLR 0xfffffff7
95 #define PCM_CS_A_TXCLR_MSB 3
96 #define PCM_CS_A_TXCLR_LSB 3
97 #define PCM_CS_A_TXON_BITS 2:2
98 #define PCM_CS_A_TXON_SET 0x00000004
99 #define PCM_CS_A_TXON_CLR 0xfffffffb
100 #define PCM_CS_A_TXON_MSB 2
101 #define PCM_CS_A_TXON_LSB 2
102 #define PCM_CS_A_RXON_BITS 1:1
103 #define PCM_CS_A_RXON_SET 0x00000002
104 #define PCM_CS_A_RXON_CLR 0xfffffffd
105 #define PCM_CS_A_RXON_MSB 1
106 #define PCM_CS_A_RXON_LSB 1
107 #define PCM_CS_A_EN_BITS 0:0
108 #define PCM_CS_A_EN_SET 0x00000001
109 #define PCM_CS_A_EN_CLR 0xfffffffe
110 #define PCM_CS_A_EN_MSB 0
111 #define PCM_CS_A_EN_LSB 0
112 #define PCM_FIFO_A HW_REGISTER_RW( 0x7e203004 )
113 #define PCM_FIFO_A_MASK 0xffffffff
114 #define PCM_FIFO_A_WIDTH 32
115 #define PCM_MODE_A HW_REGISTER_RW( 0x7e203008 )
116 #define PCM_MODE_A_MASK 0x1fffffff
117 #define PCM_MODE_A_WIDTH 29
118 #define PCM_MODE_A_RESET 0000000000
119 #define PCM_MODE_A_CLK_DIS_BITS 28:28
120 #define PCM_MODE_A_CLK_DIS_SET 0x10000000
121 #define PCM_MODE_A_CLK_DIS_CLR 0xefffffff
122 #define PCM_MODE_A_CLK_DIS_MSB 28
123 #define PCM_MODE_A_CLK_DIS_LSB 28
124 #define PCM_MODE_A_PDMN_BITS 27:27
125 #define PCM_MODE_A_PDMN_SET 0x08000000
126 #define PCM_MODE_A_PDMN_CLR 0xf7ffffff
127 #define PCM_MODE_A_PDMN_MSB 27
128 #define PCM_MODE_A_PDMN_LSB 27
129 #define PCM_MODE_A_PDME_BITS 26:26
130 #define PCM_MODE_A_PDME_SET 0x04000000
131 #define PCM_MODE_A_PDME_CLR 0xfbffffff
132 #define PCM_MODE_A_PDME_MSB 26
133 #define PCM_MODE_A_PDME_LSB 26
134 #define PCM_MODE_A_FRXP_BITS 25:25
135 #define PCM_MODE_A_FRXP_SET 0x02000000
136 #define PCM_MODE_A_FRXP_CLR 0xfdffffff
137 #define PCM_MODE_A_FRXP_MSB 25
138 #define PCM_MODE_A_FRXP_LSB 25
139 #define PCM_MODE_A_FTXP_BITS 24:24
140 #define PCM_MODE_A_FTXP_SET 0x01000000
141 #define PCM_MODE_A_FTXP_CLR 0xfeffffff
142 #define PCM_MODE_A_FTXP_MSB 24
143 #define PCM_MODE_A_FTXP_LSB 24
144 #define PCM_MODE_A_CLKM_BITS 23:23
145 #define PCM_MODE_A_CLKM_SET 0x00800000
146 #define PCM_MODE_A_CLKM_CLR 0xff7fffff
147 #define PCM_MODE_A_CLKM_MSB 23
148 #define PCM_MODE_A_CLKM_LSB 23
149 #define PCM_MODE_A_CLKI_BITS 22:22
150 #define PCM_MODE_A_CLKI_SET 0x00400000
151 #define PCM_MODE_A_CLKI_CLR 0xffbfffff
152 #define PCM_MODE_A_CLKI_MSB 22
153 #define PCM_MODE_A_CLKI_LSB 22
154 #define PCM_MODE_A_FSM_BITS 21:21
155 #define PCM_MODE_A_FSM_SET 0x00200000
156 #define PCM_MODE_A_FSM_CLR 0xffdfffff
157 #define PCM_MODE_A_FSM_MSB 21
158 #define PCM_MODE_A_FSM_LSB 21
159 #define PCM_MODE_A_FSI_BITS 20:20
160 #define PCM_MODE_A_FSI_SET 0x00100000
161 #define PCM_MODE_A_FSI_CLR 0xffefffff
162 #define PCM_MODE_A_FSI_MSB 20
163 #define PCM_MODE_A_FSI_LSB 20
164 #define PCM_MODE_A_FLEN_BITS 19:10
165 #define PCM_MODE_A_FLEN_SET 0x000ffc00
166 #define PCM_MODE_A_FLEN_CLR 0xfff003ff
167 #define PCM_MODE_A_FLEN_MSB 19
168 #define PCM_MODE_A_FLEN_LSB 10
169 #define PCM_MODE_A_FSLEN_BITS 9:0
170 #define PCM_MODE_A_FSLEN_SET 0x000003ff
171 #define PCM_MODE_A_FSLEN_CLR 0xfffffc00
172 #define PCM_MODE_A_FSLEN_MSB 9
173 #define PCM_MODE_A_FSLEN_LSB 0
174 #define PCM_RXC_A HW_REGISTER_RW( 0x7e20300c )
175 #define PCM_RXC_A_MASK 0xffffffff
176 #define PCM_RXC_A_WIDTH 32
177 #define PCM_RXC_A_RESET 0000000000
178 #define PCM_RXC_A_CH1WEX_BITS 31:31
179 #define PCM_RXC_A_CH1WEX_SET 0x80000000
180 #define PCM_RXC_A_CH1WEX_CLR 0x7fffffff
181 #define PCM_RXC_A_CH1WEX_MSB 31
182 #define PCM_RXC_A_CH1WEX_LSB 31
183 #define PCM_RXC_A_CH1EN_BITS 30:30
184 #define PCM_RXC_A_CH1EN_SET 0x40000000
185 #define PCM_RXC_A_CH1EN_CLR 0xbfffffff
186 #define PCM_RXC_A_CH1EN_MSB 30
187 #define PCM_RXC_A_CH1EN_LSB 30
188 #define PCM_RXC_A_CH1POS_BITS 29:20
189 #define PCM_RXC_A_CH1POS_SET 0x3ff00000
190 #define PCM_RXC_A_CH1POS_CLR 0xc00fffff
191 #define PCM_RXC_A_CH1POS_MSB 29
192 #define PCM_RXC_A_CH1POS_LSB 20
193 #define PCM_RXC_A_CH1WID_BITS 19:16
194 #define PCM_RXC_A_CH1WID_SET 0x000f0000
195 #define PCM_RXC_A_CH1WID_CLR 0xfff0ffff
196 #define PCM_RXC_A_CH1WID_MSB 19
197 #define PCM_RXC_A_CH1WID_LSB 16
198 #define PCM_RXC_A_CH2WEX_BITS 15:15
199 #define PCM_RXC_A_CH2WEX_SET 0x00008000
200 #define PCM_RXC_A_CH2WEX_CLR 0xffff7fff
201 #define PCM_RXC_A_CH2WEX_MSB 15
202 #define PCM_RXC_A_CH2WEX_LSB 15
203 #define PCM_RXC_A_CH2EN_BITS 14:14
204 #define PCM_RXC_A_CH2EN_SET 0x00004000
205 #define PCM_RXC_A_CH2EN_CLR 0xffffbfff
206 #define PCM_RXC_A_CH2EN_MSB 14
207 #define PCM_RXC_A_CH2EN_LSB 14
208 #define PCM_RXC_A_CH2POS_BITS 13:4
209 #define PCM_RXC_A_CH2POS_SET 0x00003ff0
210 #define PCM_RXC_A_CH2POS_CLR 0xffffc00f
211 #define PCM_RXC_A_CH2POS_MSB 13
212 #define PCM_RXC_A_CH2POS_LSB 4
213 #define PCM_RXC_A_CH2WID_BITS 3:0
214 #define PCM_RXC_A_CH2WID_SET 0x0000000f
215 #define PCM_RXC_A_CH2WID_CLR 0xfffffff0
216 #define PCM_RXC_A_CH2WID_MSB 3
217 #define PCM_RXC_A_CH2WID_LSB 0
218 #define PCM_TXC_A HW_REGISTER_RW( 0x7e203010 )
219 #define PCM_TXC_A_MASK 0xffffffff
220 #define PCM_TXC_A_WIDTH 32
221 #define PCM_TXC_A_RESET 0000000000
222 #define PCM_TXC_A_CH1WEX_BITS 31:31
223 #define PCM_TXC_A_CH1WEX_SET 0x80000000
224 #define PCM_TXC_A_CH1WEX_CLR 0x7fffffff
225 #define PCM_TXC_A_CH1WEX_MSB 31
226 #define PCM_TXC_A_CH1WEX_LSB 31
227 #define PCM_TXC_A_CH1EN_BITS 30:30
228 #define PCM_TXC_A_CH1EN_SET 0x40000000
229 #define PCM_TXC_A_CH1EN_CLR 0xbfffffff
230 #define PCM_TXC_A_CH1EN_MSB 30
231 #define PCM_TXC_A_CH1EN_LSB 30
232 #define PCM_TXC_A_CH1POS_BITS 29:20
233 #define PCM_TXC_A_CH1POS_SET 0x3ff00000
234 #define PCM_TXC_A_CH1POS_CLR 0xc00fffff
235 #define PCM_TXC_A_CH1POS_MSB 29
236 #define PCM_TXC_A_CH1POS_LSB 20
237 #define PCM_TXC_A_CH1WID_BITS 19:16
238 #define PCM_TXC_A_CH1WID_SET 0x000f0000
239 #define PCM_TXC_A_CH1WID_CLR 0xfff0ffff
240 #define PCM_TXC_A_CH1WID_MSB 19
241 #define PCM_TXC_A_CH1WID_LSB 16
242 #define PCM_TXC_A_CH2WEX_BITS 15:15
243 #define PCM_TXC_A_CH2WEX_SET 0x00008000
244 #define PCM_TXC_A_CH2WEX_CLR 0xffff7fff
245 #define PCM_TXC_A_CH2WEX_MSB 15
246 #define PCM_TXC_A_CH2WEX_LSB 15
247 #define PCM_TXC_A_CH2EN_BITS 14:14
248 #define PCM_TXC_A_CH2EN_SET 0x00004000
249 #define PCM_TXC_A_CH2EN_CLR 0xffffbfff
250 #define PCM_TXC_A_CH2EN_MSB 14
251 #define PCM_TXC_A_CH2EN_LSB 14
252 #define PCM_TXC_A_CH2POS_BITS 13:4
253 #define PCM_TXC_A_CH2POS_SET 0x00003ff0
254 #define PCM_TXC_A_CH2POS_CLR 0xffffc00f
255 #define PCM_TXC_A_CH2POS_MSB 13
256 #define PCM_TXC_A_CH2POS_LSB 4
257 #define PCM_TXC_A_CH2WID_BITS 3:0
258 #define PCM_TXC_A_CH2WID_SET 0x0000000f
259 #define PCM_TXC_A_CH2WID_CLR 0xfffffff0
260 #define PCM_TXC_A_CH2WID_MSB 3
261 #define PCM_TXC_A_CH2WID_LSB 0
262 #define PCM_DREQ_A HW_REGISTER_RW( 0x7e203014 )
263 #define PCM_DREQ_A_MASK 0x7f7f7f7f
264 #define PCM_DREQ_A_WIDTH 31
265 #define PCM_DREQ_A_RESET 0x10303020
266 #define PCM_DREQ_A_TX_PANIC_BITS 30:24
267 #define PCM_DREQ_A_TX_PANIC_SET 0x7f000000
268 #define PCM_DREQ_A_TX_PANIC_CLR 0x80ffffff
269 #define PCM_DREQ_A_TX_PANIC_MSB 30
270 #define PCM_DREQ_A_TX_PANIC_LSB 24
271 #define PCM_DREQ_A_RX_PANIC_BITS 22:16
272 #define PCM_DREQ_A_RX_PANIC_SET 0x007f0000
273 #define PCM_DREQ_A_RX_PANIC_CLR 0xff80ffff
274 #define PCM_DREQ_A_RX_PANIC_MSB 22
275 #define PCM_DREQ_A_RX_PANIC_LSB 16
276 #define PCM_DREQ_A_TX_BITS 14:8
277 #define PCM_DREQ_A_TX_SET 0x00007f00
278 #define PCM_DREQ_A_TX_CLR 0xffff80ff
279 #define PCM_DREQ_A_TX_MSB 14
280 #define PCM_DREQ_A_TX_LSB 8
281 #define PCM_DREQ_A_RX_BITS 6:0
282 #define PCM_DREQ_A_RX_SET 0x0000007f
283 #define PCM_DREQ_A_RX_CLR 0xffffff80
284 #define PCM_DREQ_A_RX_MSB 6
285 #define PCM_DREQ_A_RX_LSB 0
286 #define PCM_INTEN_A HW_REGISTER_RW( 0x7e203018 )
287 #define PCM_INTEN_A_MASK 0x0000000f
288 #define PCM_INTEN_A_WIDTH 4
289 #define PCM_INTEN_A_RESET 0000000000
290 #define PCM_INTEN_A_RXERR_BITS 3:3
291 #define PCM_INTEN_A_RXERR_SET 0x00000008
292 #define PCM_INTEN_A_RXERR_CLR 0xfffffff7
293 #define PCM_INTEN_A_RXERR_MSB 3
294 #define PCM_INTEN_A_RXERR_LSB 3
295 #define PCM_INTEN_A_TXERR_BITS 2:2
296 #define PCM_INTEN_A_TXERR_SET 0x00000004
297 #define PCM_INTEN_A_TXERR_CLR 0xfffffffb
298 #define PCM_INTEN_A_TXERR_MSB 2
299 #define PCM_INTEN_A_TXERR_LSB 2
300 #define PCM_INTEN_A_RXR_BITS 1:1
301 #define PCM_INTEN_A_RXR_SET 0x00000002
302 #define PCM_INTEN_A_RXR_CLR 0xfffffffd
303 #define PCM_INTEN_A_RXR_MSB 1
304 #define PCM_INTEN_A_RXR_LSB 1
305 #define PCM_INTEN_A_TXW_BITS 0:0
306 #define PCM_INTEN_A_TXW_SET 0x00000001
307 #define PCM_INTEN_A_TXW_CLR 0xfffffffe
308 #define PCM_INTEN_A_TXW_MSB 0
309 #define PCM_INTEN_A_TXW_LSB 0
310 #define PCM_INTSTC_A HW_REGISTER_RW( 0x7e20301c )
311 #define PCM_INTSTC_A_MASK 0x0000000f
312 #define PCM_INTSTC_A_WIDTH 4
313 #define PCM_INTSTC_A_RESET 0000000000
314 #define PCM_INTSTC_A_RXERR_BITS 3:3
315 #define PCM_INTSTC_A_RXERR_SET 0x00000008
316 #define PCM_INTSTC_A_RXERR_CLR 0xfffffff7
317 #define PCM_INTSTC_A_RXERR_MSB 3
318 #define PCM_INTSTC_A_RXERR_LSB 3
319 #define PCM_INTSTC_A_TXERR_BITS 2:2
320 #define PCM_INTSTC_A_TXERR_SET 0x00000004
321 #define PCM_INTSTC_A_TXERR_CLR 0xfffffffb
322 #define PCM_INTSTC_A_TXERR_MSB 2
323 #define PCM_INTSTC_A_TXERR_LSB 2
324 #define PCM_INTSTC_A_RXR_BITS 1:1
325 #define PCM_INTSTC_A_RXR_SET 0x00000002
326 #define PCM_INTSTC_A_RXR_CLR 0xfffffffd
327 #define PCM_INTSTC_A_RXR_MSB 1
328 #define PCM_INTSTC_A_RXR_LSB 1
329 #define PCM_INTSTC_A_TXW_BITS 0:0
330 #define PCM_INTSTC_A_TXW_SET 0x00000001
331 #define PCM_INTSTC_A_TXW_CLR 0xfffffffe
332 #define PCM_INTSTC_A_TXW_MSB 0
333 #define PCM_INTSTC_A_TXW_LSB 0
334 #define PCM_GRAY HW_REGISTER_RW( 0x7e203020 )
335 #define PCM_GRAY_MASK 0x003ffff7
336 #define PCM_GRAY_WIDTH 22
337 #define PCM_GRAY_RESET 0000000000
338 #define PCM_GRAY_RXFIFOLEVEL_BITS 21:16
339 #define PCM_GRAY_RXFIFOLEVEL_SET 0x003f0000
340 #define PCM_GRAY_RXFIFOLEVEL_CLR 0xffc0ffff
341 #define PCM_GRAY_RXFIFOLEVEL_MSB 21
342 #define PCM_GRAY_RXFIFOLEVEL_LSB 16
343 #define PCM_GRAY_FLUSHED_BITS 15:10
344 #define PCM_GRAY_FLUSHED_SET 0x0000fc00
345 #define PCM_GRAY_FLUSHED_CLR 0xffff03ff
346 #define PCM_GRAY_FLUSHED_MSB 15
347 #define PCM_GRAY_FLUSHED_LSB 10
348 #define PCM_GRAY_RXLEVEL_BITS 9:4
349 #define PCM_GRAY_RXLEVEL_SET 0x000003f0
350 #define PCM_GRAY_RXLEVEL_CLR 0xfffffc0f
351 #define PCM_GRAY_RXLEVEL_MSB 9
352 #define PCM_GRAY_RXLEVEL_LSB 4
353 #define PCM_GRAY_FLUSH_BITS 2:2
354 #define PCM_GRAY_FLUSH_SET 0x00000004
355 #define PCM_GRAY_FLUSH_CLR 0xfffffffb
356 #define PCM_GRAY_FLUSH_MSB 2
357 #define PCM_GRAY_FLUSH_LSB 2
358 #define PCM_GRAY_CLR_BITS 1:1
359 #define PCM_GRAY_CLR_SET 0x00000002
360 #define PCM_GRAY_CLR_CLR 0xfffffffd
361 #define PCM_GRAY_CLR_MSB 1
362 #define PCM_GRAY_CLR_LSB 1
363 #define PCM_GRAY_EN_BITS 0:0
364 #define PCM_GRAY_EN_SET 0x00000001
365 #define PCM_GRAY_EN_CLR 0xfffffffe
366 #define PCM_GRAY_EN_MSB 0
367 #define PCM_GRAY_EN_LSB 0
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