Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / pixel_valve0.h
1 // This file was generated by the create_regs script
2 #define PIXELVALVE0_BASE 0x7e206000
3 #define PIXELVALVE0_APB_ID 0x70697876
4 #define PIXELVALVE0_C HW_REGISTER_RW( 0x7e206000 )
5 #define PIXELVALVE0_C_MASK 0x00ffffff
6 #define PIXELVALVE0_C_WIDTH 24
7 #define PIXELVALVE0_VC HW_REGISTER_RW( 0x7e206004 )
8 #define PIXELVALVE0_VC_MASK 0x007fffff
9 #define PIXELVALVE0_VC_WIDTH 23
10 #define PIXELVALVE0_VSYNCD_EVEN HW_REGISTER_RW( 0x7e206008 )
11 #define PIXELVALVE0_VSYNCD_EVEN_MASK 0x0001ffff
12 #define PIXELVALVE0_VSYNCD_EVEN_WIDTH 17
13 #define PIXELVALVE0_HORZA HW_REGISTER_RW( 0x7e20600c )
14 #define PIXELVALVE0_HORZA_MASK 0xffffffff
15 #define PIXELVALVE0_HORZA_WIDTH 32
16 #define PIXELVALVE0_HORZB HW_REGISTER_RW( 0x7e206010 )
17 #define PIXELVALVE0_HORZB_MASK 0xffffffff
18 #define PIXELVALVE0_HORZB_WIDTH 32
19 #define PIXELVALVE0_VERTA HW_REGISTER_RW( 0x7e206014 )
20 #define PIXELVALVE0_VERTA_MASK 0xffffffff
21 #define PIXELVALVE0_VERTA_WIDTH 32
22 #define PIXELVALVE0_VERTB HW_REGISTER_RW( 0x7e206018 )
23 #define PIXELVALVE0_VERTB_MASK 0xffffffff
24 #define PIXELVALVE0_VERTB_WIDTH 32
25 #define PIXELVALVE0_VERTA_EVEN HW_REGISTER_RW( 0x7e20601c )
26 #define PIXELVALVE0_VERTA_EVEN_MASK 0xffffffff
27 #define PIXELVALVE0_VERTA_EVEN_WIDTH 32
28 #define PIXELVALVE0_VERTB_EVEN HW_REGISTER_RW( 0x7e206020 )
29 #define PIXELVALVE0_VERTB_EVEN_MASK 0xffffffff
30 #define PIXELVALVE0_VERTB_EVEN_WIDTH 32
31 #define PIXELVALVE0_INTEN HW_REGISTER_RW( 0x7e206024 )
32 #define PIXELVALVE0_INTEN_MASK 0x000003ff
33 #define PIXELVALVE0_INTEN_WIDTH 10
34 #define PIXELVALVE0_INTSTAT HW_REGISTER_RW( 0x7e206028 )
35 #define PIXELVALVE0_INTSTAT_MASK 0x000003ff
36 #define PIXELVALVE0_INTSTAT_WIDTH 10
37 #define PIXELVALVE0_STAT HW_REGISTER_RW( 0x7e20602c )
38 #define PIXELVALVE0_STAT_MASK 0x000003ff
39 #define PIXELVALVE0_STAT_WIDTH 10
40 #define PIXELVALVE0_DSI_HACT_ACT HW_REGISTER_RW( 0x7e206030 )
41 #define PIXELVALVE0_DSI_HACT_ACT_MASK 0x0000ffff
42 #define PIXELVALVE0_DSI_HACT_ACT_WIDTH 16
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