Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / pwm.h
1 // This file was generated by the create_regs script
2 #define PWM_BASE 0x7e20c000
3 #define PWM_APB_ID 0x70776d30
4 #define PWM_CTL HW_REGISTER_RW( 0x7e20c000 )
5 #define PWM_CTL_MASK 0xbfbfbfff
6 #define PWM_CTL_WIDTH 32
7 #define PWM_CTL_RESET 0000000000
8 #define PWM_CTL_PWEN1_BITS 0:0
9 #define PWM_CTL_PWEN1_SET 0x00000001
10 #define PWM_CTL_PWEN1_CLR 0xfffffffe
11 #define PWM_CTL_PWEN1_MSB 0
12 #define PWM_CTL_PWEN1_LSB 0
13 #define PWM_CTL_MODE1_BITS 1:1
14 #define PWM_CTL_MODE1_SET 0x00000002
15 #define PWM_CTL_MODE1_CLR 0xfffffffd
16 #define PWM_CTL_MODE1_MSB 1
17 #define PWM_CTL_MODE1_LSB 1
18 #define PWM_CTL_RPTL1_BITS 2:2
19 #define PWM_CTL_RPTL1_SET 0x00000004
20 #define PWM_CTL_RPTL1_CLR 0xfffffffb
21 #define PWM_CTL_RPTL1_MSB 2
22 #define PWM_CTL_RPTL1_LSB 2
23 #define PWM_CTL_SBIT1_BITS 3:3
24 #define PWM_CTL_SBIT1_SET 0x00000008
25 #define PWM_CTL_SBIT1_CLR 0xfffffff7
26 #define PWM_CTL_SBIT1_MSB 3
27 #define PWM_CTL_SBIT1_LSB 3
28 #define PWM_CTL_POLA1_BITS 4:4
29 #define PWM_CTL_POLA1_SET 0x00000010
30 #define PWM_CTL_POLA1_CLR 0xffffffef
31 #define PWM_CTL_POLA1_MSB 4
32 #define PWM_CTL_POLA1_LSB 4
33 #define PWM_CTL_USEF1_BITS 5:5
34 #define PWM_CTL_USEF1_SET 0x00000020
35 #define PWM_CTL_USEF1_CLR 0xffffffdf
36 #define PWM_CTL_USEF1_MSB 5
37 #define PWM_CTL_USEF1_LSB 5
38 #define PWM_CTL_CLRF1_BITS 6:6
39 #define PWM_CTL_CLRF1_SET 0x00000040
40 #define PWM_CTL_CLRF1_CLR 0xffffffbf
41 #define PWM_CTL_CLRF1_MSB 6
42 #define PWM_CTL_CLRF1_LSB 6
43 #define PWM_CTL_MSEN1_BITS 7:7
44 #define PWM_CTL_MSEN1_SET 0x00000080
45 #define PWM_CTL_MSEN1_CLR 0xffffff7f
46 #define PWM_CTL_MSEN1_MSB 7
47 #define PWM_CTL_MSEN1_LSB 7
48 #define PWM_CTL_PWEN2_BITS 8:8
49 #define PWM_CTL_PWEN2_SET 0x00000100
50 #define PWM_CTL_PWEN2_CLR 0xfffffeff
51 #define PWM_CTL_PWEN2_MSB 8
52 #define PWM_CTL_PWEN2_LSB 8
53 #define PWM_CTL_MODE2_BITS 9:9
54 #define PWM_CTL_MODE2_SET 0x00000200
55 #define PWM_CTL_MODE2_CLR 0xfffffdff
56 #define PWM_CTL_MODE2_MSB 9
57 #define PWM_CTL_MODE2_LSB 9
58 #define PWM_CTL_RPTL2_BITS 10:10
59 #define PWM_CTL_RPTL2_SET 0x00000400
60 #define PWM_CTL_RPTL2_CLR 0xfffffbff
61 #define PWM_CTL_RPTL2_MSB 10
62 #define PWM_CTL_RPTL2_LSB 10
63 #define PWM_CTL_SBIT2_BITS 11:11
64 #define PWM_CTL_SBIT2_SET 0x00000800
65 #define PWM_CTL_SBIT2_CLR 0xfffff7ff
66 #define PWM_CTL_SBIT2_MSB 11
67 #define PWM_CTL_SBIT2_LSB 11
68 #define PWM_CTL_POLA2_BITS 12:12
69 #define PWM_CTL_POLA2_SET 0x00001000
70 #define PWM_CTL_POLA2_CLR 0xffffefff
71 #define PWM_CTL_POLA2_MSB 12
72 #define PWM_CTL_POLA2_LSB 12
73 #define PWM_CTL_USEF2_BITS 13:13
74 #define PWM_CTL_USEF2_SET 0x00002000
75 #define PWM_CTL_USEF2_CLR 0xffffdfff
76 #define PWM_CTL_USEF2_MSB 13
77 #define PWM_CTL_USEF2_LSB 13
78 #define PWM_CTL_MSEN2_BITS 15:15
79 #define PWM_CTL_MSEN2_SET 0x00008000
80 #define PWM_CTL_MSEN2_CLR 0xffff7fff
81 #define PWM_CTL_MSEN2_MSB 15
82 #define PWM_CTL_MSEN2_LSB 15
83 #define PWM_CTL_PWEN3_BITS 16:16
84 #define PWM_CTL_PWEN3_SET 0x00010000
85 #define PWM_CTL_PWEN3_CLR 0xfffeffff
86 #define PWM_CTL_PWEN3_MSB 16
87 #define PWM_CTL_PWEN3_LSB 16
88 #define PWM_CTL_MODE3_BITS 17:17
89 #define PWM_CTL_MODE3_SET 0x00020000
90 #define PWM_CTL_MODE3_CLR 0xfffdffff
91 #define PWM_CTL_MODE3_MSB 17
92 #define PWM_CTL_MODE3_LSB 17
93 #define PWM_CTL_RPTL3_BITS 18:18
94 #define PWM_CTL_RPTL3_SET 0x00040000
95 #define PWM_CTL_RPTL3_CLR 0xfffbffff
96 #define PWM_CTL_RPTL3_MSB 18
97 #define PWM_CTL_RPTL3_LSB 18
98 #define PWM_CTL_SBIT3_BITS 19:19
99 #define PWM_CTL_SBIT3_SET 0x00080000
100 #define PWM_CTL_SBIT3_CLR 0xfff7ffff
101 #define PWM_CTL_SBIT3_MSB 19
102 #define PWM_CTL_SBIT3_LSB 19
103 #define PWM_CTL_POLA3_BITS 20:20
104 #define PWM_CTL_POLA3_SET 0x00100000
105 #define PWM_CTL_POLA3_CLR 0xffefffff
106 #define PWM_CTL_POLA3_MSB 20
107 #define PWM_CTL_POLA3_LSB 20
108 #define PWM_CTL_USEF3_BITS 21:21
109 #define PWM_CTL_USEF3_SET 0x00200000
110 #define PWM_CTL_USEF3_CLR 0xffdfffff
111 #define PWM_CTL_USEF3_MSB 21
112 #define PWM_CTL_USEF3_LSB 21
113 #define PWM_CTL_MSEN3_BITS 23:23
114 #define PWM_CTL_MSEN3_SET 0x00800000
115 #define PWM_CTL_MSEN3_CLR 0xff7fffff
116 #define PWM_CTL_MSEN3_MSB 23
117 #define PWM_CTL_MSEN3_LSB 23
118 #define PWM_CTL_PWEN4_BITS 24:24
119 #define PWM_CTL_PWEN4_SET 0x01000000
120 #define PWM_CTL_PWEN4_CLR 0xfeffffff
121 #define PWM_CTL_PWEN4_MSB 24
122 #define PWM_CTL_PWEN4_LSB 24
123 #define PWM_CTL_MODE4_BITS 25:25
124 #define PWM_CTL_MODE4_SET 0x02000000
125 #define PWM_CTL_MODE4_CLR 0xfdffffff
126 #define PWM_CTL_MODE4_MSB 25
127 #define PWM_CTL_MODE4_LSB 25
128 #define PWM_CTL_RPTL4_BITS 26:26
129 #define PWM_CTL_RPTL4_SET 0x04000000
130 #define PWM_CTL_RPTL4_CLR 0xfbffffff
131 #define PWM_CTL_RPTL4_MSB 26
132 #define PWM_CTL_RPTL4_LSB 26
133 #define PWM_CTL_SBIT4_BITS 27:27
134 #define PWM_CTL_SBIT4_SET 0x08000000
135 #define PWM_CTL_SBIT4_CLR 0xf7ffffff
136 #define PWM_CTL_SBIT4_MSB 27
137 #define PWM_CTL_SBIT4_LSB 27
138 #define PWM_CTL_POLA4_BITS 28:28
139 #define PWM_CTL_POLA4_SET 0x10000000
140 #define PWM_CTL_POLA4_CLR 0xefffffff
141 #define PWM_CTL_POLA4_MSB 28
142 #define PWM_CTL_POLA4_LSB 28
143 #define PWM_CTL_USEF4_BITS 29:29
144 #define PWM_CTL_USEF4_SET 0x20000000
145 #define PWM_CTL_USEF4_CLR 0xdfffffff
146 #define PWM_CTL_USEF4_MSB 29
147 #define PWM_CTL_USEF4_LSB 29
148 #define PWM_CTL_MSEN4_BITS 31:31
149 #define PWM_CTL_MSEN4_SET 0x80000000
150 #define PWM_CTL_MSEN4_CLR 0x7fffffff
151 #define PWM_CTL_MSEN4_MSB 31
152 #define PWM_CTL_MSEN4_LSB 31
153 #define PWM_STA HW_REGISTER_RW( 0x7e20c004 )
154 #define PWM_STA_MASK 0x00001fff
155 #define PWM_STA_WIDTH 13
156 #define PWM_STA_RESET 0000000000
157 #define PWM_STA_FULL1_BITS 0:0
158 #define PWM_STA_FULL1_SET 0x00000001
159 #define PWM_STA_FULL1_CLR 0xfffffffe
160 #define PWM_STA_FULL1_MSB 0
161 #define PWM_STA_FULL1_LSB 0
162 #define PWM_STA_EMPT1_BITS 1:1
163 #define PWM_STA_EMPT1_SET 0x00000002
164 #define PWM_STA_EMPT1_CLR 0xfffffffd
165 #define PWM_STA_EMPT1_MSB 1
166 #define PWM_STA_EMPT1_LSB 1
167 #define PWM_STA_WERR1_BITS 2:2
168 #define PWM_STA_WERR1_SET 0x00000004
169 #define PWM_STA_WERR1_CLR 0xfffffffb
170 #define PWM_STA_WERR1_MSB 2
171 #define PWM_STA_WERR1_LSB 2
172 #define PWM_STA_RERR1_BITS 3:3
173 #define PWM_STA_RERR1_SET 0x00000008
174 #define PWM_STA_RERR1_CLR 0xfffffff7
175 #define PWM_STA_RERR1_MSB 3
176 #define PWM_STA_RERR1_LSB 3
177 #define PWM_STA_GAPO1_BITS 4:4
178 #define PWM_STA_GAPO1_SET 0x00000010
179 #define PWM_STA_GAPO1_CLR 0xffffffef
180 #define PWM_STA_GAPO1_MSB 4
181 #define PWM_STA_GAPO1_LSB 4
182 #define PWM_STA_GAPO2_BITS 5:5
183 #define PWM_STA_GAPO2_SET 0x00000020
184 #define PWM_STA_GAPO2_CLR 0xffffffdf
185 #define PWM_STA_GAPO2_MSB 5
186 #define PWM_STA_GAPO2_LSB 5
187 #define PWM_STA_GAPO3_BITS 6:6
188 #define PWM_STA_GAPO3_SET 0x00000040
189 #define PWM_STA_GAPO3_CLR 0xffffffbf
190 #define PWM_STA_GAPO3_MSB 6
191 #define PWM_STA_GAPO3_LSB 6
192 #define PWM_STA_GAPO4_BITS 7:7
193 #define PWM_STA_GAPO4_SET 0x00000080
194 #define PWM_STA_GAPO4_CLR 0xffffff7f
195 #define PWM_STA_GAPO4_MSB 7
196 #define PWM_STA_GAPO4_LSB 7
197 #define PWM_STA_BERR_BITS 8:8
198 #define PWM_STA_BERR_SET 0x00000100
199 #define PWM_STA_BERR_CLR 0xfffffeff
200 #define PWM_STA_BERR_MSB 8
201 #define PWM_STA_BERR_LSB 8
202 #define PWM_STA_STA1_BITS 9:9
203 #define PWM_STA_STA1_SET 0x00000200
204 #define PWM_STA_STA1_CLR 0xfffffdff
205 #define PWM_STA_STA1_MSB 9
206 #define PWM_STA_STA1_LSB 9
207 #define PWM_STA_STA2_BITS 10:10
208 #define PWM_STA_STA2_SET 0x00000400
209 #define PWM_STA_STA2_CLR 0xfffffbff
210 #define PWM_STA_STA2_MSB 10
211 #define PWM_STA_STA2_LSB 10
212 #define PWM_STA_STA3_BITS 11:11
213 #define PWM_STA_STA3_SET 0x00000800
214 #define PWM_STA_STA3_CLR 0xfffff7ff
215 #define PWM_STA_STA3_MSB 11
216 #define PWM_STA_STA3_LSB 11
217 #define PWM_STA_STA4_BITS 12:12
218 #define PWM_STA_STA4_SET 0x00001000
219 #define PWM_STA_STA4_CLR 0xffffefff
220 #define PWM_STA_STA4_MSB 12
221 #define PWM_STA_STA4_LSB 12
222 #define PWM_DMAC HW_REGISTER_RW( 0x7e20c008 )
223 #define PWM_DMAC_MASK 0x8000ffff
224 #define PWM_DMAC_WIDTH 32
225 #define PWM_DMAC_RESET 0x00000707
226 #define PWM_DMAC_DREQ_BITS 7:0
227 #define PWM_DMAC_DREQ_SET 0x000000ff
228 #define PWM_DMAC_DREQ_CLR 0xffffff00
229 #define PWM_DMAC_DREQ_MSB 7
230 #define PWM_DMAC_DREQ_LSB 0
231 #define PWM_DMAC_PANIC_BITS 15:8
232 #define PWM_DMAC_PANIC_SET 0x0000ff00
233 #define PWM_DMAC_PANIC_CLR 0xffff00ff
234 #define PWM_DMAC_PANIC_MSB 15
235 #define PWM_DMAC_PANIC_LSB 8
236 #define PWM_DMAC_ENAB_BITS 31:31
237 #define PWM_DMAC_ENAB_SET 0x80000000
238 #define PWM_DMAC_ENAB_CLR 0x7fffffff
239 #define PWM_DMAC_ENAB_MSB 31
240 #define PWM_DMAC_ENAB_LSB 31
241 #define PWM_RNG1 HW_REGISTER_RW( 0x7e20c010 )
242 #define PWM_RNG1_MASK 0xffffffff
243 #define PWM_RNG1_WIDTH 32
244 #define PWM_RNG1_RESET 0x00000020
245 #define PWM_DAT1 HW_REGISTER_RW( 0x7e20c014 )
246 #define PWM_DAT1_MASK 0xffffffff
247 #define PWM_DAT1_WIDTH 32
248 #define PWM_DAT1_RESET 0000000000
249 #define PWM_FIF1 HW_REGISTER_RW( 0x7e20c018 )
250 #define PWM_FIF1_MASK 0xffffffff
251 #define PWM_FIF1_WIDTH 32
252 #define PWM_FIF1_RESET 0000000000
253 #define PWM_RNG2 HW_REGISTER_RW( 0x7e20c020 )
254 #define PWM_RNG2_MASK 0xffffffff
255 #define PWM_RNG2_WIDTH 32
256 #define PWM_RNG2_RESET 0x00000020
257 #define PWM_DAT2 HW_REGISTER_RW( 0x7e20c024 )
258 #define PWM_DAT2_MASK 0xffffffff
259 #define PWM_DAT2_WIDTH 32
260 #define PWM_DAT2_RESET 0000000000
261 #define PWM_RNG3 HW_REGISTER_RW( 0x7e20c030 )
262 #define PWM_RNG3_MASK 0000000000
263 #define PWM_RNG3_WIDTH 0
264 #define PWM_RNG3_RESET 0x00000020
265 #define PWM_DAT3 HW_REGISTER_RW( 0x7e20c034 )
266 #define PWM_DAT3_MASK 0000000000
267 #define PWM_DAT3_WIDTH 0
268 #define PWM_DAT3_RESET 0000000000
269 #define PWM_RNG4 HW_REGISTER_RW( 0x7e20c040 )
270 #define PWM_RNG4_MASK 0000000000
271 #define PWM_RNG4_WIDTH 0
272 #define PWM_RNG4_RESET 0x00000020
273 #define PWM_DAT4 HW_REGISTER_RW( 0x7e20c044 )
274 #define PWM_DAT4_MASK 0000000000
275 #define PWM_DAT4_WIDTH 0
276 #define PWM_DAT4_RESET 0000000000
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