Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / sdc_addr_front.h
1 // This file was generated by the create_regs script
2 #define APHY_CSR_BASE 0x7ee06000
3 #define APHY_CSR_ADDR_REV_ID HW_REGISTER_RW( 0x7ee06000 )
4 #define APHY_CSR_GLBL_ADDR_DLL_RESET HW_REGISTER_RW( 0x7ee06004 )
5 #define APHY_CSR_GLBL_ADDR_DLL_RECAL HW_REGISTER_RW( 0x7ee06008 )
6 #define APHY_CSR_GLBL_ADDR_DLL_CNTRL HW_REGISTER_RW( 0x7ee0600c )
7 #define APHY_CSR_GLBL_ADDR_DLL_PH_LD_VAL HW_REGISTER_RW( 0x7ee06010 )
8 #define APHY_CSR_ADDR_MASTER_DLL_OUTPUT HW_REGISTER_RW( 0x7ee06014 )
9 #define APHY_CSR_ADDR_SLAVE_DLL_OFFSET HW_REGISTER_RW( 0x7ee06018 )
10 #define APHY_CSR_GLBL_ADR_MSTR_DLL_BYPEN HW_REGISTER_RW( 0x7ee0601c )
11 #define APHY_CSR_GLBL_ADR_DLL_LOCK_STAT HW_REGISTER_RW( 0x7ee06020 )
12 #define APHY_CSR_DDR_PLL_GLOBAL_RESET HW_REGISTER_RW( 0x7ee06024 )
13 #define APHY_CSR_DDR_PLL_POST_DIV_RESET HW_REGISTER_RW( 0x7ee06028 )
14 #define APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0 HW_REGISTER_RW( 0x7ee0602c )
15 #define APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1 HW_REGISTER_RW( 0x7ee06030 )
16 #define APHY_CSR_DDR_PLL_MDIV_VALUE HW_REGISTER_RW( 0x7ee06034 )
17 #define APHY_CSR_DDR_PLL_CONFIG_CNTRL HW_REGISTER_RW( 0x7ee06038 )
18 #define APHY_CSR_DDR_PLL_MISC_CNTRL HW_REGISTER_RW( 0x7ee0603c )
19 #define APHY_CSR_DDR_PLL_SPRDSPECT_CTRL0 HW_REGISTER_RW( 0x7ee06040 )
20 #define APHY_CSR_DDR_PLL_SPRDSPECT_CTRL1 HW_REGISTER_RW( 0x7ee06044 )
21 #define APHY_CSR_DDR_PLL_LOCK_STATUS HW_REGISTER_RW( 0x7ee06048 )
22 #define APHY_CSR_DDR_PLL_HOLD_CH HW_REGISTER_RW( 0x7ee0604c )
23 #define APHY_CSR_DDR_PLL_ENABLE_CH HW_REGISTER_RW( 0x7ee06050 )
24 #define APHY_CSR_DDR_PLL_BYPASS HW_REGISTER_RW( 0x7ee06054 )
25 #define APHY_CSR_DDR_PLL_PWRDWN HW_REGISTER_RW( 0x7ee06058 )
26 #define APHY_CSR_DDR_PLL_CH0_DESKEW_CTRL HW_REGISTER_RW( 0x7ee0605c )
27 #define APHY_CSR_DDR_PLL_CH1_DESKEW_CTRL HW_REGISTER_RW( 0x7ee06060 )
28 #define APHY_CSR_DDR_PLL_DESKEW_STATUS HW_REGISTER_RW( 0x7ee06064 )
29 #define APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL HW_REGISTER_RW( 0x7ee06068 )
30 #define APHY_CSR_ADDR_PAD_MISC_CTRL HW_REGISTER_RW( 0x7ee0606c )
31 #define APHY_CSR_ADDR_PVT_COMP_CTRL HW_REGISTER_RW( 0x7ee06070 )
32 #define APHY_CSR_ADDR_PVT_COMP_OVRD_CTRL HW_REGISTER_RW( 0x7ee06074 )
33 #define APHY_CSR_ADDR_PVT_COMP_STATUS HW_REGISTER_RW( 0x7ee06078 )
34 #define APHY_CSR_ADDR_PVT_COMP_DEBUG HW_REGISTER_RW( 0x7ee0607c )
35 #define APHY_CSR_PHY_BIST_CNTRL_SPR HW_REGISTER_RW( 0x7ee06080 )
36 #define APHY_CSR_PHY_BIST_CA_CRC_SPR HW_REGISTER_RW( 0x7ee06084 )
37 #define APHY_CSR_ADDR_SPR0_RW HW_REGISTER_RW( 0x7ee06088 )
38 #define APHY_CSR_ADDR_SPR1_RO HW_REGISTER_RW( 0x7ee0608c )
39 #define APHY_CSR_ADDR_SPR_RO HW_REGISTER_RW( 0x7ee06090 )
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