dab2212fd2a6acda185294dcb3387cd5fd154a7c
[rpi-open-firmware.git] / bcm2708_chip / sdc_ctrl.h
1 // This file was generated by the create_regs script
2 #define SD_BASE 0x7ee00000
3 #define SD_APB_ID 0x5344434f
4 #define SD_CS HW_REGISTER_RW( 0x7ee00000 )
5 #define SD_CS_MASK 0x01ffffff
6 #define SD_CS_WIDTH 25
7 #define SD_CS_STALLING_BITS 24:24
8 #define SD_CS_STALLING_SET 0x01000000
9 #define SD_CS_STALLING_CLR 0xfeffffff
10 #define SD_CS_STALLING_MSB 24
11 #define SD_CS_STALLING_LSB 24
12 #define SD_CS_STALLING_RESET 0x0
13 #define SD_CS_EXCEPTION_BITS 23:23
14 #define SD_CS_EXCEPTION_SET 0x00800000
15 #define SD_CS_EXCEPTION_CLR 0xff7fffff
16 #define SD_CS_EXCEPTION_MSB 23
17 #define SD_CS_EXCEPTION_LSB 23
18 #define SD_CS_EXCEPTION_RESET 0x0
19 #define SD_CS_ASHDN_T_BITS 22:19
20 #define SD_CS_ASHDN_T_SET 0x00780000
21 #define SD_CS_ASHDN_T_CLR 0xff87ffff
22 #define SD_CS_ASHDN_T_MSB 22
23 #define SD_CS_ASHDN_T_LSB 19
24 #define SD_CS_ASHDN_T_RESET 0xf
25 #define SD_CS_DEL_KEEP_BITS 18:18
26 #define SD_CS_DEL_KEEP_SET 0x00040000
27 #define SD_CS_DEL_KEEP_CLR 0xfffbffff
28 #define SD_CS_DEL_KEEP_MSB 18
29 #define SD_CS_DEL_KEEP_LSB 18
30 #define SD_CS_DEL_KEEP_RESET 0x0
31 #define SD_CS_ASHDNE_BITS 17:17
32 #define SD_CS_ASHDNE_SET 0x00020000
33 #define SD_CS_ASHDNE_CLR 0xfffdffff
34 #define SD_CS_ASHDNE_MSB 17
35 #define SD_CS_ASHDNE_LSB 17
36 #define SD_CS_ASHDNE_RESET 0x0
37 #define SD_CS_RDH_IDLE_BITS 16:16
38 #define SD_CS_RDH_IDLE_SET 0x00010000
39 #define SD_CS_RDH_IDLE_CLR 0xfffeffff
40 #define SD_CS_RDH_IDLE_MSB 16
41 #define SD_CS_RDH_IDLE_LSB 16
42 #define SD_CS_RDH_IDLE_RESET 0x0
43 #define SD_CS_SDUP_BITS 15:15
44 #define SD_CS_SDUP_SET 0x00008000
45 #define SD_CS_SDUP_CLR 0xffff7fff
46 #define SD_CS_SDUP_MSB 15
47 #define SD_CS_SDUP_LSB 15
48 #define SD_CS_SDUP_RESET 0x0
49 #define SD_CS_CLKOFF_BITS 14:14
50 #define SD_CS_CLKOFF_SET 0x00004000
51 #define SD_CS_CLKOFF_CLR 0xffffbfff
52 #define SD_CS_CLKOFF_MSB 14
53 #define SD_CS_CLKOFF_LSB 14
54 #define SD_CS_CLKOFF_RESET 0x1
55 #define SD_CS_DLLCAL_BITS 11:10
56 #define SD_CS_DLLCAL_SET 0x00000c00
57 #define SD_CS_DLLCAL_CLR 0xfffff3ff
58 #define SD_CS_DLLCAL_MSB 11
59 #define SD_CS_DLLCAL_LSB 10
60 #define SD_CS_DLLCAL_RESET 0x0
61 #define SD_CS_IDLE_BITS 9:9
62 #define SD_CS_IDLE_SET 0x00000200
63 #define SD_CS_IDLE_CLR 0xfffffdff
64 #define SD_CS_IDLE_MSB 9
65 #define SD_CS_IDLE_LSB 9
66 #define SD_CS_IDLE_RESET 0x0
67 #define SD_CS_SREF2RUN_BITS 8:8
68 #define SD_CS_SREF2RUN_SET 0x00000100
69 #define SD_CS_SREF2RUN_CLR 0xfffffeff
70 #define SD_CS_SREF2RUN_MSB 8
71 #define SD_CS_SREF2RUN_LSB 8
72 #define SD_CS_SREF2RUN_RESET 0x0
73 #define SD_CS_STOP_BITS 7:7
74 #define SD_CS_STOP_SET 0x00000080
75 #define SD_CS_STOP_CLR 0xffffff7f
76 #define SD_CS_STOP_MSB 7
77 #define SD_CS_STOP_LSB 7
78 #define SD_CS_STOP_RESET 0x0
79 #define SD_CS_STATEN_BITS 6:6
80 #define SD_CS_STATEN_SET 0x00000040
81 #define SD_CS_STATEN_CLR 0xffffffbf
82 #define SD_CS_STATEN_MSB 6
83 #define SD_CS_STATEN_LSB 6
84 #define SD_CS_STATEN_RESET 0x0
85 #define SD_CS_SDTST_BITS 5:5
86 #define SD_CS_SDTST_SET 0x00000020
87 #define SD_CS_SDTST_CLR 0xffffffdf
88 #define SD_CS_SDTST_MSB 5
89 #define SD_CS_SDTST_LSB 5
90 #define SD_CS_SDTST_RESET 0x0
91 #define SD_CS_PUSKIP_BITS 4:4
92 #define SD_CS_PUSKIP_SET 0x00000010
93 #define SD_CS_PUSKIP_CLR 0xffffffef
94 #define SD_CS_PUSKIP_MSB 4
95 #define SD_CS_PUSKIP_LSB 4
96 #define SD_CS_PUSKIP_RESET 0x0
97 #define SD_CS_STBY_BITS 3:3
98 #define SD_CS_STBY_SET 0x00000008
99 #define SD_CS_STBY_CLR 0xfffffff7
100 #define SD_CS_STBY_MSB 3
101 #define SD_CS_STBY_LSB 3
102 #define SD_CS_STBY_RESET 0x0
103 #define SD_CS_DPD_BITS 2:2
104 #define SD_CS_DPD_SET 0x00000004
105 #define SD_CS_DPD_CLR 0xfffffffb
106 #define SD_CS_DPD_MSB 2
107 #define SD_CS_DPD_LSB 2
108 #define SD_CS_DPD_RESET 0x0
109 #define SD_CS_EN_BITS 1:1
110 #define SD_CS_EN_SET 0x00000002
111 #define SD_CS_EN_CLR 0xfffffffd
112 #define SD_CS_EN_MSB 1
113 #define SD_CS_EN_LSB 1
114 #define SD_CS_EN_RESET 0x0
115 #define SD_CS_RESTRT_BITS 0:0
116 #define SD_CS_RESTRT_SET 0x00000001
117 #define SD_CS_RESTRT_CLR 0xfffffffe
118 #define SD_CS_RESTRT_MSB 0
119 #define SD_CS_RESTRT_LSB 0
120 #define SD_CS_RESTRT_RESET 0x0
121 #define SD_SA HW_REGISTER_RW( 0x7ee00004 )
122 #define SD_SA_MASK 0xffffffff
123 #define SD_SA_WIDTH 32
124 #define SD_SA_RFSH_T_BITS 31:16
125 #define SD_SA_RFSH_T_SET 0xffff0000
126 #define SD_SA_RFSH_T_CLR 0x0000ffff
127 #define SD_SA_RFSH_T_MSB 31
128 #define SD_SA_RFSH_T_LSB 16
129 #define SD_SA_RFSH_T_RESET 0x30c
130 #define SD_SA_PGEHLD_IDL_BITS 15:15
131 #define SD_SA_PGEHLD_IDL_SET 0x00008000
132 #define SD_SA_PGEHLD_IDL_CLR 0xffff7fff
133 #define SD_SA_PGEHLD_IDL_MSB 15
134 #define SD_SA_PGEHLD_IDL_LSB 15
135 #define SD_SA_PGEHLD_IDL_RESET 0x0
136 #define SD_SA_PGEHLDE_BITS 8:8
137 #define SD_SA_PGEHLDE_SET 0x00000100
138 #define SD_SA_PGEHLDE_CLR 0xfffffeff
139 #define SD_SA_PGEHLDE_MSB 8
140 #define SD_SA_PGEHLDE_LSB 8
141 #define SD_SA_PGEHLDE_RESET 0x0
142 #define SD_SA_CLKSTOP_BITS 7:7
143 #define SD_SA_CLKSTOP_SET 0x00000080
144 #define SD_SA_CLKSTOP_CLR 0xffffff7f
145 #define SD_SA_CLKSTOP_MSB 7
146 #define SD_SA_CLKSTOP_LSB 7
147 #define SD_SA_CLKSTOP_RESET 0x1
148 #define SD_SA_POWSAVE_BITS 0:0
149 #define SD_SA_POWSAVE_SET 0x00000001
150 #define SD_SA_POWSAVE_CLR 0xfffffffe
151 #define SD_SA_POWSAVE_MSB 0
152 #define SD_SA_POWSAVE_LSB 0
153 #define SD_SA_POWSAVE_RESET 0x0
154 #define SD_SB HW_REGISTER_RW( 0x7ee00008 )
155 #define SD_SB_MASK 0xfff001ff
156 #define SD_SB_WIDTH 32
157 #define SD_SB_STBY_T_BITS 31:20
158 #define SD_SB_STBY_T_SET 0xfff00000
159 #define SD_SB_STBY_T_CLR 0x000fffff
160 #define SD_SB_STBY_T_MSB 31
161 #define SD_SB_STBY_T_LSB 20
162 #define SD_SB_STBY_T_RESET 0x0
163 #define SD_SB_INHIBIT_LA_BITS 8:8
164 #define SD_SB_INHIBIT_LA_SET 0x00000100
165 #define SD_SB_INHIBIT_LA_CLR 0xfffffeff
166 #define SD_SB_INHIBIT_LA_MSB 8
167 #define SD_SB_INHIBIT_LA_LSB 8
168 #define SD_SB_INHIBIT_LA_RESET 0x0
169 #define SD_SB_REORDER_BITS 7:7
170 #define SD_SB_REORDER_SET 0x00000080
171 #define SD_SB_REORDER_CLR 0xffffff7f
172 #define SD_SB_REORDER_MSB 7
173 #define SD_SB_REORDER_LSB 7
174 #define SD_SB_REORDER_RESET 0x0
175 #define SD_SB_BANKLOW_BITS 6:5
176 #define SD_SB_BANKLOW_SET 0x00000060
177 #define SD_SB_BANKLOW_CLR 0xffffff9f
178 #define SD_SB_BANKLOW_MSB 6
179 #define SD_SB_BANKLOW_LSB 5
180 #define SD_SB_BANKLOW_RESET 0x0
181 #define SD_SB_EIGHTBANK_BITS 4:4
182 #define SD_SB_EIGHTBANK_SET 0x00000010
183 #define SD_SB_EIGHTBANK_CLR 0xffffffef
184 #define SD_SB_EIGHTBANK_MSB 4
185 #define SD_SB_EIGHTBANK_LSB 4
186 #define SD_SB_EIGHTBANK_RESET 0x0
187 #define SD_SB_ROWBITS_BITS 3:2
188 #define SD_SB_ROWBITS_SET 0x0000000c
189 #define SD_SB_ROWBITS_CLR 0xfffffff3
190 #define SD_SB_ROWBITS_MSB 3
191 #define SD_SB_ROWBITS_LSB 2
192 #define SD_SB_ROWBITS_RESET 0x1
193 #define SD_SB_COLBITS_BITS 1:0
194 #define SD_SB_COLBITS_SET 0x00000003
195 #define SD_SB_COLBITS_CLR 0xfffffffc
196 #define SD_SB_COLBITS_MSB 1
197 #define SD_SB_COLBITS_LSB 0
198 #define SD_SB_COLBITS_RESET 0x1
199 #define SD_SC HW_REGISTER_RW( 0x7ee0000c )
200 #define SD_SC_MASK 0x7ff00f77
201 #define SD_SC_WIDTH 31
202 #define SD_SC_T_RFC_BITS 30:24
203 #define SD_SC_T_RFC_SET 0x7f000000
204 #define SD_SC_T_RFC_CLR 0x80ffffff
205 #define SD_SC_T_RFC_MSB 30
206 #define SD_SC_T_RFC_LSB 24
207 #define SD_SC_T_RFC_RESET 0x1e
208 #define SD_SC_T_RRD_BITS 23:20
209 #define SD_SC_T_RRD_SET 0x00f00000
210 #define SD_SC_T_RRD_CLR 0xff0fffff
211 #define SD_SC_T_RRD_MSB 23
212 #define SD_SC_T_RRD_LSB 20
213 #define SD_SC_T_RRD_RESET 0x4
214 #define SD_SC_T_WR_BITS 11:8
215 #define SD_SC_T_WR_SET 0x00000f00
216 #define SD_SC_T_WR_CLR 0xfffff0ff
217 #define SD_SC_T_WR_MSB 11
218 #define SD_SC_T_WR_LSB 8
219 #define SD_SC_T_WR_RESET 0x6
220 #define SD_SC_T_WTR_BITS 6:4
221 #define SD_SC_T_WTR_SET 0x00000070
222 #define SD_SC_T_WTR_CLR 0xffffff8f
223 #define SD_SC_T_WTR_MSB 6
224 #define SD_SC_T_WTR_LSB 4
225 #define SD_SC_T_WTR_RESET 0x3
226 #define SD_SC_WL_BITS 2:0
227 #define SD_SC_WL_SET 0x00000007
228 #define SD_SC_WL_CLR 0xfffffff8
229 #define SD_SC_WL_MSB 2
230 #define SD_SC_WL_LSB 0
231 #define SD_SC_WL_RESET 0x2
232 #define SD_SD HW_REGISTER_RW( 0x7ee00094 )
233 #define SD_SD_MASK 0xf1f71fff
234 #define SD_SD_WIDTH 32
235 #define SD_SD_T_RPab_BITS 31:28
236 #define SD_SD_T_RPab_SET 0xf0000000
237 #define SD_SD_T_RPab_CLR 0x0fffffff
238 #define SD_SD_T_RPab_MSB 31
239 #define SD_SD_T_RPab_LSB 28
240 #define SD_SD_T_RPab_RESET 0xa
241 #define SD_SD_T_RC_BITS 24:20
242 #define SD_SD_T_RC_SET 0x01f00000
243 #define SD_SD_T_RC_CLR 0xfe0fffff
244 #define SD_SD_T_RC_MSB 24
245 #define SD_SD_T_RC_LSB 20
246 #define SD_SD_T_RC_RESET 0x14
247 #define SD_SD_T_XP_BITS 18:16
248 #define SD_SD_T_XP_SET 0x00070000
249 #define SD_SD_T_XP_CLR 0xfff8ffff
250 #define SD_SD_T_XP_MSB 18
251 #define SD_SD_T_XP_LSB 16
252 #define SD_SD_T_XP_RESET 0x2
253 #define SD_SD_T_RAS_BITS 12:8
254 #define SD_SD_T_RAS_SET 0x00001f00
255 #define SD_SD_T_RAS_CLR 0xffffe0ff
256 #define SD_SD_T_RAS_MSB 12
257 #define SD_SD_T_RAS_LSB 8
258 #define SD_SD_T_RAS_RESET 0xe
259 #define SD_SD_T_RPpb_BITS 7:4
260 #define SD_SD_T_RPpb_SET 0x000000f0
261 #define SD_SD_T_RPpb_CLR 0xffffff0f
262 #define SD_SD_T_RPpb_MSB 7
263 #define SD_SD_T_RPpb_LSB 4
264 #define SD_SD_T_RPpb_RESET 0x8
265 #define SD_SD_T_RCD_BITS 3:0
266 #define SD_SD_T_RCD_SET 0x0000000f
267 #define SD_SD_T_RCD_CLR 0xfffffff0
268 #define SD_SD_T_RCD_MSB 3
269 #define SD_SD_T_RCD_LSB 0
270 #define SD_SD_T_RCD_RESET 0x8
271 #define SD_SE HW_REGISTER_RW( 0x7ee00098 )
272 #define SD_SE_MASK 0x13f3f73f
273 #define SD_SE_WIDTH 29
274 #define SD_SE_RL_EN_BITS 28:28
275 #define SD_SE_RL_EN_SET 0x10000000
276 #define SD_SE_RL_EN_CLR 0xefffffff
277 #define SD_SE_RL_EN_MSB 28
278 #define SD_SE_RL_EN_LSB 28
279 #define SD_SE_RL_EN_RESET 0x0
280 #define SD_SE_RL_BITS 25:20
281 #define SD_SE_RL_SET 0x03f00000
282 #define SD_SE_RL_CLR 0xfc0fffff
283 #define SD_SE_RL_MSB 25
284 #define SD_SE_RL_LSB 20
285 #define SD_SE_RL_RESET 0x8
286 #define SD_SE_T_FAW_BITS 17:12
287 #define SD_SE_T_FAW_SET 0x0003f000
288 #define SD_SE_T_FAW_CLR 0xfffc0fff
289 #define SD_SE_T_FAW_MSB 17
290 #define SD_SE_T_FAW_LSB 12
291 #define SD_SE_T_FAW_RESET 0x19
292 #define SD_SE_T_RTP_BITS 10:8
293 #define SD_SE_T_RTP_SET 0x00000700
294 #define SD_SE_T_RTP_CLR 0xfffff8ff
295 #define SD_SE_T_RTP_MSB 10
296 #define SD_SE_T_RTP_LSB 8
297 #define SD_SE_T_RTP_RESET 0x3
298 #define SD_SE_T_XSR_BITS 5:0
299 #define SD_SE_T_XSR_SET 0x0000003f
300 #define SD_SE_T_XSR_CLR 0xffffffc0
301 #define SD_SE_T_XSR_MSB 5
302 #define SD_SE_T_XSR_LSB 0
303 #define SD_SE_T_XSR_RESET 0x28
304 #define SD_SF HW_REGISTER_RW( 0x7ee000b4 )
305 #define SD_SF_MASK 0x3fffffff
306 #define SD_SF_WIDTH 30
307 #define SD_SF_PHYHOLD_BITS 29:29
308 #define SD_SF_PHYHOLD_SET 0x20000000
309 #define SD_SF_PHYHOLD_CLR 0xdfffffff
310 #define SD_SF_PHYHOLD_MSB 29
311 #define SD_SF_PHYHOLD_LSB 29
312 #define SD_SF_PHYHOLD_RESET 0x0
313 #define SD_SF_PGEHLD_T_BITS 28:19
314 #define SD_SF_PGEHLD_T_SET 0x1ff80000
315 #define SD_SF_PGEHLD_T_CLR 0xe007ffff
316 #define SD_SF_PGEHLD_T_MSB 28
317 #define SD_SF_PGEHLD_T_LSB 19
318 #define SD_SF_PGEHLD_T_RESET 0x100
319 #define SD_SF_POWSAV_T_BITS 18:9
320 #define SD_SF_POWSAV_T_SET 0x0007fe00
321 #define SD_SF_POWSAV_T_CLR 0xfff801ff
322 #define SD_SF_POWSAV_T_MSB 18
323 #define SD_SF_POWSAV_T_LSB 9
324 #define SD_SF_POWSAV_T_RESET 0x040
325 #define SD_SF_MDLL_CAL_BITS 8:0
326 #define SD_SF_MDLL_CAL_SET 0x000001ff
327 #define SD_SF_MDLL_CAL_CLR 0xfffffe00
328 #define SD_SF_MDLL_CAL_MSB 8
329 #define SD_SF_MDLL_CAL_LSB 0
330 #define SD_SF_MDLL_CAL_RESET 0x12c
331 #define SD_MR HW_REGISTER_RW( 0x7ee00090 )
332 #define SD_MR_MASK 0xf0ffffff
333 #define SD_MR_WIDTH 32
334 #define SD_MR_DONE_BITS 31:31
335 #define SD_MR_DONE_SET 0x80000000
336 #define SD_MR_DONE_CLR 0x7fffffff
337 #define SD_MR_DONE_MSB 31
338 #define SD_MR_DONE_LSB 31
339 #define SD_MR_DONE_RESET 0x1
340 #define SD_MR_TIMEOUT_BITS 30:30
341 #define SD_MR_TIMEOUT_SET 0x40000000
342 #define SD_MR_TIMEOUT_CLR 0xbfffffff
343 #define SD_MR_TIMEOUT_MSB 30
344 #define SD_MR_TIMEOUT_LSB 30
345 #define SD_MR_TIMEOUT_RESET 0x0
346 #define SD_MR_HI_Z_BITS 29:29
347 #define SD_MR_HI_Z_SET 0x20000000
348 #define SD_MR_HI_Z_CLR 0xdfffffff
349 #define SD_MR_HI_Z_MSB 29
350 #define SD_MR_HI_Z_LSB 29
351 #define SD_MR_HI_Z_RESET 0x0
352 #define SD_MR_RW_BITS 28:28
353 #define SD_MR_RW_SET 0x10000000
354 #define SD_MR_RW_CLR 0xefffffff
355 #define SD_MR_RW_MSB 28
356 #define SD_MR_RW_LSB 28
357 #define SD_MR_RW_RESET 0x0
358 #define SD_MR_RDATA_BITS 23:16
359 #define SD_MR_RDATA_SET 0x00ff0000
360 #define SD_MR_RDATA_CLR 0xff00ffff
361 #define SD_MR_RDATA_MSB 23
362 #define SD_MR_RDATA_LSB 16
363 #define SD_MR_RDATA_RESET 0x0
364 #define SD_MR_WDATA_BITS 15:8
365 #define SD_MR_WDATA_SET 0x0000ff00
366 #define SD_MR_WDATA_CLR 0xffff00ff
367 #define SD_MR_WDATA_MSB 15
368 #define SD_MR_WDATA_LSB 8
369 #define SD_MR_WDATA_RESET 0x0
370 #define SD_MR_ADDR_BITS 7:0
371 #define SD_MR_ADDR_SET 0x000000ff
372 #define SD_MR_ADDR_CLR 0xffffff00
373 #define SD_MR_ADDR_MSB 7
374 #define SD_MR_ADDR_LSB 0
375 #define SD_MR_ADDR_RESET 0x0
376 #define SD_MRT HW_REGISTER_RW( 0x7ee00064 )
377 #define SD_MRT_MASK 0x000001ff
378 #define SD_MRT_WIDTH 9
379 #define SD_MRT_T_MRW_BITS 8:0
380 #define SD_MRT_T_MRW_SET 0x000001ff
381 #define SD_MRT_T_MRW_CLR 0xfffffe00
382 #define SD_MRT_T_MRW_MSB 8
383 #define SD_MRT_T_MRW_LSB 0
384 #define SD_MRT_T_MRW_RESET 0x4
385 #define SD_PT1 HW_REGISTER_RW( 0x7ee00014 )
386 #define SD_PT1_MASK 0x0fffffff
387 #define SD_PT1_WIDTH 28
388 #define SD_PT1_T_INIT3_BITS 27:8
389 #define SD_PT1_T_INIT3_SET 0x0fffff00
390 #define SD_PT1_T_INIT3_CLR 0xf00000ff
391 #define SD_PT1_T_INIT3_MSB 27
392 #define SD_PT1_T_INIT3_LSB 8
393 #define SD_PT1_T_INIT3_RESET 0x13880
394 #define SD_PT1_T_INIT1_BITS 7:0
395 #define SD_PT1_T_INIT1_SET 0x000000ff
396 #define SD_PT1_T_INIT1_CLR 0xffffff00
397 #define SD_PT1_T_INIT1_MSB 7
398 #define SD_PT1_T_INIT1_LSB 0
399 #define SD_PT1_T_INIT1_RESET 0x28
400 #define SD_PT2 HW_REGISTER_RW( 0x7ee00010 )
401 #define SD_PT2_MASK 0xffffffff
402 #define SD_PT2_WIDTH 32
403 #define SD_PT2_T_INIT5_BITS 15:0
404 #define SD_PT2_T_INIT5_SET 0x0000ffff
405 #define SD_PT2_T_INIT5_CLR 0xffff0000
406 #define SD_PT2_T_INIT5_MSB 15
407 #define SD_PT2_T_INIT5_LSB 0
408 #define SD_PT2_T_INIT5_RESET 0xfa0
409 #define SD_IDL HW_REGISTER_RW( 0x7ee00018 )
410 #define SD_IDL_MASK 0x0fffffff
411 #define SD_IDL_WIDTH 28
412 #define SD_IDL_RESET 0000000000
413 #define SD_RTC HW_REGISTER_RW( 0x7ee0001c )
414 #define SD_RTC_MASK 0xffffffff
415 #define SD_RTC_WIDTH 32
416 #define SD_RTC_RESET 0000000000
417 #define SD_WTC HW_REGISTER_RO( 0x7ee00020 )
418 #define SD_WTC_MASK 0x0fffffff
419 #define SD_WTC_WIDTH 28
420 #define SD_WTC_RESET 0000000000
421 #define SD_RDC HW_REGISTER_RO( 0x7ee00024 )
422 #define SD_RDC_MASK 0x0fffffff
423 #define SD_RDC_WIDTH 28
424 #define SD_RDC_RESET 0000000000
425 #define SD_WDC HW_REGISTER_RO( 0x7ee00028 )
426 #define SD_WDC_MASK 0x0fffffff
427 #define SD_WDC_WIDTH 28
428 #define SD_WDC_RESET 0000000000
429 #define SD_RAC HW_REGISTER_RO( 0x7ee0002c )
430 #define SD_RAC_MASK 0x0fffffff
431 #define SD_RAC_WIDTH 28
432 #define SD_RAC_RESET 0000000000
433 #define SD_CYC HW_REGISTER_RO( 0x7ee00030 )
434 #define SD_CYC_MASK 0x0fffffff
435 #define SD_CYC_WIDTH 28
436 #define SD_CYC_RESET 0000000000
437 #define SD_CMD HW_REGISTER_RO( 0x7ee00034 )
438 #define SD_CMD_MASK 0x0fffffff
439 #define SD_CMD_WIDTH 28
440 #define SD_CMD_RESET 0000000000
441 #define SD_DAT HW_REGISTER_RO( 0x7ee00038 )
442 #define SD_DAT_MASK 0x0fffffff
443 #define SD_DAT_WIDTH 28
444 #define SD_DAT_RESET 0000000000
445 #define SD_REORD HW_REGISTER_RO( 0x7ee000a8 )
446 #define SD_REORD_MASK 0x0fffffff
447 #define SD_REORD_WIDTH 28
448 #define SD_REORD_RESET 0000000000
449 #define SD_LAC HW_REGISTER_RO( 0x7ee000ac )
450 #define SD_LAC_MASK 0x0fffffff
451 #define SD_LAC_WIDTH 28
452 #define SD_LAC_RESET 0000000000
453 #define SD_PRE HW_REGISTER_RO( 0x7ee000b0 )
454 #define SD_PRE_MASK 0x0fffffff
455 #define SD_PRE_WIDTH 28
456 #define SD_PRE_RESET 0000000000
457 #define SD_SECSRT0 HW_REGISTER_RW( 0x7ee0003c )
458 #define SD_SECSRT0_MASK 0xffffffff
459 #define SD_SECSRT0_WIDTH 32
460 #define SD_SECSRT0_ADDR_MS_BITS 31:13
461 #define SD_SECSRT0_ADDR_MS_SET 0xffffe000
462 #define SD_SECSRT0_ADDR_MS_CLR 0x00001fff
463 #define SD_SECSRT0_ADDR_MS_MSB 31
464 #define SD_SECSRT0_ADDR_MS_LSB 13
465 #define SD_SECSRT0_ADDR_MS_RESET 0x0
466 #define SD_SECSRT0_ADDR_LS_BITS 12:1
467 #define SD_SECSRT0_ADDR_LS_SET 0x00001ffe
468 #define SD_SECSRT0_ADDR_LS_CLR 0xffffe001
469 #define SD_SECSRT0_ADDR_LS_MSB 12
470 #define SD_SECSRT0_ADDR_LS_LSB 1
471 #define SD_SECSRT0_ADDR_LS_RESET 0x0
472 #define SD_SECSRT0_EN_BITS 0:0
473 #define SD_SECSRT0_EN_SET 0x00000001
474 #define SD_SECSRT0_EN_CLR 0xfffffffe
475 #define SD_SECSRT0_EN_MSB 0
476 #define SD_SECSRT0_EN_LSB 0
477 #define SD_SECSRT0_EN_RESET 0x0
478 #define SD_SECEND0 HW_REGISTER_RW( 0x7ee00040 )
479 #define SD_SECEND0_MASK 0xffffffff
480 #define SD_SECEND0_WIDTH 32
481 #define SD_SECEND0_ADDR_MS_BITS 31:13
482 #define SD_SECEND0_ADDR_MS_SET 0xffffe000
483 #define SD_SECEND0_ADDR_MS_CLR 0x00001fff
484 #define SD_SECEND0_ADDR_MS_MSB 31
485 #define SD_SECEND0_ADDR_MS_LSB 13
486 #define SD_SECEND0_ADDR_MS_RESET 0x0
487 #define SD_SECEND0_ADDR_LS_BITS 12:0
488 #define SD_SECEND0_ADDR_LS_SET 0x00001fff
489 #define SD_SECEND0_ADDR_LS_CLR 0xffffe000
490 #define SD_SECEND0_ADDR_LS_MSB 12
491 #define SD_SECEND0_ADDR_LS_LSB 0
492 #define SD_SECEND0_ADDR_LS_RESET 0xfff
493 #define SD_SECSRT1 HW_REGISTER_RW( 0x7ee00044 )
494 #define SD_SECSRT1_MASK 0xffffffff
495 #define SD_SECSRT1_WIDTH 32
496 #define SD_SECSRT1_ADDR_MS_BITS 31:13
497 #define SD_SECSRT1_ADDR_MS_SET 0xffffe000
498 #define SD_SECSRT1_ADDR_MS_CLR 0x00001fff
499 #define SD_SECSRT1_ADDR_MS_MSB 31
500 #define SD_SECSRT1_ADDR_MS_LSB 13
501 #define SD_SECSRT1_ADDR_MS_RESET 0x0
502 #define SD_SECSRT1_ADDR_LS_BITS 12:1
503 #define SD_SECSRT1_ADDR_LS_SET 0x00001ffe
504 #define SD_SECSRT1_ADDR_LS_CLR 0xffffe001
505 #define SD_SECSRT1_ADDR_LS_MSB 12
506 #define SD_SECSRT1_ADDR_LS_LSB 1
507 #define SD_SECSRT1_ADDR_LS_RESET 0x0
508 #define SD_SECSRT1_EN_BITS 0:0
509 #define SD_SECSRT1_EN_SET 0x00000001
510 #define SD_SECSRT1_EN_CLR 0xfffffffe
511 #define SD_SECSRT1_EN_MSB 0
512 #define SD_SECSRT1_EN_LSB 0
513 #define SD_SECSRT1_EN_RESET 0x0
514 #define SD_SECEND1 HW_REGISTER_RW( 0x7ee00048 )
515 #define SD_SECEND1_MASK 0xffffffff
516 #define SD_SECEND1_WIDTH 32
517 #define SD_SECEND1_ADDR_MS_BITS 31:13
518 #define SD_SECEND1_ADDR_MS_SET 0xffffe000
519 #define SD_SECEND1_ADDR_MS_CLR 0x00001fff
520 #define SD_SECEND1_ADDR_MS_MSB 31
521 #define SD_SECEND1_ADDR_MS_LSB 13
522 #define SD_SECEND1_ADDR_MS_RESET 0x0
523 #define SD_SECEND1_ADDR_LS_BITS 12:0
524 #define SD_SECEND1_ADDR_LS_SET 0x00001fff
525 #define SD_SECEND1_ADDR_LS_CLR 0xffffe000
526 #define SD_SECEND1_ADDR_LS_MSB 12
527 #define SD_SECEND1_ADDR_LS_LSB 0
528 #define SD_SECEND1_ADDR_LS_RESET 0xfff
529 #define SD_SECSRT2 HW_REGISTER_RW( 0x7ee0004c )
530 #define SD_SECSRT2_MASK 0xffffffff
531 #define SD_SECSRT2_WIDTH 32
532 #define SD_SECSRT2_ADDR_MS_BITS 31:13
533 #define SD_SECSRT2_ADDR_MS_SET 0xffffe000
534 #define SD_SECSRT2_ADDR_MS_CLR 0x00001fff
535 #define SD_SECSRT2_ADDR_MS_MSB 31
536 #define SD_SECSRT2_ADDR_MS_LSB 13
537 #define SD_SECSRT2_ADDR_MS_RESET 0x0
538 #define SD_SECSRT2_ADDR_LS_BITS 12:1
539 #define SD_SECSRT2_ADDR_LS_SET 0x00001ffe
540 #define SD_SECSRT2_ADDR_LS_CLR 0xffffe001
541 #define SD_SECSRT2_ADDR_LS_MSB 12
542 #define SD_SECSRT2_ADDR_LS_LSB 1
543 #define SD_SECSRT2_ADDR_LS_RESET 0x0
544 #define SD_SECSRT2_EN_BITS 0:0
545 #define SD_SECSRT2_EN_SET 0x00000001
546 #define SD_SECSRT2_EN_CLR 0xfffffffe
547 #define SD_SECSRT2_EN_MSB 0
548 #define SD_SECSRT2_EN_LSB 0
549 #define SD_SECSRT2_EN_RESET 0x0
550 #define SD_SECEND2 HW_REGISTER_RW( 0x7ee00050 )
551 #define SD_SECEND2_MASK 0xffffffff
552 #define SD_SECEND2_WIDTH 32
553 #define SD_SECEND2_ADDR_MS_BITS 31:13
554 #define SD_SECEND2_ADDR_MS_SET 0xffffe000
555 #define SD_SECEND2_ADDR_MS_CLR 0x00001fff
556 #define SD_SECEND2_ADDR_MS_MSB 31
557 #define SD_SECEND2_ADDR_MS_LSB 13
558 #define SD_SECEND2_ADDR_MS_RESET 0x0
559 #define SD_SECEND2_ADDR_LS_BITS 12:0
560 #define SD_SECEND2_ADDR_LS_SET 0x00001fff
561 #define SD_SECEND2_ADDR_LS_CLR 0xffffe000
562 #define SD_SECEND2_ADDR_LS_MSB 12
563 #define SD_SECEND2_ADDR_LS_LSB 0
564 #define SD_SECEND2_ADDR_LS_RESET 0xfff
565 #define SD_SECSRT3 HW_REGISTER_RW( 0x7ee00054 )
566 #define SD_SECSRT3_MASK 0xffffffff
567 #define SD_SECSRT3_WIDTH 32
568 #define SD_SECSRT3_ADDR_MS_BITS 31:13
569 #define SD_SECSRT3_ADDR_MS_SET 0xffffe000
570 #define SD_SECSRT3_ADDR_MS_CLR 0x00001fff
571 #define SD_SECSRT3_ADDR_MS_MSB 31
572 #define SD_SECSRT3_ADDR_MS_LSB 13
573 #define SD_SECSRT3_ADDR_MS_RESET 0x0
574 #define SD_SECSRT3_ADDR_LS_BITS 12:1
575 #define SD_SECSRT3_ADDR_LS_SET 0x00001ffe
576 #define SD_SECSRT3_ADDR_LS_CLR 0xffffe001
577 #define SD_SECSRT3_ADDR_LS_MSB 12
578 #define SD_SECSRT3_ADDR_LS_LSB 1
579 #define SD_SECSRT3_ADDR_LS_RESET 0x0
580 #define SD_SECSRT3_EN_BITS 0:0
581 #define SD_SECSRT3_EN_SET 0x00000001
582 #define SD_SECSRT3_EN_CLR 0xfffffffe
583 #define SD_SECSRT3_EN_MSB 0
584 #define SD_SECSRT3_EN_LSB 0
585 #define SD_SECSRT3_EN_RESET 0x0
586 #define SD_SECEND3 HW_REGISTER_RW( 0x7ee00058 )
587 #define SD_SECEND3_MASK 0xffffffff
588 #define SD_SECEND3_WIDTH 32
589 #define SD_SECEND3_ADDR_MS_BITS 31:13
590 #define SD_SECEND3_ADDR_MS_SET 0xffffe000
591 #define SD_SECEND3_ADDR_MS_CLR 0x00001fff
592 #define SD_SECEND3_ADDR_MS_MSB 31
593 #define SD_SECEND3_ADDR_MS_LSB 13
594 #define SD_SECEND3_ADDR_MS_RESET 0x0
595 #define SD_SECEND3_ADDR_LS_BITS 12:0
596 #define SD_SECEND3_ADDR_LS_SET 0x00001fff
597 #define SD_SECEND3_ADDR_LS_CLR 0xffffe000
598 #define SD_SECEND3_ADDR_LS_MSB 12
599 #define SD_SECEND3_ADDR_LS_LSB 0
600 #define SD_SECEND3_ADDR_LS_RESET 0xfff
601 #define SD_PHYC HW_REGISTER_RW( 0x7ee00060 )
602 #define SD_PHYC_MASK 0x01111111
603 #define SD_PHYC_WIDTH 25
604 #define SD_PHYC_CRC_CLR_BITS 24:24
605 #define SD_PHYC_CRC_CLR_SET 0x01000000
606 #define SD_PHYC_CRC_CLR_CLR 0xfeffffff
607 #define SD_PHYC_CRC_CLR_MSB 24
608 #define SD_PHYC_CRC_CLR_LSB 24
609 #define SD_PHYC_CRC_CLR_RESET 0x0
610 #define SD_PHYC_CRC_EN_BITS 20:20
611 #define SD_PHYC_CRC_EN_SET 0x00100000
612 #define SD_PHYC_CRC_EN_CLR 0xffefffff
613 #define SD_PHYC_CRC_EN_MSB 20
614 #define SD_PHYC_CRC_EN_LSB 20
615 #define SD_PHYC_CRC_EN_RESET 0x0
616 #define SD_PHYC_MDLL_TMODE_BITS 16:16
617 #define SD_PHYC_MDLL_TMODE_SET 0x00010000
618 #define SD_PHYC_MDLL_TMODE_CLR 0xfffeffff
619 #define SD_PHYC_MDLL_TMODE_MSB 16
620 #define SD_PHYC_MDLL_TMODE_LSB 16
621 #define SD_PHYC_MDLL_TMODE_RESET 0x0
622 #define SD_PHYC_IOB_TMODE_BITS 12:12
623 #define SD_PHYC_IOB_TMODE_SET 0x00001000
624 #define SD_PHYC_IOB_TMODE_CLR 0xffffefff
625 #define SD_PHYC_IOB_TMODE_MSB 12
626 #define SD_PHYC_IOB_TMODE_LSB 12
627 #define SD_PHYC_IOB_TMODE_RESET 0x0
628 #define SD_PHYC_BIST_MODE_BITS 8:8
629 #define SD_PHYC_BIST_MODE_SET 0x00000100
630 #define SD_PHYC_BIST_MODE_CLR 0xfffffeff
631 #define SD_PHYC_BIST_MODE_MSB 8
632 #define SD_PHYC_BIST_MODE_LSB 8
633 #define SD_PHYC_BIST_MODE_RESET 0x0
634 #define SD_PHYC_VREF_ENB_BITS 4:4
635 #define SD_PHYC_VREF_ENB_SET 0x00000010
636 #define SD_PHYC_VREF_ENB_CLR 0xffffffef
637 #define SD_PHYC_VREF_ENB_MSB 4
638 #define SD_PHYC_VREF_ENB_LSB 4
639 #define SD_PHYC_VREF_ENB_RESET 0x0
640 #define SD_PHYC_PHYRST_BITS 0:0
641 #define SD_PHYC_PHYRST_SET 0x00000001
642 #define SD_PHYC_PHYRST_CLR 0xfffffffe
643 #define SD_PHYC_PHYRST_MSB 0
644 #define SD_PHYC_PHYRST_LSB 0
645 #define SD_PHYC_PHYRST_RESET 0x0
646 #define SD_TMC HW_REGISTER_RW( 0x7ee0007c )
647 #define SD_TMC_MASK 0xffffff73
648 #define SD_TMC_WIDTH 32
649 #define SD_TMC_TSTPAT_BITS 31:16
650 #define SD_TMC_TSTPAT_SET 0xffff0000
651 #define SD_TMC_TSTPAT_CLR 0x0000ffff
652 #define SD_TMC_TSTPAT_MSB 31
653 #define SD_TMC_TSTPAT_LSB 16
654 #define SD_TMC_TSTPAT_RESET 0x0
655 #define SD_TMC_IPRD_BITS 15:8
656 #define SD_TMC_IPRD_SET 0x0000ff00
657 #define SD_TMC_IPRD_CLR 0xffff00ff
658 #define SD_TMC_IPRD_MSB 15
659 #define SD_TMC_IPRD_LSB 8
660 #define SD_TMC_IPRD_RESET 0x0
661 #define SD_TMC_IPSEL_BITS 6:4
662 #define SD_TMC_IPSEL_SET 0x00000070
663 #define SD_TMC_IPSEL_CLR 0xffffff8f
664 #define SD_TMC_IPSEL_MSB 6
665 #define SD_TMC_IPSEL_LSB 4
666 #define SD_TMC_IPSEL_RESET 0x0
667 #define SD_TMC_TS_BITS 1:1
668 #define SD_TMC_TS_SET 0x00000002
669 #define SD_TMC_TS_CLR 0xfffffffd
670 #define SD_TMC_TS_MSB 1
671 #define SD_TMC_TS_LSB 1
672 #define SD_TMC_TS_RESET 0x0
673 #define SD_TMC_TSTCLK_BITS 0:0
674 #define SD_TMC_TSTCLK_SET 0x00000001
675 #define SD_TMC_TSTCLK_CLR 0xfffffffe
676 #define SD_TMC_TSTCLK_MSB 0
677 #define SD_TMC_TSTCLK_LSB 0
678 #define SD_TMC_TSTCLK_RESET 0x0
679 #define SD_RWC HW_REGISTER_RW( 0x7ee00080 )
680 #define SD_RWC_MASK 0x9fdf9f9f
681 #define SD_RWC_WIDTH 32
682 #define SD_RWC_RSTMAX_BITS 31:31
683 #define SD_RWC_RSTMAX_SET 0x80000000
684 #define SD_RWC_RSTMAX_CLR 0x7fffffff
685 #define SD_RWC_RSTMAX_MSB 31
686 #define SD_RWC_RSTMAX_LSB 31
687 #define SD_RWC_RSTMAX_RESET 0x0
688 #define SD_RWC_MAXCNT_BITS 28:24
689 #define SD_RWC_MAXCNT_SET 0x1f000000
690 #define SD_RWC_MAXCNT_CLR 0xe0ffffff
691 #define SD_RWC_MAXCNT_MSB 28
692 #define SD_RWC_MAXCNT_LSB 24
693 #define SD_RWC_MAXCNT_RESET 0x0
694 #define SD_RWC_MARGIN_BITS 23:22
695 #define SD_RWC_MARGIN_SET 0x00c00000
696 #define SD_RWC_MARGIN_CLR 0xff3fffff
697 #define SD_RWC_MARGIN_MSB 23
698 #define SD_RWC_MARGIN_LSB 22
699 #define SD_RWC_MARGIN_RESET 0x1
700 #define SD_RWC_LASTCNT_BITS 20:16
701 #define SD_RWC_LASTCNT_SET 0x001f0000
702 #define SD_RWC_LASTCNT_CLR 0xffe0ffff
703 #define SD_RWC_LASTCNT_MSB 20
704 #define SD_RWC_LASTCNT_LSB 16
705 #define SD_RWC_LASTCNT_RESET 0x0
706 #define SD_RWC_WRTOVR_BITS 15:15
707 #define SD_RWC_WRTOVR_SET 0x00008000
708 #define SD_RWC_WRTOVR_CLR 0xffff7fff
709 #define SD_RWC_WRTOVR_MSB 15
710 #define SD_RWC_WRTOVR_LSB 15
711 #define SD_RWC_WRTOVR_RESET 0x0
712 #define SD_RWC_WRTVAL_BITS 12:8
713 #define SD_RWC_WRTVAL_SET 0x00001f00
714 #define SD_RWC_WRTVAL_CLR 0xffffe0ff
715 #define SD_RWC_WRTVAL_MSB 12
716 #define SD_RWC_WRTVAL_LSB 8
717 #define SD_RWC_WRTVAL_RESET 0x0
718 #define SD_RWC_RXOVR_BITS 7:7
719 #define SD_RWC_RXOVR_SET 0x00000080
720 #define SD_RWC_RXOVR_CLR 0xffffff7f
721 #define SD_RWC_RXOVR_MSB 7
722 #define SD_RWC_RXOVR_LSB 7
723 #define SD_RWC_RXOVR_RESET 0x0
724 #define SD_RWC_RXVAL_BITS 4:0
725 #define SD_RWC_RXVAL_SET 0x0000001f
726 #define SD_RWC_RXVAL_CLR 0xffffffe0
727 #define SD_RWC_RXVAL_MSB 4
728 #define SD_RWC_RXVAL_LSB 0
729 #define SD_RWC_RXVAL_RESET 0x0
730 #define SD_VAD HW_REGISTER_RO( 0x7ee00084 )
731 #define SD_VAD_MASK 0xffffffff
732 #define SD_VAD_WIDTH 32
733 #define SD_VAD_RESET 0000000000
734 #define SD_VIN HW_REGISTER_RW( 0x7ee00088 )
735 #define SD_VIN_MASK 0x9113ffff
736 #define SD_VIN_WIDTH 32
737 #define SD_VIN_CLEAR_BITS 31:31
738 #define SD_VIN_CLEAR_SET 0x80000000
739 #define SD_VIN_CLEAR_CLR 0x7fffffff
740 #define SD_VIN_CLEAR_MSB 31
741 #define SD_VIN_CLEAR_LSB 31
742 #define SD_VIN_CLEAR_RESET 0x0
743 #define SD_VIN_INT_EN_BITS 28:28
744 #define SD_VIN_INT_EN_SET 0x10000000
745 #define SD_VIN_INT_EN_CLR 0xefffffff
746 #define SD_VIN_INT_EN_MSB 28
747 #define SD_VIN_INT_EN_LSB 28
748 #define SD_VIN_INT_EN_RESET 0x0
749 #define SD_VIN_MULT_BITS 24:24
750 #define SD_VIN_MULT_SET 0x01000000
751 #define SD_VIN_MULT_CLR 0xfeffffff
752 #define SD_VIN_MULT_MSB 24
753 #define SD_VIN_MULT_LSB 24
754 #define SD_VIN_MULT_RESET 0x0
755 #define SD_VIN_VIO_BITS 20:20
756 #define SD_VIN_VIO_SET 0x00100000
757 #define SD_VIN_VIO_CLR 0xffefffff
758 #define SD_VIN_VIO_MSB 20
759 #define SD_VIN_VIO_LSB 20
760 #define SD_VIN_VIO_RESET 0x0
761 #define SD_VIN_SPLIT_BITS 17:17
762 #define SD_VIN_SPLIT_SET 0x00020000
763 #define SD_VIN_SPLIT_CLR 0xfffdffff
764 #define SD_VIN_SPLIT_MSB 17
765 #define SD_VIN_SPLIT_LSB 17
766 #define SD_VIN_SPLIT_RESET 0x0
767 #define SD_VIN_WRITE_BITS 16:16
768 #define SD_VIN_WRITE_SET 0x00010000
769 #define SD_VIN_WRITE_CLR 0xfffeffff
770 #define SD_VIN_WRITE_MSB 16
771 #define SD_VIN_WRITE_LSB 16
772 #define SD_VIN_WRITE_RESET 0x0
773 #define SD_VIN_ID_BITS 15:0
774 #define SD_VIN_ID_SET 0x0000ffff
775 #define SD_VIN_ID_CLR 0xffff0000
776 #define SD_VIN_ID_MSB 15
777 #define SD_VIN_ID_LSB 0
778 #define SD_VIN_ID_RESET 0x0
779 #define SD_VER HW_REGISTER_RO( 0x7ee0009c )
780 #define SD_VER_MASK 0xffffffff
781 #define SD_VER_WIDTH 32
782 #define SD_VER_RESET 0x00000009
783 #define SD_STALL HW_REGISTER_RW( 0x7ee000a0 ) // ENGINEERING & DEBUG USE ONLY
784 #define SD_STALL_MASK 0x000003ff
785 #define SD_STALL_WIDTH 10
786 #define SD_STALL_CYCLES_BITS 9:0
787 #define SD_STALL_CYCLES_SET 0x000003ff
788 #define SD_STALL_CYCLES_CLR 0xfffffc00
789 #define SD_STALL_CYCLES_MSB 9
790 #define SD_STALL_CYCLES_LSB 0
791 #define SD_STALL_CYCLES_RESET 0x0
792 #define SD_CARCRC HW_REGISTER_RO( 0x7ee00100 )
793 #define SD_CARCRC_MASK 0xffffffff
794 #define SD_CARCRC_WIDTH 32
795 #define SD_CARCRC_RISE_BITS 31:16
796 #define SD_CARCRC_RISE_SET 0xffff0000
797 #define SD_CARCRC_RISE_CLR 0x0000ffff
798 #define SD_CARCRC_RISE_MSB 31
799 #define SD_CARCRC_RISE_LSB 16
800 #define SD_CARCRC_RISE_RESET 0x0
801 #define SD_CARCRC_FALL_BITS 15:0
802 #define SD_CARCRC_FALL_SET 0x0000ffff
803 #define SD_CARCRC_FALL_CLR 0xffff0000
804 #define SD_CARCRC_FALL_MSB 15
805 #define SD_CARCRC_FALL_LSB 0
806 #define SD_CARCRC_FALL_RESET 0x0
807 #define SD_DMRCRC0 HW_REGISTER_RO( 0x7ee00104 )
808 #define SD_DMRCRC0_MASK 0xffffffff
809 #define SD_DMRCRC0_WIDTH 32
810 #define SD_DMRCRC0_HIGH_BITS 31:16
811 #define SD_DMRCRC0_HIGH_SET 0xffff0000
812 #define SD_DMRCRC0_HIGH_CLR 0x0000ffff
813 #define SD_DMRCRC0_HIGH_MSB 31
814 #define SD_DMRCRC0_HIGH_LSB 16
815 #define SD_DMRCRC0_HIGH_RESET 0x0
816 #define SD_DMRCRC0_LOW_BITS 15:0
817 #define SD_DMRCRC0_LOW_SET 0x0000ffff
818 #define SD_DMRCRC0_LOW_CLR 0xffff0000
819 #define SD_DMRCRC0_LOW_MSB 15
820 #define SD_DMRCRC0_LOW_LSB 0
821 #define SD_DMRCRC0_LOW_RESET 0x0
822 #define SD_DMRCRC1 HW_REGISTER_RO( 0x7ee00108 ) // (only for 64 bit wide SDRAM)
823 #define SD_DMRCRC1_MASK 0xffffffff
824 #define SD_DMRCRC1_WIDTH 32
825 #define SD_DMRCRC1_HIGH_BITS 31:16
826 #define SD_DMRCRC1_HIGH_SET 0xffff0000
827 #define SD_DMRCRC1_HIGH_CLR 0x0000ffff
828 #define SD_DMRCRC1_HIGH_MSB 31
829 #define SD_DMRCRC1_HIGH_LSB 16
830 #define SD_DMRCRC1_HIGH_RESET 0x0
831 #define SD_DMRCRC1_LOW_BITS 15:0
832 #define SD_DMRCRC1_LOW_SET 0x0000ffff
833 #define SD_DMRCRC1_LOW_CLR 0xffff0000
834 #define SD_DMRCRC1_LOW_MSB 15
835 #define SD_DMRCRC1_LOW_LSB 0
836 #define SD_DMRCRC1_LOW_RESET 0x0
837 #define SD_DQRCRC0 HW_REGISTER_RO( 0x7ee0010c )
838 #define SD_DQRCRC0_MASK 0xffffffff
839 #define SD_DQRCRC0_WIDTH 32
840 #define SD_DQRCRC0_RISE_BITS 31:16
841 #define SD_DQRCRC0_RISE_SET 0xffff0000
842 #define SD_DQRCRC0_RISE_CLR 0x0000ffff
843 #define SD_DQRCRC0_RISE_MSB 31
844 #define SD_DQRCRC0_RISE_LSB 16
845 #define SD_DQRCRC0_RISE_RESET 0x0
846 #define SD_DQRCRC0_FALL_BITS 15:0
847 #define SD_DQRCRC0_FALL_SET 0x0000ffff
848 #define SD_DQRCRC0_FALL_CLR 0xffff0000
849 #define SD_DQRCRC0_FALL_MSB 15
850 #define SD_DQRCRC0_FALL_LSB 0
851 #define SD_DQRCRC0_FALL_RESET 0x0
852 #define SD_DQRCRC1 HW_REGISTER_RO( 0x7ee00110 )
853 #define SD_DQRCRC1_MASK 0xffffffff
854 #define SD_DQRCRC1_WIDTH 32
855 #define SD_DQRCRC1_RISE_BITS 31:16
856 #define SD_DQRCRC1_RISE_SET 0xffff0000
857 #define SD_DQRCRC1_RISE_CLR 0x0000ffff
858 #define SD_DQRCRC1_RISE_MSB 31
859 #define SD_DQRCRC1_RISE_LSB 16
860 #define SD_DQRCRC1_RISE_RESET 0x0
861 #define SD_DQRCRC1_FALL_BITS 15:0
862 #define SD_DQRCRC1_FALL_SET 0x0000ffff
863 #define SD_DQRCRC1_FALL_CLR 0xffff0000
864 #define SD_DQRCRC1_FALL_MSB 15
865 #define SD_DQRCRC1_FALL_LSB 0
866 #define SD_DQRCRC1_FALL_RESET 0x0
867 #define SD_DQRCRC2 HW_REGISTER_RO( 0x7ee00114 )
868 #define SD_DQRCRC2_MASK 0xffffffff
869 #define SD_DQRCRC2_WIDTH 32
870 #define SD_DQRCRC2_RISE_BITS 31:16
871 #define SD_DQRCRC2_RISE_SET 0xffff0000
872 #define SD_DQRCRC2_RISE_CLR 0x0000ffff
873 #define SD_DQRCRC2_RISE_MSB 31
874 #define SD_DQRCRC2_RISE_LSB 16
875 #define SD_DQRCRC2_RISE_RESET 0x0
876 #define SD_DQRCRC2_FALL_BITS 15:0
877 #define SD_DQRCRC2_FALL_SET 0x0000ffff
878 #define SD_DQRCRC2_FALL_CLR 0xffff0000
879 #define SD_DQRCRC2_FALL_MSB 15
880 #define SD_DQRCRC2_FALL_LSB 0
881 #define SD_DQRCRC2_FALL_RESET 0x0
882 #define SD_DQRCRC3 HW_REGISTER_RO( 0x7ee00118 )
883 #define SD_DQRCRC3_MASK 0xffffffff
884 #define SD_DQRCRC3_WIDTH 32
885 #define SD_DQRCRC3_RISE_BITS 31:16
886 #define SD_DQRCRC3_RISE_SET 0xffff0000
887 #define SD_DQRCRC3_RISE_CLR 0x0000ffff
888 #define SD_DQRCRC3_RISE_MSB 31
889 #define SD_DQRCRC3_RISE_LSB 16
890 #define SD_DQRCRC3_RISE_RESET 0x0
891 #define SD_DQRCRC3_FALL_BITS 15:0
892 #define SD_DQRCRC3_FALL_SET 0x0000ffff
893 #define SD_DQRCRC3_FALL_CLR 0xffff0000
894 #define SD_DQRCRC3_FALL_MSB 15
895 #define SD_DQRCRC3_FALL_LSB 0
896 #define SD_DQRCRC3_FALL_RESET 0x0
897 #define SD_DQRCRC4 HW_REGISTER_RO( 0x7ee0011c )
898 #define SD_DQRCRC4_MASK 0xffffffff
899 #define SD_DQRCRC4_WIDTH 32
900 #define SD_DQRCRC4_RISE_BITS 31:16
901 #define SD_DQRCRC4_RISE_SET 0xffff0000
902 #define SD_DQRCRC4_RISE_CLR 0x0000ffff
903 #define SD_DQRCRC4_RISE_MSB 31
904 #define SD_DQRCRC4_RISE_LSB 16
905 #define SD_DQRCRC4_RISE_RESET 0x0
906 #define SD_DQRCRC4_FALL_BITS 15:0
907 #define SD_DQRCRC4_FALL_SET 0x0000ffff
908 #define SD_DQRCRC4_FALL_CLR 0xffff0000
909 #define SD_DQRCRC4_FALL_MSB 15
910 #define SD_DQRCRC4_FALL_LSB 0
911 #define SD_DQRCRC4_FALL_RESET 0x0
912 #define SD_DQRCRC5 HW_REGISTER_RO( 0x7ee00120 )
913 #define SD_DQRCRC5_MASK 0xffffffff
914 #define SD_DQRCRC5_WIDTH 32
915 #define SD_DQRCRC5_RISE_BITS 31:16
916 #define SD_DQRCRC5_RISE_SET 0xffff0000
917 #define SD_DQRCRC5_RISE_CLR 0x0000ffff
918 #define SD_DQRCRC5_RISE_MSB 31
919 #define SD_DQRCRC5_RISE_LSB 16
920 #define SD_DQRCRC5_RISE_RESET 0x0
921 #define SD_DQRCRC5_FALL_BITS 15:0
922 #define SD_DQRCRC5_FALL_SET 0x0000ffff
923 #define SD_DQRCRC5_FALL_CLR 0xffff0000
924 #define SD_DQRCRC5_FALL_MSB 15
925 #define SD_DQRCRC5_FALL_LSB 0
926 #define SD_DQRCRC5_FALL_RESET 0x0
927 #define SD_DQRCRC6 HW_REGISTER_RO( 0x7ee00124 )
928 #define SD_DQRCRC6_MASK 0xffffffff
929 #define SD_DQRCRC6_WIDTH 32
930 #define SD_DQRCRC6_RISE_BITS 31:16
931 #define SD_DQRCRC6_RISE_SET 0xffff0000
932 #define SD_DQRCRC6_RISE_CLR 0x0000ffff
933 #define SD_DQRCRC6_RISE_MSB 31
934 #define SD_DQRCRC6_RISE_LSB 16
935 #define SD_DQRCRC6_RISE_RESET 0x0
936 #define SD_DQRCRC6_FALL_BITS 15:0
937 #define SD_DQRCRC6_FALL_SET 0x0000ffff
938 #define SD_DQRCRC6_FALL_CLR 0xffff0000
939 #define SD_DQRCRC6_FALL_MSB 15
940 #define SD_DQRCRC6_FALL_LSB 0
941 #define SD_DQRCRC6_FALL_RESET 0x0
942 #define SD_DQRCRC7 HW_REGISTER_RO( 0x7ee00128 )
943 #define SD_DQRCRC7_MASK 0xffffffff
944 #define SD_DQRCRC7_WIDTH 32
945 #define SD_DQRCRC7_RISE_BITS 31:16
946 #define SD_DQRCRC7_RISE_SET 0xffff0000
947 #define SD_DQRCRC7_RISE_CLR 0x0000ffff
948 #define SD_DQRCRC7_RISE_MSB 31
949 #define SD_DQRCRC7_RISE_LSB 16
950 #define SD_DQRCRC7_RISE_RESET 0x0
951 #define SD_DQRCRC7_FALL_BITS 15:0
952 #define SD_DQRCRC7_FALL_SET 0x0000ffff
953 #define SD_DQRCRC7_FALL_CLR 0xffff0000
954 #define SD_DQRCRC7_FALL_MSB 15
955 #define SD_DQRCRC7_FALL_LSB 0
956 #define SD_DQRCRC7_FALL_RESET 0x0
957 #define SD_DQRCRC8 HW_REGISTER_RO( 0x7ee0012c ) // (only for 64 bit wide SDRAM)
958 #define SD_DQRCRC8_MASK 0xffffffff
959 #define SD_DQRCRC8_WIDTH 32
960 #define SD_DQRCRC8_RISE_BITS 31:16
961 #define SD_DQRCRC8_RISE_SET 0xffff0000
962 #define SD_DQRCRC8_RISE_CLR 0x0000ffff
963 #define SD_DQRCRC8_RISE_MSB 31
964 #define SD_DQRCRC8_RISE_LSB 16
965 #define SD_DQRCRC8_RISE_RESET 0x0
966 #define SD_DQRCRC8_FALL_BITS 15:0
967 #define SD_DQRCRC8_FALL_SET 0x0000ffff
968 #define SD_DQRCRC8_FALL_CLR 0xffff0000
969 #define SD_DQRCRC8_FALL_MSB 15
970 #define SD_DQRCRC8_FALL_LSB 0
971 #define SD_DQRCRC8_FALL_RESET 0x0
972 #define SD_DQRCRC9 HW_REGISTER_RO( 0x7ee00130 ) // (only for 64 bit wide SDRAM)
973 #define SD_DQRCRC9_MASK 0xffffffff
974 #define SD_DQRCRC9_WIDTH 32
975 #define SD_DQRCRC9_RISE_BITS 31:16
976 #define SD_DQRCRC9_RISE_SET 0xffff0000
977 #define SD_DQRCRC9_RISE_CLR 0x0000ffff
978 #define SD_DQRCRC9_RISE_MSB 31
979 #define SD_DQRCRC9_RISE_LSB 16
980 #define SD_DQRCRC9_RISE_RESET 0x0
981 #define SD_DQRCRC9_FALL_BITS 15:0
982 #define SD_DQRCRC9_FALL_SET 0x0000ffff
983 #define SD_DQRCRC9_FALL_CLR 0xffff0000
984 #define SD_DQRCRC9_FALL_MSB 15
985 #define SD_DQRCRC9_FALL_LSB 0
986 #define SD_DQRCRC9_FALL_RESET 0x0
987 #define SD_DQRCRC10 HW_REGISTER_RO( 0x7ee00134 ) // (only for 64 bit wide SDRAM)
988 #define SD_DQRCRC10_MASK 0xffffffff
989 #define SD_DQRCRC10_WIDTH 32
990 #define SD_DQRCRC10_RISE_BITS 31:16
991 #define SD_DQRCRC10_RISE_SET 0xffff0000
992 #define SD_DQRCRC10_RISE_CLR 0x0000ffff
993 #define SD_DQRCRC10_RISE_MSB 31
994 #define SD_DQRCRC10_RISE_LSB 16
995 #define SD_DQRCRC10_RISE_RESET 0x0
996 #define SD_DQRCRC10_FALL_BITS 15:0
997 #define SD_DQRCRC10_FALL_SET 0x0000ffff
998 #define SD_DQRCRC10_FALL_CLR 0xffff0000
999 #define SD_DQRCRC10_FALL_MSB 15
1000 #define SD_DQRCRC10_FALL_LSB 0
1001 #define SD_DQRCRC10_FALL_RESET 0x0
1002 #define SD_DQRCRC11 HW_REGISTER_RO( 0x7ee00138 ) // (only for 64 bit wide SDRAM)
1003 #define SD_DQRCRC11_MASK 0xffffffff
1004 #define SD_DQRCRC11_WIDTH 32
1005 #define SD_DQRCRC11_RISE_BITS 31:16
1006 #define SD_DQRCRC11_RISE_SET 0xffff0000
1007 #define SD_DQRCRC11_RISE_CLR 0x0000ffff
1008 #define SD_DQRCRC11_RISE_MSB 31
1009 #define SD_DQRCRC11_RISE_LSB 16
1010 #define SD_DQRCRC11_RISE_RESET 0x0
1011 #define SD_DQRCRC11_FALL_BITS 15:0
1012 #define SD_DQRCRC11_FALL_SET 0x0000ffff
1013 #define SD_DQRCRC11_FALL_CLR 0xffff0000
1014 #define SD_DQRCRC11_FALL_MSB 15
1015 #define SD_DQRCRC11_FALL_LSB 0
1016 #define SD_DQRCRC11_FALL_RESET 0x0
1017 #define SD_DQRCRC12 HW_REGISTER_RO( 0x7ee0013c ) // (only for 64 bit wide SDRAM)
1018 #define SD_DQRCRC12_MASK 0xffffffff
1019 #define SD_DQRCRC12_WIDTH 32
1020 #define SD_DQRCRC12_RISE_BITS 31:16
1021 #define SD_DQRCRC12_RISE_SET 0xffff0000
1022 #define SD_DQRCRC12_RISE_CLR 0x0000ffff
1023 #define SD_DQRCRC12_RISE_MSB 31
1024 #define SD_DQRCRC12_RISE_LSB 16
1025 #define SD_DQRCRC12_RISE_RESET 0x0
1026 #define SD_DQRCRC12_FALL_BITS 15:0
1027 #define SD_DQRCRC12_FALL_SET 0x0000ffff
1028 #define SD_DQRCRC12_FALL_CLR 0xffff0000
1029 #define SD_DQRCRC12_FALL_MSB 15
1030 #define SD_DQRCRC12_FALL_LSB 0
1031 #define SD_DQRCRC12_FALL_RESET 0x0
1032 #define SD_DQRCRC13 HW_REGISTER_RO( 0x7ee00140 ) // (only for 64 bit wide SDRAM)
1033 #define SD_DQRCRC13_MASK 0xffffffff
1034 #define SD_DQRCRC13_WIDTH 32
1035 #define SD_DQRCRC13_RISE_BITS 31:16
1036 #define SD_DQRCRC13_RISE_SET 0xffff0000
1037 #define SD_DQRCRC13_RISE_CLR 0x0000ffff
1038 #define SD_DQRCRC13_RISE_MSB 31
1039 #define SD_DQRCRC13_RISE_LSB 16
1040 #define SD_DQRCRC13_RISE_RESET 0x0
1041 #define SD_DQRCRC13_FALL_BITS 15:0
1042 #define SD_DQRCRC13_FALL_SET 0x0000ffff
1043 #define SD_DQRCRC13_FALL_CLR 0xffff0000
1044 #define SD_DQRCRC13_FALL_MSB 15
1045 #define SD_DQRCRC13_FALL_LSB 0
1046 #define SD_DQRCRC13_FALL_RESET 0x0
1047 #define SD_DQRCRC14 HW_REGISTER_RO( 0x7ee00144 ) // (only for 64 bit wide SDRAM)
1048 #define SD_DQRCRC14_MASK 0xffffffff
1049 #define SD_DQRCRC14_WIDTH 32
1050 #define SD_DQRCRC14_RISE_BITS 31:16
1051 #define SD_DQRCRC14_RISE_SET 0xffff0000
1052 #define SD_DQRCRC14_RISE_CLR 0x0000ffff
1053 #define SD_DQRCRC14_RISE_MSB 31
1054 #define SD_DQRCRC14_RISE_LSB 16
1055 #define SD_DQRCRC14_RISE_RESET 0x0
1056 #define SD_DQRCRC14_FALL_BITS 15:0
1057 #define SD_DQRCRC14_FALL_SET 0x0000ffff
1058 #define SD_DQRCRC14_FALL_CLR 0xffff0000
1059 #define SD_DQRCRC14_FALL_MSB 15
1060 #define SD_DQRCRC14_FALL_LSB 0
1061 #define SD_DQRCRC14_FALL_RESET 0x0
1062 #define SD_DQRCRC15 HW_REGISTER_RO( 0x7ee00148 ) // (only for 64 bit wide SDRAM)
1063 #define SD_DQRCRC15_MASK 0xffffffff
1064 #define SD_DQRCRC15_WIDTH 32
1065 #define SD_DQRCRC15_RISE_BITS 31:16
1066 #define SD_DQRCRC15_RISE_SET 0xffff0000
1067 #define SD_DQRCRC15_RISE_CLR 0x0000ffff
1068 #define SD_DQRCRC15_RISE_MSB 31
1069 #define SD_DQRCRC15_RISE_LSB 16
1070 #define SD_DQRCRC15_RISE_RESET 0x0
1071 #define SD_DQRCRC15_FALL_BITS 15:0
1072 #define SD_DQRCRC15_FALL_SET 0x0000ffff
1073 #define SD_DQRCRC15_FALL_CLR 0xffff0000
1074 #define SD_DQRCRC15_FALL_MSB 15
1075 #define SD_DQRCRC15_FALL_LSB 0
1076 #define SD_DQRCRC15_FALL_RESET 0x0
1077 #define SD_DQLCRC0 HW_REGISTER_RO( 0x7ee0014c )
1078 #define SD_DQLCRC0_MASK 0xffffffff
1079 #define SD_DQLCRC0_WIDTH 32
1080 #define SD_DQLCRC0_RISE_BITS 31:16
1081 #define SD_DQLCRC0_RISE_SET 0xffff0000
1082 #define SD_DQLCRC0_RISE_CLR 0x0000ffff
1083 #define SD_DQLCRC0_RISE_MSB 31
1084 #define SD_DQLCRC0_RISE_LSB 16
1085 #define SD_DQLCRC0_RISE_RESET 0x0
1086 #define SD_DQLCRC0_FALL_BITS 15:0
1087 #define SD_DQLCRC0_FALL_SET 0x0000ffff
1088 #define SD_DQLCRC0_FALL_CLR 0xffff0000
1089 #define SD_DQLCRC0_FALL_MSB 15
1090 #define SD_DQLCRC0_FALL_LSB 0
1091 #define SD_DQLCRC0_FALL_RESET 0x0
1092 #define SD_DQLCRC1 HW_REGISTER_RO( 0x7ee00150 )
1093 #define SD_DQLCRC1_MASK 0xffffffff
1094 #define SD_DQLCRC1_WIDTH 32
1095 #define SD_DQLCRC1_RISE_BITS 31:16
1096 #define SD_DQLCRC1_RISE_SET 0xffff0000
1097 #define SD_DQLCRC1_RISE_CLR 0x0000ffff
1098 #define SD_DQLCRC1_RISE_MSB 31
1099 #define SD_DQLCRC1_RISE_LSB 16
1100 #define SD_DQLCRC1_RISE_RESET 0x0
1101 #define SD_DQLCRC1_FALL_BITS 15:0
1102 #define SD_DQLCRC1_FALL_SET 0x0000ffff
1103 #define SD_DQLCRC1_FALL_CLR 0xffff0000
1104 #define SD_DQLCRC1_FALL_MSB 15
1105 #define SD_DQLCRC1_FALL_LSB 0
1106 #define SD_DQLCRC1_FALL_RESET 0x0
1107 #define SD_DQLCRC2 HW_REGISTER_RO( 0x7ee00154 )
1108 #define SD_DQLCRC2_MASK 0xffffffff
1109 #define SD_DQLCRC2_WIDTH 32
1110 #define SD_DQLCRC2_RISE_BITS 31:16
1111 #define SD_DQLCRC2_RISE_SET 0xffff0000
1112 #define SD_DQLCRC2_RISE_CLR 0x0000ffff
1113 #define SD_DQLCRC2_RISE_MSB 31
1114 #define SD_DQLCRC2_RISE_LSB 16
1115 #define SD_DQLCRC2_RISE_RESET 0x0
1116 #define SD_DQLCRC2_FALL_BITS 15:0
1117 #define SD_DQLCRC2_FALL_SET 0x0000ffff
1118 #define SD_DQLCRC2_FALL_CLR 0xffff0000
1119 #define SD_DQLCRC2_FALL_MSB 15
1120 #define SD_DQLCRC2_FALL_LSB 0
1121 #define SD_DQLCRC2_FALL_RESET 0x0
1122 #define SD_DQLCRC3 HW_REGISTER_RO( 0x7ee00158 )
1123 #define SD_DQLCRC3_MASK 0xffffffff
1124 #define SD_DQLCRC3_WIDTH 32
1125 #define SD_DQLCRC3_RISE_BITS 31:16
1126 #define SD_DQLCRC3_RISE_SET 0xffff0000
1127 #define SD_DQLCRC3_RISE_CLR 0x0000ffff
1128 #define SD_DQLCRC3_RISE_MSB 31
1129 #define SD_DQLCRC3_RISE_LSB 16
1130 #define SD_DQLCRC3_RISE_RESET 0x0
1131 #define SD_DQLCRC3_FALL_BITS 15:0
1132 #define SD_DQLCRC3_FALL_SET 0x0000ffff
1133 #define SD_DQLCRC3_FALL_CLR 0xffff0000
1134 #define SD_DQLCRC3_FALL_MSB 15
1135 #define SD_DQLCRC3_FALL_LSB 0
1136 #define SD_DQLCRC3_FALL_RESET 0x0
1137 #define SD_DQLCRC4 HW_REGISTER_RO( 0x7ee0015c )
1138 #define SD_DQLCRC4_MASK 0xffffffff
1139 #define SD_DQLCRC4_WIDTH 32
1140 #define SD_DQLCRC4_RISE_BITS 31:16
1141 #define SD_DQLCRC4_RISE_SET 0xffff0000
1142 #define SD_DQLCRC4_RISE_CLR 0x0000ffff
1143 #define SD_DQLCRC4_RISE_MSB 31
1144 #define SD_DQLCRC4_RISE_LSB 16
1145 #define SD_DQLCRC4_RISE_RESET 0x0
1146 #define SD_DQLCRC4_FALL_BITS 15:0
1147 #define SD_DQLCRC4_FALL_SET 0x0000ffff
1148 #define SD_DQLCRC4_FALL_CLR 0xffff0000
1149 #define SD_DQLCRC4_FALL_MSB 15
1150 #define SD_DQLCRC4_FALL_LSB 0
1151 #define SD_DQLCRC4_FALL_RESET 0x0
1152 #define SD_DQLCRC5 HW_REGISTER_RO( 0x7ee00160 )
1153 #define SD_DQLCRC5_MASK 0xffffffff
1154 #define SD_DQLCRC5_WIDTH 32
1155 #define SD_DQLCRC5_RISE_BITS 31:16
1156 #define SD_DQLCRC5_RISE_SET 0xffff0000
1157 #define SD_DQLCRC5_RISE_CLR 0x0000ffff
1158 #define SD_DQLCRC5_RISE_MSB 31
1159 #define SD_DQLCRC5_RISE_LSB 16
1160 #define SD_DQLCRC5_RISE_RESET 0x0
1161 #define SD_DQLCRC5_FALL_BITS 15:0
1162 #define SD_DQLCRC5_FALL_SET 0x0000ffff
1163 #define SD_DQLCRC5_FALL_CLR 0xffff0000
1164 #define SD_DQLCRC5_FALL_MSB 15
1165 #define SD_DQLCRC5_FALL_LSB 0
1166 #define SD_DQLCRC5_FALL_RESET 0x0
1167 #define SD_DQLCRC6 HW_REGISTER_RO( 0x7ee00164 )
1168 #define SD_DQLCRC6_MASK 0xffffffff
1169 #define SD_DQLCRC6_WIDTH 32
1170 #define SD_DQLCRC6_RISE_BITS 31:16
1171 #define SD_DQLCRC6_RISE_SET 0xffff0000
1172 #define SD_DQLCRC6_RISE_CLR 0x0000ffff
1173 #define SD_DQLCRC6_RISE_MSB 31
1174 #define SD_DQLCRC6_RISE_LSB 16
1175 #define SD_DQLCRC6_RISE_RESET 0x0
1176 #define SD_DQLCRC6_FALL_BITS 15:0
1177 #define SD_DQLCRC6_FALL_SET 0x0000ffff
1178 #define SD_DQLCRC6_FALL_CLR 0xffff0000
1179 #define SD_DQLCRC6_FALL_MSB 15
1180 #define SD_DQLCRC6_FALL_LSB 0
1181 #define SD_DQLCRC6_FALL_RESET 0x0
1182 #define SD_DQLCRC7 HW_REGISTER_RO( 0x7ee00168 )
1183 #define SD_DQLCRC7_MASK 0xffffffff
1184 #define SD_DQLCRC7_WIDTH 32
1185 #define SD_DQLCRC7_RISE_BITS 31:16
1186 #define SD_DQLCRC7_RISE_SET 0xffff0000
1187 #define SD_DQLCRC7_RISE_CLR 0x0000ffff
1188 #define SD_DQLCRC7_RISE_MSB 31
1189 #define SD_DQLCRC7_RISE_LSB 16
1190 #define SD_DQLCRC7_RISE_RESET 0x0
1191 #define SD_DQLCRC7_FALL_BITS 15:0
1192 #define SD_DQLCRC7_FALL_SET 0x0000ffff
1193 #define SD_DQLCRC7_FALL_CLR 0xffff0000
1194 #define SD_DQLCRC7_FALL_MSB 15
1195 #define SD_DQLCRC7_FALL_LSB 0
1196 #define SD_DQLCRC7_FALL_RESET 0x0
1197 #define SD_DQLCRC8 HW_REGISTER_RO( 0x7ee0016c ) // (only for 64 bit wide SDRAM)
1198 #define SD_DQLCRC8_MASK 0xffffffff
1199 #define SD_DQLCRC8_WIDTH 32
1200 #define SD_DQLCRC8_RISE_BITS 31:16
1201 #define SD_DQLCRC8_RISE_SET 0xffff0000
1202 #define SD_DQLCRC8_RISE_CLR 0x0000ffff
1203 #define SD_DQLCRC8_RISE_MSB 31
1204 #define SD_DQLCRC8_RISE_LSB 16
1205 #define SD_DQLCRC8_RISE_RESET 0x0
1206 #define SD_DQLCRC8_FALL_BITS 15:0
1207 #define SD_DQLCRC8_FALL_SET 0x0000ffff
1208 #define SD_DQLCRC8_FALL_CLR 0xffff0000
1209 #define SD_DQLCRC8_FALL_MSB 15
1210 #define SD_DQLCRC8_FALL_LSB 0
1211 #define SD_DQLCRC8_FALL_RESET 0x0
1212 #define SD_DQLCRC9 HW_REGISTER_RO( 0x7ee00170 ) // (only for 64 bit wide SDRAM)
1213 #define SD_DQLCRC9_MASK 0xffffffff
1214 #define SD_DQLCRC9_WIDTH 32
1215 #define SD_DQLCRC9_RISE_BITS 31:16
1216 #define SD_DQLCRC9_RISE_SET 0xffff0000
1217 #define SD_DQLCRC9_RISE_CLR 0x0000ffff
1218 #define SD_DQLCRC9_RISE_MSB 31
1219 #define SD_DQLCRC9_RISE_LSB 16
1220 #define SD_DQLCRC9_RISE_RESET 0x0
1221 #define SD_DQLCRC9_FALL_BITS 15:0
1222 #define SD_DQLCRC9_FALL_SET 0x0000ffff
1223 #define SD_DQLCRC9_FALL_CLR 0xffff0000
1224 #define SD_DQLCRC9_FALL_MSB 15
1225 #define SD_DQLCRC9_FALL_LSB 0
1226 #define SD_DQLCRC9_FALL_RESET 0x0
1227 #define SD_DQLCRC10 HW_REGISTER_RO( 0x7ee00174 ) // (only for 64 bit wide SDRAM)
1228 #define SD_DQLCRC10_MASK 0xffffffff
1229 #define SD_DQLCRC10_WIDTH 32
1230 #define SD_DQLCRC10_RISE_BITS 31:16
1231 #define SD_DQLCRC10_RISE_SET 0xffff0000
1232 #define SD_DQLCRC10_RISE_CLR 0x0000ffff
1233 #define SD_DQLCRC10_RISE_MSB 31
1234 #define SD_DQLCRC10_RISE_LSB 16
1235 #define SD_DQLCRC10_RISE_RESET 0x0
1236 #define SD_DQLCRC10_FALL_BITS 15:0
1237 #define SD_DQLCRC10_FALL_SET 0x0000ffff
1238 #define SD_DQLCRC10_FALL_CLR 0xffff0000
1239 #define SD_DQLCRC10_FALL_MSB 15
1240 #define SD_DQLCRC10_FALL_LSB 0
1241 #define SD_DQLCRC10_FALL_RESET 0x0
1242 #define SD_DQLCRC11 HW_REGISTER_RO( 0x7ee00178 ) // (only for 64 bit wide SDRAM)
1243 #define SD_DQLCRC11_MASK 0xffffffff
1244 #define SD_DQLCRC11_WIDTH 32
1245 #define SD_DQLCRC11_RISE_BITS 31:16
1246 #define SD_DQLCRC11_RISE_SET 0xffff0000
1247 #define SD_DQLCRC11_RISE_CLR 0x0000ffff
1248 #define SD_DQLCRC11_RISE_MSB 31
1249 #define SD_DQLCRC11_RISE_LSB 16
1250 #define SD_DQLCRC11_RISE_RESET 0x0
1251 #define SD_DQLCRC11_FALL_BITS 15:0
1252 #define SD_DQLCRC11_FALL_SET 0x0000ffff
1253 #define SD_DQLCRC11_FALL_CLR 0xffff0000
1254 #define SD_DQLCRC11_FALL_MSB 15
1255 #define SD_DQLCRC11_FALL_LSB 0
1256 #define SD_DQLCRC11_FALL_RESET 0x0
1257 #define SD_DQLCRC12 HW_REGISTER_RO( 0x7ee0017c ) // (only for 64 bit wide SDRAM)
1258 #define SD_DQLCRC12_MASK 0xffffffff
1259 #define SD_DQLCRC12_WIDTH 32
1260 #define SD_DQLCRC12_RISE_BITS 31:16
1261 #define SD_DQLCRC12_RISE_SET 0xffff0000
1262 #define SD_DQLCRC12_RISE_CLR 0x0000ffff
1263 #define SD_DQLCRC12_RISE_MSB 31
1264 #define SD_DQLCRC12_RISE_LSB 16
1265 #define SD_DQLCRC12_RISE_RESET 0x0
1266 #define SD_DQLCRC12_FALL_BITS 15:0
1267 #define SD_DQLCRC12_FALL_SET 0x0000ffff
1268 #define SD_DQLCRC12_FALL_CLR 0xffff0000
1269 #define SD_DQLCRC12_FALL_MSB 15
1270 #define SD_DQLCRC12_FALL_LSB 0
1271 #define SD_DQLCRC12_FALL_RESET 0x0
1272 #define SD_DQLCRC13 HW_REGISTER_RO( 0x7ee00180 ) // (only for 64 bit wide SDRAM)
1273 #define SD_DQLCRC13_MASK 0xffffffff
1274 #define SD_DQLCRC13_WIDTH 32
1275 #define SD_DQLCRC13_RISE_BITS 31:16
1276 #define SD_DQLCRC13_RISE_SET 0xffff0000
1277 #define SD_DQLCRC13_RISE_CLR 0x0000ffff
1278 #define SD_DQLCRC13_RISE_MSB 31
1279 #define SD_DQLCRC13_RISE_LSB 16
1280 #define SD_DQLCRC13_RISE_RESET 0x0
1281 #define SD_DQLCRC13_FALL_BITS 15:0
1282 #define SD_DQLCRC13_FALL_SET 0x0000ffff
1283 #define SD_DQLCRC13_FALL_CLR 0xffff0000
1284 #define SD_DQLCRC13_FALL_MSB 15
1285 #define SD_DQLCRC13_FALL_LSB 0
1286 #define SD_DQLCRC13_FALL_RESET 0x0
1287 #define SD_DQLCRC14 HW_REGISTER_RO( 0x7ee00184 ) // (only for 64 bit wide SDRAM)
1288 #define SD_DQLCRC14_MASK 0xffffffff
1289 #define SD_DQLCRC14_WIDTH 32
1290 #define SD_DQLCRC14_RISE_BITS 31:16
1291 #define SD_DQLCRC14_RISE_SET 0xffff0000
1292 #define SD_DQLCRC14_RISE_CLR 0x0000ffff
1293 #define SD_DQLCRC14_RISE_MSB 31
1294 #define SD_DQLCRC14_RISE_LSB 16
1295 #define SD_DQLCRC14_RISE_RESET 0x0
1296 #define SD_DQLCRC14_FALL_BITS 15:0
1297 #define SD_DQLCRC14_FALL_SET 0x0000ffff
1298 #define SD_DQLCRC14_FALL_CLR 0xffff0000
1299 #define SD_DQLCRC14_FALL_MSB 15
1300 #define SD_DQLCRC14_FALL_LSB 0
1301 #define SD_DQLCRC14_FALL_RESET 0x0
1302 #define SD_DQLCRC15 HW_REGISTER_RO( 0x7ee00188 ) // (only for 64 bit wide SDRAM)
1303 #define SD_DQLCRC15_MASK 0xffffffff
1304 #define SD_DQLCRC15_WIDTH 32
1305 #define SD_DQLCRC15_RISE_BITS 31:16
1306 #define SD_DQLCRC15_RISE_SET 0xffff0000
1307 #define SD_DQLCRC15_RISE_CLR 0x0000ffff
1308 #define SD_DQLCRC15_RISE_MSB 31
1309 #define SD_DQLCRC15_RISE_LSB 16
1310 #define SD_DQLCRC15_RISE_RESET 0x0
1311 #define SD_DQLCRC15_FALL_BITS 15:0
1312 #define SD_DQLCRC15_FALL_SET 0x0000ffff
1313 #define SD_DQLCRC15_FALL_CLR 0xffff0000
1314 #define SD_DQLCRC15_FALL_MSB 15
1315 #define SD_DQLCRC15_FALL_LSB 0
1316 #define SD_DQLCRC15_FALL_RESET 0x0
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