e990489f038c8080d98d65382ddfee10d5124482
[rpi-open-firmware.git] / bcm2708_chip / sdc_dq_front.h
1 // This file was generated by the create_regs script
2 #define DPHY_CSR_BASE 0x7ee07000
3 #define DPHY_CSR_DQ_REV_ID HW_REGISTER_RW( 0x7ee07000 )
4 #define DPHY_CSR_GLBL_DQ_DLL_RESET HW_REGISTER_RW( 0x7ee07004 )
5 #define DPHY_CSR_GLBL_DQ_DLL_RECALIBRATE HW_REGISTER_RW( 0x7ee07008 )
6 #define DPHY_CSR_GLBL_DQ_DLL_CNTRL HW_REGISTER_RW( 0x7ee0700c )
7 #define DPHY_CSR_GLBL_DQ_DLL_PHASE_LD_VL HW_REGISTER_RW( 0x7ee07010 )
8 #define DPHY_CSR_GLBL_DQ_MSTR_DLL_BYP_EN HW_REGISTER_RW( 0x7ee07014 )
9 #define DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT HW_REGISTER_RW( 0x7ee07018 )
10 #define DPHY_CSR_BYTE0_SLAVE_DLL_OFFSET HW_REGISTER_RW( 0x7ee0701c )
11 #define DPHY_CSR_BYTE1_SLAVE_DLL_OFFSET HW_REGISTER_RW( 0x7ee07020 )
12 #define DPHY_CSR_BYTE2_SLAVE_DLL_OFFSET HW_REGISTER_RW( 0x7ee07024 )
13 #define DPHY_CSR_BYTE3_SLAVE_DLL_OFFSET HW_REGISTER_RW( 0x7ee07028 )
14 #define DPHY_CSR_BYTE0_MASTER_DLL_OUTPUT HW_REGISTER_RW( 0x7ee0702c )
15 #define DPHY_CSR_BYTE1_MASTER_DLL_OUTPUT HW_REGISTER_RW( 0x7ee07030 )
16 #define DPHY_CSR_BYTE2_MASTER_DLL_OUTPUT HW_REGISTER_RW( 0x7ee07034 )
17 #define DPHY_CSR_BYTE3_MASTER_DLL_OUTPUT HW_REGISTER_RW( 0x7ee07038 )
18 #define DPHY_CSR_NORM_READ_DQS_GATE_CTRL HW_REGISTER_RW( 0x7ee0703c )
19 #define DPHY_CSR_BOOT_READ_DQS_GATE_CTRL HW_REGISTER_RW( 0x7ee07040 )
20 #define DPHY_CSR_PHY_FIFO_PNTRS HW_REGISTER_RW( 0x7ee07044 )
21 #define DPHY_CSR_DQ_PHY_MISC_CTRL HW_REGISTER_RW( 0x7ee07048 )
22 #define DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL HW_REGISTER_RW( 0x7ee0704c )
23 #define DPHY_CSR_DQ_PAD_MISC_CTRL HW_REGISTER_RW( 0x7ee07050 )
24 #define DPHY_CSR_DQ_PVT_COMP_CTRL HW_REGISTER_RW( 0x7ee07054 )
25 #define DPHY_CSR_DQ_PVT_COMP_OVERRD_CTRL HW_REGISTER_RW( 0x7ee07058 )
26 #define DPHY_CSR_DQ_PVT_COMP_STATUS HW_REGISTER_RW( 0x7ee0705c )
27 #define DPHY_CSR_DQ_PVT_COMP_DEBUG HW_REGISTER_RW( 0x7ee07060 )
28 #define DPHY_CSR_DQ_PHY_READ_CTRL HW_REGISTER_RW( 0x7ee07064 )
29 #define DPHY_CSR_DQ_PHY_READ_STATUS HW_REGISTER_RW( 0x7ee07068 )
30 #define DPHY_CSR_DQ_SPR_RW HW_REGISTER_RW( 0x7ee0706c )
31 #define DPHY_CSR_DQ_SPR1_RO HW_REGISTER_RW( 0x7ee07070 )
32 #define DPHY_CSR_DQ_SPR_RO HW_REGISTER_RW( 0x7ee07074 )
33 #define DPHY_CSR_CRC_CTRL HW_REGISTER_RW( 0x7ee07800 )
34 #define DPHY_CSR_CRC_CTRL_MASK 0x00000111
35 #define DPHY_CSR_CRC_CTRL_WIDTH 9
36 #define DPHY_CSR_CRC_CTRL_RESET 0000000000
37 #define DPHY_CSR_CRC_DATA HW_REGISTER_RW( 0x7ee07804 )
38 #define DPHY_CSR_CRC_DATA_MASK 0x0fffffff
39 #define DPHY_CSR_CRC_DATA_WIDTH 28
40 #define DPHY_CSR_CRC_DATA_RESET 0000000000
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