Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / spi_master.h
1 // This file was generated by the create_regs script
2 #define SPI_BASE 0x7e204000
3 #define SPI_CS HW_REGISTER_RW( 0x7e204000 )
4 #define SPI_CS_MASK 0x001f07ff
5 #define SPI_CS_WIDTH 21
6 #define SPI_CS_RESET 0000000000
7 #define SPI_CS_RXF_BITS 20:20
8 #define SPI_CS_RXF_SET 0x00100000
9 #define SPI_CS_RXF_CLR 0xffefffff
10 #define SPI_CS_RXF_MSB 20
11 #define SPI_CS_RXF_LSB 20
12 #define SPI_CS_RXR_BITS 19:19
13 #define SPI_CS_RXR_SET 0x00080000
14 #define SPI_CS_RXR_CLR 0xfff7ffff
15 #define SPI_CS_RXR_MSB 19
16 #define SPI_CS_RXR_LSB 19
17 #define SPI_CS_TXD_BITS 18:18
18 #define SPI_CS_TXD_SET 0x00040000
19 #define SPI_CS_TXD_CLR 0xfffbffff
20 #define SPI_CS_TXD_MSB 18
21 #define SPI_CS_TXD_LSB 18
22 #define SPI_CS_RXD_BITS 17:17
23 #define SPI_CS_RXD_SET 0x00020000
24 #define SPI_CS_RXD_CLR 0xfffdffff
25 #define SPI_CS_RXD_MSB 17
26 #define SPI_CS_RXD_LSB 17
27 #define SPI_CS_DONE_BITS 16:16
28 #define SPI_CS_DONE_SET 0x00010000
29 #define SPI_CS_DONE_CLR 0xfffeffff
30 #define SPI_CS_DONE_MSB 16
31 #define SPI_CS_DONE_LSB 16
32 #define SPI_CS_INTR_BITS 10:10
33 #define SPI_CS_INTR_SET 0x00000400
34 #define SPI_CS_INTR_CLR 0xfffffbff
35 #define SPI_CS_INTR_MSB 10
36 #define SPI_CS_INTR_LSB 10
37 #define SPI_CS_INTD_BITS 9:9
38 #define SPI_CS_INTD_SET 0x00000200
39 #define SPI_CS_INTD_CLR 0xfffffdff
40 #define SPI_CS_INTD_MSB 9
41 #define SPI_CS_INTD_LSB 9
42 #define SPI_CS_DMAEN_BITS 8:8
43 #define SPI_CS_DMAEN_SET 0x00000100
44 #define SPI_CS_DMAEN_CLR 0xfffffeff
45 #define SPI_CS_DMAEN_MSB 8
46 #define SPI_CS_DMAEN_LSB 8
47 #define SPI_CS_TA_BITS 7:7
48 #define SPI_CS_TA_SET 0x00000080
49 #define SPI_CS_TA_CLR 0xffffff7f
50 #define SPI_CS_TA_MSB 7
51 #define SPI_CS_TA_LSB 7
52 #define SPI_CS_CSPOL_BITS 6:6
53 #define SPI_CS_CSPOL_SET 0x00000040
54 #define SPI_CS_CSPOL_CLR 0xffffffbf
55 #define SPI_CS_CSPOL_MSB 6
56 #define SPI_CS_CSPOL_LSB 6
57 #define SPI_CS_CLEAR_BITS 5:4
58 #define SPI_CS_CLEAR_SET 0x00000030
59 #define SPI_CS_CLEAR_CLR 0xffffffcf
60 #define SPI_CS_CLEAR_MSB 5
61 #define SPI_CS_CLEAR_LSB 4
62 #define SPI_CS_CPOL_BITS 3:3
63 #define SPI_CS_CPOL_SET 0x00000008
64 #define SPI_CS_CPOL_CLR 0xfffffff7
65 #define SPI_CS_CPOL_MSB 3
66 #define SPI_CS_CPOL_LSB 3
67 #define SPI_CS_CPHA_BITS 2:2
68 #define SPI_CS_CPHA_SET 0x00000004
69 #define SPI_CS_CPHA_CLR 0xfffffffb
70 #define SPI_CS_CPHA_MSB 2
71 #define SPI_CS_CPHA_LSB 2
72 #define SPI_FIFO HW_REGISTER_RW( 0x7e204004 )
73 #define SPI_FIFO_MASK 0x000000ff
74 #define SPI_FIFO_WIDTH 8
75 #define SPI_FIFO_RESET 0000000000
76 #define SPI_FIFO_DATA_BITS 7:0
77 #define SPI_FIFO_DATA_SET 0x000000ff
78 #define SPI_FIFO_DATA_CLR 0xffffff00
79 #define SPI_FIFO_DATA_MSB 7
80 #define SPI_FIFO_DATA_LSB 0
81 #define SPI_CLK HW_REGISTER_RW( 0x7e204008 )
82 #define SPI_CLK_MASK 0x0000ffff
83 #define SPI_CLK_WIDTH 16
84 #define SPI_CLK_RESET 0000000000
85 #define SPI_CLK_CDIV_BITS 15:0
86 #define SPI_CLK_CDIV_SET 0x0000ffff
87 #define SPI_CLK_CDIV_CLR 0xffff0000
88 #define SPI_CLK_CDIV_MSB 15
89 #define SPI_CLK_CDIV_LSB 0
90 #define SPI_DLEN HW_REGISTER_RW( 0x7e20400c )
91 #define SPI_DLEN_MASK 0x0000ffff
92 #define SPI_DLEN_WIDTH 16
93 #define SPI_DLEN_RESET 0000000000
94 #define SPI_DLEN_LEN_BITS 15:0
95 #define SPI_DLEN_LEN_SET 0x0000ffff
96 #define SPI_DLEN_LEN_CLR 0xffff0000
97 #define SPI_DLEN_LEN_MSB 15
98 #define SPI_DLEN_LEN_LSB 0
99 #define SPI_LTOH HW_REGISTER_RW( 0x7e204010 )
100 #define SPI_LTOH_MASK 0x0000000f
101 #define SPI_LTOH_WIDTH 4
102 #define SPI_LTOH_RESET 0x00000001
103 #define SPI_LTOH_TOH_BITS 3:0
104 #define SPI_LTOH_TOH_SET 0x0000000f
105 #define SPI_LTOH_TOH_CLR 0xfffffff0
106 #define SPI_LTOH_TOH_MSB 3
107 #define SPI_LTOH_TOH_LSB 0
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