Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / system_arbiter_ctrl.h
1 // This file was generated by the create_regs script
2 #define SYSAC_BASE 0x7e009000
3 #define SYSAC_APB_ID 0x4152424d
4 #define SYSAC_HOST_PRIORITY HW_REGISTER_RW( 0x7e009000 )
5 #define SYSAC_HOST_PRIORITY_MASK 0x0000000f
6 #define SYSAC_HOST_PRIORITY_WIDTH 4
7 #define SYSAC_HOST_PRIORITY_RESET 0000000000
8 #define SYSAC_HOST_PRIORITY_PRIORITY_BITS 3:0
9 #define SYSAC_HOST_PRIORITY_PRIORITY_SET 0x0000000f
10 #define SYSAC_HOST_PRIORITY_PRIORITY_CLR 0xfffffff0
11 #define SYSAC_HOST_PRIORITY_PRIORITY_MSB 3
12 #define SYSAC_HOST_PRIORITY_PRIORITY_LSB 0
13 #define SYSAC_HOST_PRIORITY_PRIORITY_RESET 0x0
14 #define SYSAC_DBG_PRIORITY HW_REGISTER_RW( 0x7e009004 )
15 #define SYSAC_DBG_PRIORITY_MASK 0x0000000f
16 #define SYSAC_DBG_PRIORITY_WIDTH 4
17 #define SYSAC_DBG_PRIORITY_RESET 0000000000
18 #define SYSAC_DBG_PRIORITY_PRIORITY_BITS 3:0
19 #define SYSAC_DBG_PRIORITY_PRIORITY_SET 0x0000000f
20 #define SYSAC_DBG_PRIORITY_PRIORITY_CLR 0xfffffff0
21 #define SYSAC_DBG_PRIORITY_PRIORITY_MSB 3
22 #define SYSAC_DBG_PRIORITY_PRIORITY_LSB 0
23 #define SYSAC_DBG_PRIORITY_PRIORITY_RESET 0x0
24 #define SYSAC_HVSM_PRIORITY HW_REGISTER_RW( 0x7e009008 )
25 #define SYSAC_HVSM_PRIORITY_MASK 0x000000ff
26 #define SYSAC_HVSM_PRIORITY_WIDTH 8
27 #define SYSAC_HVSM_PRIORITY_RESET 0000000000
28 #define SYSAC_HVSM_PRIORITY_P_PRIORITY_BITS 7:4
29 #define SYSAC_HVSM_PRIORITY_P_PRIORITY_SET 0x000000f0
30 #define SYSAC_HVSM_PRIORITY_P_PRIORITY_CLR 0xffffff0f
31 #define SYSAC_HVSM_PRIORITY_P_PRIORITY_MSB 7
32 #define SYSAC_HVSM_PRIORITY_P_PRIORITY_LSB 4
33 #define SYSAC_HVSM_PRIORITY_P_PRIORITY_RESET 0x0
34 #define SYSAC_HVSM_PRIORITY_N_PRIORITY_BITS 3:0
35 #define SYSAC_HVSM_PRIORITY_N_PRIORITY_SET 0x0000000f
36 #define SYSAC_HVSM_PRIORITY_N_PRIORITY_CLR 0xfffffff0
37 #define SYSAC_HVSM_PRIORITY_N_PRIORITY_MSB 3
38 #define SYSAC_HVSM_PRIORITY_N_PRIORITY_LSB 0
39 #define SYSAC_HVSM_PRIORITY_N_PRIORITY_RESET 0x0
40 #define SYSAC_V3D_PRIORITY HW_REGISTER_RW( 0x7e00900c )
41 #define SYSAC_V3D_PRIORITY_MASK 0x0000000f
42 #define SYSAC_V3D_PRIORITY_WIDTH 4
43 #define SYSAC_V3D_PRIORITY_RESET 0000000000
44 #define SYSAC_V3D_PRIORITY_PRIORITY_BITS 3:0
45 #define SYSAC_V3D_PRIORITY_PRIORITY_SET 0x0000000f
46 #define SYSAC_V3D_PRIORITY_PRIORITY_CLR 0xfffffff0
47 #define SYSAC_V3D_PRIORITY_PRIORITY_MSB 3
48 #define SYSAC_V3D_PRIORITY_PRIORITY_LSB 0
49 #define SYSAC_V3D_PRIORITY_PRIORITY_RESET 0x0
50 #define SYSAC_H264_PRIORITY HW_REGISTER_RW( 0x7e009010 )
51 #define SYSAC_H264_PRIORITY_MASK 0x0000000f
52 #define SYSAC_H264_PRIORITY_WIDTH 4
53 #define SYSAC_H264_PRIORITY_RESET 0000000000
54 #define SYSAC_H264_PRIORITY_PRIORITY_BITS 3:0
55 #define SYSAC_H264_PRIORITY_PRIORITY_SET 0x0000000f
56 #define SYSAC_H264_PRIORITY_PRIORITY_CLR 0xfffffff0
57 #define SYSAC_H264_PRIORITY_PRIORITY_MSB 3
58 #define SYSAC_H264_PRIORITY_PRIORITY_LSB 0
59 #define SYSAC_H264_PRIORITY_PRIORITY_RESET 0x0
60 #define SYSAC_JPEG_PRIORITY HW_REGISTER_RW( 0x7e009014 )
61 #define SYSAC_JPEG_PRIORITY_MASK 0x000000ff
62 #define SYSAC_JPEG_PRIORITY_WIDTH 8
63 #define SYSAC_JPEG_PRIORITY_RESET 0000000000
64 #define SYSAC_JPEG_PRIORITY_P_PRIORITY_BITS 7:4
65 #define SYSAC_JPEG_PRIORITY_P_PRIORITY_SET 0x000000f0
66 #define SYSAC_JPEG_PRIORITY_P_PRIORITY_CLR 0xffffff0f
67 #define SYSAC_JPEG_PRIORITY_P_PRIORITY_MSB 7
68 #define SYSAC_JPEG_PRIORITY_P_PRIORITY_LSB 4
69 #define SYSAC_JPEG_PRIORITY_P_PRIORITY_RESET 0x0
70 #define SYSAC_JPEG_PRIORITY_N_PRIORITY_BITS 3:0
71 #define SYSAC_JPEG_PRIORITY_N_PRIORITY_SET 0x0000000f
72 #define SYSAC_JPEG_PRIORITY_N_PRIORITY_CLR 0xfffffff0
73 #define SYSAC_JPEG_PRIORITY_N_PRIORITY_MSB 3
74 #define SYSAC_JPEG_PRIORITY_N_PRIORITY_LSB 0
75 #define SYSAC_JPEG_PRIORITY_N_PRIORITY_RESET 0x0
76 #define SYSAC_TRANS_PRIORITY HW_REGISTER_RW( 0x7e009018 )
77 #define SYSAC_TRANS_PRIORITY_MASK 0x000000ff
78 #define SYSAC_TRANS_PRIORITY_WIDTH 8
79 #define SYSAC_TRANS_PRIORITY_RESET 0000000000
80 #define SYSAC_TRANS_PRIORITY_P_PRIORITY_BITS 7:4
81 #define SYSAC_TRANS_PRIORITY_P_PRIORITY_SET 0x000000f0
82 #define SYSAC_TRANS_PRIORITY_P_PRIORITY_CLR 0xffffff0f
83 #define SYSAC_TRANS_PRIORITY_P_PRIORITY_MSB 7
84 #define SYSAC_TRANS_PRIORITY_P_PRIORITY_LSB 4
85 #define SYSAC_TRANS_PRIORITY_P_PRIORITY_RESET 0x0
86 #define SYSAC_TRANS_PRIORITY_N_PRIORITY_BITS 3:0
87 #define SYSAC_TRANS_PRIORITY_N_PRIORITY_SET 0x0000000f
88 #define SYSAC_TRANS_PRIORITY_N_PRIORITY_CLR 0xfffffff0
89 #define SYSAC_TRANS_PRIORITY_N_PRIORITY_MSB 3
90 #define SYSAC_TRANS_PRIORITY_N_PRIORITY_LSB 0
91 #define SYSAC_TRANS_PRIORITY_N_PRIORITY_RESET 0x0
92 #define SYSAC_ISP_PRIORITY HW_REGISTER_RW( 0x7e00901c )
93 #define SYSAC_ISP_PRIORITY_MASK 0x0000000f
94 #define SYSAC_ISP_PRIORITY_WIDTH 4
95 #define SYSAC_ISP_PRIORITY_RESET 0000000000
96 #define SYSAC_ISP_PRIORITY_PRIORITY_BITS 3:0
97 #define SYSAC_ISP_PRIORITY_PRIORITY_SET 0x0000000f
98 #define SYSAC_ISP_PRIORITY_PRIORITY_CLR 0xfffffff0
99 #define SYSAC_ISP_PRIORITY_PRIORITY_MSB 3
100 #define SYSAC_ISP_PRIORITY_PRIORITY_LSB 0
101 #define SYSAC_ISP_PRIORITY_PRIORITY_RESET 0x0
102 #define SYSAC_USB_PRIORITY HW_REGISTER_RW( 0x7e009020 )
103 #define SYSAC_USB_PRIORITY_MASK 0x0000000f
104 #define SYSAC_USB_PRIORITY_WIDTH 4
105 #define SYSAC_USB_PRIORITY_RESET 0000000000
106 #define SYSAC_USB_PRIORITY_PRIORITY_BITS 3:0
107 #define SYSAC_USB_PRIORITY_PRIORITY_SET 0x0000000f
108 #define SYSAC_USB_PRIORITY_PRIORITY_CLR 0xfffffff0
109 #define SYSAC_USB_PRIORITY_PRIORITY_MSB 3
110 #define SYSAC_USB_PRIORITY_PRIORITY_LSB 0
111 #define SYSAC_USB_PRIORITY_PRIORITY_RESET 0x0
112 #define SYSAC_L2_ARBITER_CONTROL HW_REGISTER_RW( 0x7e009040 )
113 #define SYSAC_L2_ARBITER_CONTROL_MASK 0x0000ffff
114 #define SYSAC_L2_ARBITER_CONTROL_WIDTH 16
115 #define SYSAC_L2_ARBITER_CONTROL_RESET 0000000000
116 #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
117 #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
118 #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
119 #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
120 #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
121 #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
122 #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_BITS 7:6
123 #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
124 #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
125 #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_MSB 7
126 #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_LSB 6
127 #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_RESET 0x0
128 #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_BITS 5:4
129 #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
130 #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
131 #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_MSB 5
132 #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_LSB 4
133 #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_RESET 0x0
134 #define SYSAC_L2_ARBITER_CONTROL_DELAY_BITS 3:2
135 #define SYSAC_L2_ARBITER_CONTROL_DELAY_SET 0x0000000c
136 #define SYSAC_L2_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
137 #define SYSAC_L2_ARBITER_CONTROL_DELAY_MSB 3
138 #define SYSAC_L2_ARBITER_CONTROL_DELAY_LSB 2
139 #define SYSAC_L2_ARBITER_CONTROL_DELAY_RESET 0x0
140 #define SYSAC_L2_ARBITER_CONTROL_LIMIT_BITS 1:0
141 #define SYSAC_L2_ARBITER_CONTROL_LIMIT_SET 0x00000003
142 #define SYSAC_L2_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
143 #define SYSAC_L2_ARBITER_CONTROL_LIMIT_MSB 1
144 #define SYSAC_L2_ARBITER_CONTROL_LIMIT_LSB 0
145 #define SYSAC_L2_ARBITER_CONTROL_LIMIT_RESET 0x0
146 #define SYSAC_UC_ARBITER_CONTROL HW_REGISTER_RW( 0x7e009044 )
147 #define SYSAC_UC_ARBITER_CONTROL_MASK 0x0000ffff
148 #define SYSAC_UC_ARBITER_CONTROL_WIDTH 16
149 #define SYSAC_UC_ARBITER_CONTROL_RESET 0000000000
150 #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
151 #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
152 #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
153 #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
154 #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
155 #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
156 #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_BITS 7:6
157 #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
158 #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
159 #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_MSB 7
160 #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_LSB 6
161 #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_RESET 0x0
162 #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_BITS 5:4
163 #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
164 #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
165 #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_MSB 5
166 #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_LSB 4
167 #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_RESET 0x0
168 #define SYSAC_UC_ARBITER_CONTROL_DELAY_BITS 3:2
169 #define SYSAC_UC_ARBITER_CONTROL_DELAY_SET 0x0000000c
170 #define SYSAC_UC_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
171 #define SYSAC_UC_ARBITER_CONTROL_DELAY_MSB 3
172 #define SYSAC_UC_ARBITER_CONTROL_DELAY_LSB 2
173 #define SYSAC_UC_ARBITER_CONTROL_DELAY_RESET 0x0
174 #define SYSAC_UC_ARBITER_CONTROL_LIMIT_BITS 1:0
175 #define SYSAC_UC_ARBITER_CONTROL_LIMIT_SET 0x00000003
176 #define SYSAC_UC_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
177 #define SYSAC_UC_ARBITER_CONTROL_LIMIT_MSB 1
178 #define SYSAC_UC_ARBITER_CONTROL_LIMIT_LSB 0
179 #define SYSAC_UC_ARBITER_CONTROL_LIMIT_RESET 0x0
180 #define SYSAC_SRC_ARBITER_CONTROL HW_REGISTER_RW( 0x7e009048 )
181 #define SYSAC_SRC_ARBITER_CONTROL_MASK 0x0000ffff
182 #define SYSAC_SRC_ARBITER_CONTROL_WIDTH 16
183 #define SYSAC_SRC_ARBITER_CONTROL_RESET 0000000000
184 #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
185 #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
186 #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
187 #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
188 #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
189 #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
190 #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_BITS 7:6
191 #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
192 #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
193 #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_MSB 7
194 #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_LSB 6
195 #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_RESET 0x0
196 #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_BITS 5:4
197 #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
198 #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
199 #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_MSB 5
200 #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_LSB 4
201 #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_RESET 0x0
202 #define SYSAC_SRC_ARBITER_CONTROL_DELAY_BITS 3:2
203 #define SYSAC_SRC_ARBITER_CONTROL_DELAY_SET 0x0000000c
204 #define SYSAC_SRC_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
205 #define SYSAC_SRC_ARBITER_CONTROL_DELAY_MSB 3
206 #define SYSAC_SRC_ARBITER_CONTROL_DELAY_LSB 2
207 #define SYSAC_SRC_ARBITER_CONTROL_DELAY_RESET 0x0
208 #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_BITS 1:0
209 #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_SET 0x00000003
210 #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
211 #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_MSB 1
212 #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_LSB 0
213 #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_RESET 0x0
214 #define SYSAC_PERI_ARBITER_CONTROL HW_REGISTER_RW( 0x7e00904c )
215 #define SYSAC_PERI_ARBITER_CONTROL_MASK 0x0000ffff
216 #define SYSAC_PERI_ARBITER_CONTROL_WIDTH 16
217 #define SYSAC_PERI_ARBITER_CONTROL_RESET 0000000000
218 #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
219 #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
220 #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
221 #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
222 #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
223 #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
224 #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_BITS 7:6
225 #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
226 #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
227 #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_MSB 7
228 #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_LSB 6
229 #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_RESET 0x0
230 #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_BITS 5:4
231 #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
232 #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
233 #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_MSB 5
234 #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_LSB 4
235 #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_RESET 0x0
236 #define SYSAC_PERI_ARBITER_CONTROL_DELAY_BITS 3:2
237 #define SYSAC_PERI_ARBITER_CONTROL_DELAY_SET 0x0000000c
238 #define SYSAC_PERI_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
239 #define SYSAC_PERI_ARBITER_CONTROL_DELAY_MSB 3
240 #define SYSAC_PERI_ARBITER_CONTROL_DELAY_LSB 2
241 #define SYSAC_PERI_ARBITER_CONTROL_DELAY_RESET 0x0
242 #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_BITS 1:0
243 #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_SET 0x00000003
244 #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
245 #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_MSB 1
246 #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_LSB 0
247 #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_RESET 0x0
248 #define SYSAC_DMA_ARBITER_CONTROL_UC HW_REGISTER_RW( 0x7e009050 )
249 #define SYSAC_DMA_ARBITER_CONTROL_UC_MASK 0x0000ffff
250 #define SYSAC_DMA_ARBITER_CONTROL_UC_WIDTH 16
251 #define SYSAC_DMA_ARBITER_CONTROL_UC_RESET 0000000000
252 #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_BITS 15:8
253 #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_SET 0x0000ff00
254 #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_CLR 0xffff00ff
255 #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_MSB 15
256 #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_LSB 8
257 #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_RESET 0x0
258 #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_BITS 7:6
259 #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_SET 0x000000c0
260 #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_CLR 0xffffff3f
261 #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_MSB 7
262 #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_LSB 6
263 #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_RESET 0x0
264 #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_BITS 5:4
265 #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_SET 0x00000030
266 #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_CLR 0xffffffcf
267 #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_MSB 5
268 #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_LSB 4
269 #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_RESET 0x0
270 #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_BITS 3:2
271 #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_SET 0x0000000c
272 #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_CLR 0xfffffff3
273 #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_MSB 3
274 #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_LSB 2
275 #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_RESET 0x0
276 #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_BITS 1:0
277 #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_SET 0x00000003
278 #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_CLR 0xfffffffc
279 #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_MSB 1
280 #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_LSB 0
281 #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_RESET 0x0
282 #define SYSAC_DMA_ARBITER_CONTROL_L2 HW_REGISTER_RW( 0x7e009054 )
283 #define SYSAC_DMA_ARBITER_CONTROL_L2_MASK 0x0000ffff
284 #define SYSAC_DMA_ARBITER_CONTROL_L2_WIDTH 16
285 #define SYSAC_DMA_ARBITER_CONTROL_L2_RESET 0000000000
286 #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_BITS 7:6
287 #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_SET 0x000000c0
288 #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_CLR 0xffffff3f
289 #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_MSB 7
290 #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_LSB 6
291 #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_RESET 0x0
292 #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_BITS 5:4
293 #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_SET 0x00000030
294 #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_CLR 0xffffffcf
295 #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_MSB 5
296 #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_LSB 4
297 #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_RESET 0x0
298 #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_BITS 3:2
299 #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_SET 0x0000000c
300 #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_CLR 0xfffffff3
301 #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_MSB 3
302 #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_LSB 2
303 #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_RESET 0x0
304 #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_BITS 1:0
305 #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_SET 0x00000003
306 #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_CLR 0xfffffffc
307 #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_MSB 1
308 #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_LSB 0
309 #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_RESET 0x0
310 #define SYSAC_DMA_ARBITER_CONTROL_PER HW_REGISTER_RW( 0x7e009058 )
311 #define SYSAC_DMA_ARBITER_CONTROL_PER_MASK 0x0000ffff
312 #define SYSAC_DMA_ARBITER_CONTROL_PER_WIDTH 16
313 #define SYSAC_DMA_ARBITER_CONTROL_PER_RESET 0000000000
314 #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_BITS 15:8
315 #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_SET 0x0000ff00
316 #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_CLR 0xffff00ff
317 #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_MSB 15
318 #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_LSB 8
319 #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_RESET 0x0
320 #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_BITS 7:6
321 #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_SET 0x000000c0
322 #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_CLR 0xffffff3f
323 #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_MSB 7
324 #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_LSB 6
325 #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_RESET 0x0
326 #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_BITS 5:4
327 #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_SET 0x00000030
328 #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_CLR 0xffffffcf
329 #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_MSB 5
330 #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_LSB 4
331 #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_RESET 0x0
332 #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_BITS 3:2
333 #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_SET 0x0000000c
334 #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_CLR 0xfffffff3
335 #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_MSB 3
336 #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_LSB 2
337 #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_RESET 0x0
338 #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_BITS 1:0
339 #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_SET 0x00000003
340 #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_CLR 0xfffffffc
341 #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_MSB 1
342 #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_LSB 0
343 #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_RESET 0x0
344 #define SYSAC_DMA_ARBITER_CONTROL_LITE HW_REGISTER_RW( 0x7e00905c )
345 #define SYSAC_DMA_ARBITER_CONTROL_LITE_MASK 0x0000ffff
346 #define SYSAC_DMA_ARBITER_CONTROL_LITE_WIDTH 16
347 #define SYSAC_DMA_ARBITER_CONTROL_LITE_RESET 0000000000
348 #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_BITS 15:8
349 #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_SET 0x0000ff00
350 #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_CLR 0xffff00ff
351 #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_MSB 15
352 #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_LSB 8
353 #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_RESET0x0
354 #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_BITS 7:6
355 #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_SET 0x000000c0
356 #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_CLR 0xffffff3f
357 #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_MSB 7
358 #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_LSB 6
359 #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_RESET 0x0
360 #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_BITS 5:4
361 #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_SET 0x00000030
362 #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_CLR 0xffffffcf
363 #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_MSB 5
364 #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_LSB 4
365 #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_RESET 0x0
366 #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_BITS 3:2
367 #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_SET 0x0000000c
368 #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_CLR 0xfffffff3
369 #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_MSB 3
370 #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_LSB 2
371 #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_RESET 0x0
372 #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_BITS 1:0
373 #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_SET 0x00000003
374 #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_CLR 0xfffffffc
375 #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_MSB 1
376 #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_LSB 0
377 #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_RESET 0x0
378 #define SYSAC_DUMMY_STATUS HW_REGISTER_RW( 0x7e009060 )
379 #define SYSAC_DUMMY_STATUS_MASK 0x00000001
380 #define SYSAC_DUMMY_STATUS_WIDTH 1
381 #define SYSAC_DUMMY_STATUS_RESET 0000000000
382 #define SYSAC_DUMMY_STATUS_IDLE_BITS 0:0
383 #define SYSAC_DUMMY_STATUS_IDLE_SET 0x00000001
384 #define SYSAC_DUMMY_STATUS_IDLE_CLR 0xfffffffe
385 #define SYSAC_DUMMY_STATUS_IDLE_MSB 0
386 #define SYSAC_DUMMY_STATUS_IDLE_LSB 0
387 #define SYSAC_DUMMY_STATUS_IDLE_RESET 0x0
388 #define SYSAC_DMA_DREQ_CONTROL HW_REGISTER_RW( 0x7e009064 )
389 #define SYSAC_DMA_DREQ_CONTROL_MASK 0x0000000f
390 #define SYSAC_DMA_DREQ_CONTROL_WIDTH 4
391 #define SYSAC_DMA_DREQ_CONTROL_RESET 0000000000
392 #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_BITS 2:0
393 #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_SET 0x00000007
394 #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_CLR 0xfffffff8
395 #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_MSB 2
396 #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_LSB 0
397 #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_RESET 0x0
398 #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_BITS 3:3
399 #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_SET 0x00000008
400 #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_CLR 0xfffffff7
401 #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_MSB 3
402 #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_LSB 3
403 #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_RESET 0x0
404 #define SYSAC_V3D_LIMITER HW_REGISTER_RW( 0x7e009068 )
405 #define SYSAC_V3D_LIMITER_MASK 0x00000fff
406 #define SYSAC_V3D_LIMITER_WIDTH 12
407 #define SYSAC_V3D_LIMITER_RESET 0000000000
408 #define SYSAC_V3D_LIMITER_ENABLE_BITS 0:0
409 #define SYSAC_V3D_LIMITER_ENABLE_SET 0x00000001
410 #define SYSAC_V3D_LIMITER_ENABLE_CLR 0xfffffffe
411 #define SYSAC_V3D_LIMITER_ENABLE_MSB 0
412 #define SYSAC_V3D_LIMITER_ENABLE_LSB 0
413 #define SYSAC_V3D_LIMITER_ENABLE_RESET 0x0
414 #define SYSAC_V3D_LIMITER_SPARE_BITS 3:1
415 #define SYSAC_V3D_LIMITER_SPARE_SET 0x0000000e
416 #define SYSAC_V3D_LIMITER_SPARE_CLR 0xfffffff1
417 #define SYSAC_V3D_LIMITER_SPARE_MSB 3
418 #define SYSAC_V3D_LIMITER_SPARE_LSB 1
419 #define SYSAC_V3D_LIMITER_SPARE_RESET 0x0
420 #define SYSAC_V3D_LIMITER_MAX_PRIORITY_BITS 7:3
421 #define SYSAC_V3D_LIMITER_MAX_PRIORITY_SET 0x000000f8
422 #define SYSAC_V3D_LIMITER_MAX_PRIORITY_CLR 0xffffff07
423 #define SYSAC_V3D_LIMITER_MAX_PRIORITY_MSB 7
424 #define SYSAC_V3D_LIMITER_MAX_PRIORITY_LSB 3
425 #define SYSAC_V3D_LIMITER_MAX_PRIORITY_RESET 0x0
426 #define SYSAC_V3D_LIMITER_INCREMENT_BITS 0:0
427 #define SYSAC_V3D_LIMITER_INCREMENT_SET 0x00000001
428 #define SYSAC_V3D_LIMITER_INCREMENT_CLR 0xfffffffe
429 #define SYSAC_V3D_LIMITER_INCREMENT_MSB 0
430 #define SYSAC_V3D_LIMITER_INCREMENT_LSB 0
431 #define SYSAC_V3D_LIMITER_INCREMENT_RESET 0x0
432 #define SYSAC_V3D_LIMITER_HOLDOFF_BITS 0:0
433 #define SYSAC_V3D_LIMITER_HOLDOFF_SET 0x00000001
434 #define SYSAC_V3D_LIMITER_HOLDOFF_CLR 0xfffffffe
435 #define SYSAC_V3D_LIMITER_HOLDOFF_MSB 0
436 #define SYSAC_V3D_LIMITER_HOLDOFF_LSB 0
437 #define SYSAC_V3D_LIMITER_HOLDOFF_RESET 0x0
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