Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / tempsens.h
1 // This file was generated by the create_regs script
2 #define TS_BASE 0x7e212000
3 #define TS_APB_ID 0x7473656e
4 #define TS_TSENSCTL HW_REGISTER_RW( 0x7e212000 )
5 #define TS_TSENSCTL_MASK 0x07ffffff
6 #define TS_TSENSCTL_WIDTH 27
7 #define TS_TSENSCTL_RESET 0000000000
8 #define TS_TSENSCTL_PRWDW_BITS 0:0
9 #define TS_TSENSCTL_PRWDW_SET 0x00000001
10 #define TS_TSENSCTL_PRWDW_CLR 0xfffffffe
11 #define TS_TSENSCTL_PRWDW_MSB 0
12 #define TS_TSENSCTL_PRWDW_LSB 0
13 #define TS_TSENSCTL_RSTB_BITS 1:1
14 #define TS_TSENSCTL_RSTB_SET 0x00000002
15 #define TS_TSENSCTL_RSTB_CLR 0xfffffffd
16 #define TS_TSENSCTL_RSTB_MSB 1
17 #define TS_TSENSCTL_RSTB_LSB 1
18 #define TS_TSENSCTL_CTRL_BITS 4:2
19 #define TS_TSENSCTL_CTRL_SET 0x0000001c
20 #define TS_TSENSCTL_CTRL_CLR 0xffffffe3
21 #define TS_TSENSCTL_CTRL_MSB 4
22 #define TS_TSENSCTL_CTRL_LSB 2
23 #define TS_TSENSCTL_EN_INT_BITS 5:5
24 #define TS_TSENSCTL_EN_INT_SET 0x00000020
25 #define TS_TSENSCTL_EN_INT_CLR 0xffffffdf
26 #define TS_TSENSCTL_EN_INT_MSB 5
27 #define TS_TSENSCTL_EN_INT_LSB 5
28 #define TS_TSENSCTL_DIRECT_BITS 6:6
29 #define TS_TSENSCTL_DIRECT_SET 0x00000040
30 #define TS_TSENSCTL_DIRECT_CLR 0xffffffbf
31 #define TS_TSENSCTL_DIRECT_MSB 6
32 #define TS_TSENSCTL_DIRECT_LSB 6
33 #define TS_TSENSCTL_CLR_INT_BITS 7:7
34 #define TS_TSENSCTL_CLR_INT_SET 0x00000080
35 #define TS_TSENSCTL_CLR_INT_CLR 0xffffff7f
36 #define TS_TSENSCTL_CLR_INT_MSB 7
37 #define TS_TSENSCTL_CLR_INT_LSB 7
38 #define TS_TSENSCTL_THOLD_BITS 17:8
39 #define TS_TSENSCTL_THOLD_SET 0x0003ff00
40 #define TS_TSENSCTL_THOLD_CLR 0xfffc00ff
41 #define TS_TSENSCTL_THOLD_MSB 17
42 #define TS_TSENSCTL_THOLD_LSB 8
43 #define TS_TSENSCTL_RSTDELAY_BITS 25:18
44 #define TS_TSENSCTL_RSTDELAY_SET 0x03fc0000
45 #define TS_TSENSCTL_RSTDELAY_CLR 0xfc03ffff
46 #define TS_TSENSCTL_RSTDELAY_MSB 25
47 #define TS_TSENSCTL_RSTDELAY_LSB 18
48 #define TS_TSENSCTL_REGULEN_BITS 26:26
49 #define TS_TSENSCTL_REGULEN_SET 0x04000000
50 #define TS_TSENSCTL_REGULEN_CLR 0xfbffffff
51 #define TS_TSENSCTL_REGULEN_MSB 26
52 #define TS_TSENSCTL_REGULEN_LSB 26
53 #define TS_TSENSSTAT HW_REGISTER_RW( 0x7e212004 )
54 #define TS_TSENSSTAT_MASK 0x00000fff
55 #define TS_TSENSSTAT_WIDTH 12
56 #define TS_TSENSSTAT_RESET 0000000000
57 #define TS_TSENSSTAT_DATA_BITS 9:0
58 #define TS_TSENSSTAT_DATA_SET 0x000003ff
59 #define TS_TSENSSTAT_DATA_CLR 0xfffffc00
60 #define TS_TSENSSTAT_DATA_MSB 9
61 #define TS_TSENSSTAT_DATA_LSB 0
62 #define TS_TSENSSTAT_VALID_BITS 10:10
63 #define TS_TSENSSTAT_VALID_SET 0x00000400
64 #define TS_TSENSSTAT_VALID_CLR 0xfffffbff
65 #define TS_TSENSSTAT_VALID_MSB 10
66 #define TS_TSENSSTAT_VALID_LSB 10
67 #define TS_TSENSSTAT_INTERUPT_BITS 11:11
68 #define TS_TSENSSTAT_INTERUPT_SET 0x00000800
69 #define TS_TSENSSTAT_INTERUPT_CLR 0xfffff7ff
70 #define TS_TSENSSTAT_INTERUPT_MSB 11
71 #define TS_TSENSSTAT_INTERUPT_LSB 11
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