9245135b97bd7d4486e01a11531f49be1b142653
[rpi-open-firmware.git] / bcm2708_chip / testbus.h
1 // This file was generated by the create_regs script
2 #define TB_BASE 0x7e20b000
3 #define TB_ADDR HW_REGISTER_RW( 0x7e20b000 )
4 #define TB_ADDR_MASK 0xffffffff
5 #define TB_ADDR_WIDTH 32
6 #define TB_TASK HW_REGISTER_RW( 0x7e20b000 )
7 #define TB_TASK_MASK 0x0001ffff
8 #define TB_TASK_WIDTH 17
9 #define TB_TASK_NUM_BITS 15:0
10 #define TB_TASK_NUM_SET 0x0000ffff
11 #define TB_TASK_NUM_CLR 0xffff0000
12 #define TB_TASK_NUM_MSB 15
13 #define TB_TASK_NUM_LSB 0
14 #define TB_TASK_TEXT_FLAG_BITS 16:16
15 #define TB_TASK_TEXT_FLAG_SET 0x00010000
16 #define TB_TASK_TEXT_FLAG_CLR 0xfffeffff
17 #define TB_TASK_TEXT_FLAG_MSB 16
18 #define TB_TASK_TEXT_FLAG_LSB 16
19 #define TB_TASK_PARAM1 HW_REGISTER_RW( 0x7e20b004 )
20 #define TB_TASK_PARAM1_MASK 0xffffffff
21 #define TB_TASK_PARAM1_WIDTH 32
22 #define TB_TASK_PARAM2 HW_REGISTER_RW( 0x7e20b008 )
23 #define TB_TASK_PARAM2_MASK 0xffffffff
24 #define TB_TASK_PARAM2_WIDTH 32
25 #define TB_TASK_PARAM3 HW_REGISTER_RW( 0x7e20b00c )
26 #define TB_TASK_PARAM3_MASK 0xffffffff
27 #define TB_TASK_PARAM3_WIDTH 32
28 #define TB_TASK_STATUS HW_REGISTER_RW( 0x7e20b080 )
29 #define TB_TASK_STATUS_MASK 0xffffffff
30 #define TB_TASK_STATUS_WIDTH 32
31 #define TB_TASK_RXDATA1 HW_REGISTER_RW( 0x7e20b084 )
32 #define TB_TASK_RXDATA1_MASK 0xffffffff
33 #define TB_TASK_RXDATA1_WIDTH 32
34 #define TB_TASK_RXDATA2 HW_REGISTER_RW( 0x7e20b088 )
35 #define TB_TASK_RXDATA2_MASK 0xffffffff
36 #define TB_TASK_RXDATA2_WIDTH 32
37 #define TB_TASK_TXTCLR HW_REGISTER_RW( 0x7e20b0f0 )
38 #define TB_TASK_TXTCLR_MASK 0xffffffff
39 #define TB_TASK_TXTCLR_WIDTH 32
40 #define TB_HDMI HW_REGISTER_RW( 0x7e20b100 )
41 #define TB_HDMI_MASK 0xffffffff
42 #define TB_HDMI_WIDTH 32
43 #define TB_PCM HW_REGISTER_RW( 0x7e20b200 )
44 #define TB_PCM_MASK 0xffffffff
45 #define TB_PCM_WIDTH 32
46 #define TB_HOST HW_REGISTER_RW( 0x7e20b300 )
47 #define TB_HOST_MASK 0xffffffff
48 #define TB_HOST_WIDTH 32
49 #define TB_PRINTER_CTRL HW_REGISTER_RW( 0x7e20b400 )
50 #define TB_PRINTER_CTRL_MASK 0x0000fff3
51 #define TB_PRINTER_CTRL_WIDTH 16
52 #define TB_PRINTER_CTRL_TASKNO_BITS 15:4
53 #define TB_PRINTER_CTRL_TASKNO_SET 0x0000fff0
54 #define TB_PRINTER_CTRL_TASKNO_CLR 0xffff000f
55 #define TB_PRINTER_CTRL_TASKNO_MSB 15
56 #define TB_PRINTER_CTRL_TASKNO_LSB 4
57 #define TB_PRINTER_CTRL_OFFSET_BITS 1:0
58 #define TB_PRINTER_CTRL_OFFSET_SET 0x00000003
59 #define TB_PRINTER_CTRL_OFFSET_CLR 0xfffffffc
60 #define TB_PRINTER_CTRL_OFFSET_MSB 1
61 #define TB_PRINTER_CTRL_OFFSET_LSB 0
62 #define TB_PRINTER_DATA HW_REGISTER_RW( 0x7e20b404 )
63 #define TB_PRINTER_DATA_MASK 0xffffffff
64 #define TB_PRINTER_DATA_WIDTH 32
65 #define TB_BOOT_ADDR HW_REGISTER_RW( 0x7e20b500 )
66 #define TB_BOOT_ADDR_MASK 0xffffffff
67 #define TB_BOOT_ADDR_WIDTH 32
68 #define TB_BOOT_OPT HW_REGISTER_RW( 0x7e20b504 )
69 #define TB_BOOT_OPT_MASK 0x800007ff
70 #define TB_BOOT_OPT_WIDTH 32
71 #define TB_BOOT_OPT_FAST_OPT_BITS 0:0
72 #define TB_BOOT_OPT_FAST_OPT_SET 0x00000001
73 #define TB_BOOT_OPT_FAST_OPT_CLR 0xfffffffe
74 #define TB_BOOT_OPT_FAST_OPT_MSB 0
75 #define TB_BOOT_OPT_FAST_OPT_LSB 0
76 #define TB_BOOT_OPT_EIGHT_BANK_BITS 1:1
77 #define TB_BOOT_OPT_EIGHT_BANK_SET 0x00000002
78 #define TB_BOOT_OPT_EIGHT_BANK_CLR 0xfffffffd
79 #define TB_BOOT_OPT_EIGHT_BANK_MSB 1
80 #define TB_BOOT_OPT_EIGHT_BANK_LSB 1
81 #define TB_BOOT_OPT_FPGA_BITS 2:2
82 #define TB_BOOT_OPT_FPGA_SET 0x00000004
83 #define TB_BOOT_OPT_FPGA_CLR 0xfffffffb
84 #define TB_BOOT_OPT_FPGA_MSB 2
85 #define TB_BOOT_OPT_FPGA_LSB 2
86 #define TB_BOOT_OPT_TCL_SIM_BITS 3:3
87 #define TB_BOOT_OPT_TCL_SIM_SET 0x00000008
88 #define TB_BOOT_OPT_TCL_SIM_CLR 0xfffffff7
89 #define TB_BOOT_OPT_TCL_SIM_MSB 3
90 #define TB_BOOT_OPT_TCL_SIM_LSB 3
91 #define TB_BOOT_OPT_ELPIDA_BITS 4:4
92 #define TB_BOOT_OPT_ELPIDA_SET 0x00000010
93 #define TB_BOOT_OPT_ELPIDA_CLR 0xffffffef
94 #define TB_BOOT_OPT_ELPIDA_MSB 4
95 #define TB_BOOT_OPT_ELPIDA_LSB 4
96 #define TB_BOOT_OPT_SDC_BEHAV_PHY_BITS 5:5
97 #define TB_BOOT_OPT_SDC_BEHAV_PHY_SET 0x00000020
98 #define TB_BOOT_OPT_SDC_BEHAV_PHY_CLR 0xffffffdf
99 #define TB_BOOT_OPT_SDC_BEHAV_PHY_MSB 5
100 #define TB_BOOT_OPT_SDC_BEHAV_PHY_LSB 5
101 #define TB_BOOT_OPT_NO_PRINT_BITS 6:6
102 #define TB_BOOT_OPT_NO_PRINT_SET 0x00000040
103 #define TB_BOOT_OPT_NO_PRINT_CLR 0xffffffbf
104 #define TB_BOOT_OPT_NO_PRINT_MSB 6
105 #define TB_BOOT_OPT_NO_PRINT_LSB 6
106 #define TB_BOOT_OPT_BOOT_HALT_BITS 7:7
107 #define TB_BOOT_OPT_BOOT_HALT_SET 0x00000080
108 #define TB_BOOT_OPT_BOOT_HALT_CLR 0xffffff7f
109 #define TB_BOOT_OPT_BOOT_HALT_MSB 7
110 #define TB_BOOT_OPT_BOOT_HALT_LSB 7
111 #define TB_BOOT_OPT_BANK_MODE_BITS 9:8
112 #define TB_BOOT_OPT_BANK_MODE_SET 0x00000300
113 #define TB_BOOT_OPT_BANK_MODE_CLR 0xfffffcff
114 #define TB_BOOT_OPT_BANK_MODE_MSB 9
115 #define TB_BOOT_OPT_BANK_MODE_LSB 8
116 #define TB_BOOT_OPT_DONT_SET_VPU_CLK_BITS 10:10
117 #define TB_BOOT_OPT_DONT_SET_VPU_CLK_SET 0x00000400
118 #define TB_BOOT_OPT_DONT_SET_VPU_CLK_CLR 0xfffffbff
119 #define TB_BOOT_OPT_DONT_SET_VPU_CLK_MSB 10
120 #define TB_BOOT_OPT_DONT_SET_VPU_CLK_LSB 10
121 #define TB_BOOT_OPT_TB_PRESENT_BITS 31:31
122 #define TB_BOOT_OPT_TB_PRESENT_SET 0x80000000
123 #define TB_BOOT_OPT_TB_PRESENT_CLR 0x7fffffff
124 #define TB_BOOT_OPT_TB_PRESENT_MSB 31
125 #define TB_BOOT_OPT_TB_PRESENT_LSB 31
126 #define TB_BOOT_SECURE_MODE HW_REGISTER_RW( 0x7e20b508 )
127 #define TB_BOOT_SECURE_MODE_MASK 0x00000003
128 #define TB_BOOT_SECURE_MODE_WIDTH 2
129 #define TB_BOOT_SECURE_MODE_JTAG_SECURE_BITS 1:0
130 #define TB_BOOT_SECURE_MODE_JTAG_SECURE_SET 0x00000003
131 #define TB_BOOT_SECURE_MODE_JTAG_SECURE_CLR 0xfffffffc
132 #define TB_BOOT_SECURE_MODE_JTAG_SECURE_MSB 1
133 #define TB_BOOT_SECURE_MODE_JTAG_SECURE_LSB 0
134 #define TB_BOOT_STATUS HW_REGISTER_RW( 0x7e20b50c )
135 #define TB_BOOT_STATUS_MASK 0x00000001
136 #define TB_BOOT_STATUS_WIDTH 1
137 #define TB_BOOT_STATUS_CPRMAN_PROGRAMMED_BITS 0:0
138 #define TB_BOOT_STATUS_CPRMAN_PROGRAMMED_SET 0x00000001
139 #define TB_BOOT_STATUS_CPRMAN_PROGRAMMED_CLR 0xfffffffe
140 #define TB_BOOT_STATUS_CPRMAN_PROGRAMMED_MSB 0
141 #define TB_BOOT_STATUS_CPRMAN_PROGRAMMED_LSB 0
142 #define TB_JTB_CONFIG HW_REGISTER_RW( 0x7e20b800 )
143 #define TB_JTB_CONFIG_MASK 0xbfffffff
144 #define TB_JTB_CONFIG_WIDTH 32
145 #define TB_JTB_CONFIG_SBITS_BITS 4:0
146 #define TB_JTB_CONFIG_SBITS_SET 0x0000001f
147 #define TB_JTB_CONFIG_SBITS_CLR 0xffffffe0
148 #define TB_JTB_CONFIG_SBITS_MSB 4
149 #define TB_JTB_CONFIG_SBITS_LSB 0
150 #define TB_JTB_CONFIG_OUT_MS_BITS 6:6
151 #define TB_JTB_CONFIG_OUT_MS_SET 0x00000040
152 #define TB_JTB_CONFIG_OUT_MS_CLR 0xffffffbf
153 #define TB_JTB_CONFIG_OUT_MS_MSB 6
154 #define TB_JTB_CONFIG_OUT_MS_LSB 6
155 #define TB_JTB_CONFIG_INV_CLK_BITS 7:7
156 #define TB_JTB_CONFIG_INV_CLK_SET 0x00000080
157 #define TB_JTB_CONFIG_INV_CLK_CLR 0xffffff7f
158 #define TB_JTB_CONFIG_INV_CLK_MSB 7
159 #define TB_JTB_CONFIG_INV_CLK_LSB 7
160 #define TB_JTB_CONFIG_TMS_RISE_BITS 8:8
161 #define TB_JTB_CONFIG_TMS_RISE_SET 0x00000100
162 #define TB_JTB_CONFIG_TMS_RISE_CLR 0xfffffeff
163 #define TB_JTB_CONFIG_TMS_RISE_MSB 8
164 #define TB_JTB_CONFIG_TMS_RISE_LSB 8
165 #define TB_JTB_CONFIG_TDI_RISE_BITS 9:9
166 #define TB_JTB_CONFIG_TDI_RISE_SET 0x00000200
167 #define TB_JTB_CONFIG_TDI_RISE_CLR 0xfffffdff
168 #define TB_JTB_CONFIG_TDI_RISE_MSB 9
169 #define TB_JTB_CONFIG_TDI_RISE_LSB 9
170 #define TB_JTB_CONFIG_TDO_RISE_BITS 10:10
171 #define TB_JTB_CONFIG_TDO_RISE_SET 0x00000400
172 #define TB_JTB_CONFIG_TDO_RISE_CLR 0xfffffbff
173 #define TB_JTB_CONFIG_TDO_RISE_MSB 10
174 #define TB_JTB_CONFIG_TDO_RISE_LSB 10
175 #define TB_JTB_CONFIG_ENABLE_BITS 11:11
176 #define TB_JTB_CONFIG_ENABLE_SET 0x00000800
177 #define TB_JTB_CONFIG_ENABLE_CLR 0xfffff7ff
178 #define TB_JTB_CONFIG_ENABLE_MSB 11
179 #define TB_JTB_CONFIG_ENABLE_LSB 11
180 #define TB_JTB_CONFIG_D_HOLD_BITS 13:12
181 #define TB_JTB_CONFIG_D_HOLD_SET 0x00003000
182 #define TB_JTB_CONFIG_D_HOLD_CLR 0xffffcfff
183 #define TB_JTB_CONFIG_D_HOLD_MSB 13
184 #define TB_JTB_CONFIG_D_HOLD_LSB 12
185 #define TB_JTB_CONFIG_TRSTN_BITS 14:14
186 #define TB_JTB_CONFIG_TRSTN_SET 0x00004000
187 #define TB_JTB_CONFIG_TRSTN_CLR 0xffffbfff
188 #define TB_JTB_CONFIG_TRSTN_MSB 14
189 #define TB_JTB_CONFIG_TRSTN_LSB 14
190 #define TB_JTB_CONFIG_SPEED_BITS 23:16
191 #define TB_JTB_CONFIG_SPEED_SET 0x00ff0000
192 #define TB_JTB_CONFIG_SPEED_CLR 0xff00ffff
193 #define TB_JTB_CONFIG_SPEED_MSB 23
194 #define TB_JTB_CONFIG_SPEED_LSB 16
195 #define TB_JTB_CONFIG_BITCNT_BITS 29:23
196 #define TB_JTB_CONFIG_BITCNT_SET 0x3f800000
197 #define TB_JTB_CONFIG_BITCNT_CLR 0xc07fffff
198 #define TB_JTB_CONFIG_BITCNT_MSB 29
199 #define TB_JTB_CONFIG_BITCNT_LSB 23
200 #define TB_JTB_CONFIG_BUSY_BITS 31:31
201 #define TB_JTB_CONFIG_BUSY_SET 0x80000000
202 #define TB_JTB_CONFIG_BUSY_CLR 0x7fffffff
203 #define TB_JTB_CONFIG_BUSY_MSB 31
204 #define TB_JTB_CONFIG_BUSY_LSB 31
205 #define TB_JTB_TMS HW_REGISTER_RW( 0x7e20b804 )
206 #define TB_JTB_TMS_MASK 0xffffffff
207 #define TB_JTB_TMS_WIDTH 32
208 #define TB_JTB_TDI HW_REGISTER_RW( 0x7e20b808 )
209 #define TB_JTB_TDI_MASK 0xffffffff
210 #define TB_JTB_TDI_WIDTH 32
211 #define TB_JTB_TDO HW_REGISTER_RO( 0x7e20b80c )
212 #define TB_JTB_TDO_MASK 0xffffffff
213 #define TB_JTB_TDO_WIDTH 32
214 #define TB_JTB_BITCNT HW_REGISTER_RW( 0x7e20b810 )
215 #define TB_JTB_BITCNT_MASK 0x0000003f
216 #define TB_JTB_BITCNT_WIDTH 6
217 #define TB_JTB_PORTEN HW_REGISTER_RW( 0x7e20b814 )
218 #define TB_JTB_PORTEN_MASK 0x000000ff
219 #define TB_JTB_PORTEN_WIDTH 8
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